Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	50319	1			T2	142		T9	59		T10	71
access_err	63631	1			T1	4		T2	150		T4	2
write_blank_err	409	1			T2	5		T5	1		T6	8
ecc_uncorr_err	68742	1			T2	290		T4	263		T5	48
ecc_corr_err	1460	1			T4	2		T7	2		T9	40
no_err	93459	1			T1	35		T2	292		T4	7

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	707	1			T6	37		T12	8		T13	2
secret2	26483	1			T1	2		T2	176		T4	69
secret1	31364	1			T1	3		T2	68		T4	71
secret0	35484	1			T1	5		T2	41		T5	9
hw_cfg1	37768	1			T1	3		T2	23		T5	60
hw_cfg0	25928	1			T1	6		T2	29		T4	4
rot_creator_auth_state	21449	1			T1	4		T2	45		T4	69
rot_creator_auth_codesign	23470	1			T1	5		T2	43		T4	61
owner_sw_cfg	22387	1			T1	9		T2	58		T5	14
creator_sw_cfg	19732	1			T1	1		T2	343		T5	19
vendor_test	33248	1			T1	1		T2	53		T5	33

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4949	1			T2	120		T285	264		T227	134
fsm_err	secret1	5184	1			T2	22		T252	489		T246	107
fsm_err	secret0	4064	1			T14	117		T346	99		T264	216
fsm_err	hw_cfg1	4192	1			T101	251		T247	228		T245	312
fsm_err	hw_cfg0	4566	1			T10	71		T6	2		T182	253
fsm_err	rot_creator_auth_state	2421	1			T135	31		T14	201		T248	411
fsm_err	rot_creator_auth_codesign	4028	1			T13	155		T145	72		T262	122
fsm_err	owner_sw_cfg	3752	1			T347	190		T348	205		T349	24
fsm_err	creator_sw_cfg	1712	1			T135	55		T220	191		T350	351
fsm_err	vendor_test	15451	1			T9	59		T6	177		T35	31
access_err	life_cycle	707	1			T6	37		T12	8		T13	2
access_err	secret2	11257	1			T1	2		T2	43		T4	2
access_err	secret1	5871	1			T9	24		T24	30		T6	27
access_err	secret0	4697	1			T1	2		T2	3		T9	36
access_err	hw_cfg1	1329	1			T2	4		T5	1		T9	2
access_err	hw_cfg0	2111	1			T9	5		T24	15		T6	22
access_err	rot_creator_auth_state	6215	1			T2	24		T7	1		T9	16
access_err	rot_creator_auth_codesign	8432	1			T2	13		T9	36		T24	49
access_err	owner_sw_cfg	7285	1			T2	18		T9	45		T24	43
access_err	creator_sw_cfg	7864	1			T2	18		T9	45		T24	33
access_err	vendor_test	7863	1			T2	27		T5	2		T9	23
write_blank_err	secret2	11	1			T256	1		T351	1		T352	1
write_blank_err	secret1	25	1			T6	1		T12	1		T145	1
write_blank_err	secret0	47	1			T6	2		T181	1		T94	2
write_blank_err	hw_cfg1	65	1			T5	1		T6	2		T13	1
write_blank_err	hw_cfg0	14	1			T6	1		T353	1		T143	1
write_blank_err	rot_creator_auth_state	149	1			T2	1		T6	2		T12	1
write_blank_err	rot_creator_auth_codesign	41	1			T94	1		T354	2		T212	1
write_blank_err	owner_sw_cfg	9	1			T353	1		T351	1		T355	1
write_blank_err	creator_sw_cfg	17	1			T2	1		T286	1		T356	1
write_blank_err	vendor_test	31	1			T2	3		T13	1		T357	2
ecc_uncorr_err	secret2	4868	1			T4	66		T142	112		T256	554
ecc_uncorr_err	secret1	10372	1			T4	71		T7	56		T6	649
ecc_uncorr_err	secret0	17452	1			T6	851		T181	326		T135	37
ecc_uncorr_err	hw_cfg1	20892	1			T5	48		T7	51		T6	285
ecc_uncorr_err	hw_cfg0	6543	1			T7	20		T135	34		T353	553
ecc_uncorr_err	rot_creator_auth_state	3936	1			T4	66		T13	169		T204	507
ecc_uncorr_err	rot_creator_auth_codesign	1349	1			T4	60		T358	45		T142	95
ecc_uncorr_err	owner_sw_cfg	1773	1			T7	31		T135	37		T358	41
ecc_uncorr_err	creator_sw_cfg	1557	1			T2	290		T7	32		T135	32
ecc_corr_err	secret2	101	1			T9	2		T35	1		T102	1
ecc_corr_err	secret1	106	1			T124	2		T127	2		T135	1
ecc_corr_err	secret0	115	1			T9	5		T35	4		T94	2
ecc_corr_err	hw_cfg1	277	1			T9	8		T6	2		T35	2
ecc_corr_err	hw_cfg0	263	1			T4	2		T9	11		T6	1
ecc_corr_err	rot_creator_auth_state	169	1			T9	4		T12	1		T135	1
ecc_corr_err	rot_creator_auth_codesign	159	1			T7	2		T9	2		T35	1
ecc_corr_err	owner_sw_cfg	125	1			T9	6		T135	2		T70	2
ecc_corr_err	creator_sw_cfg	145	1			T9	2		T35	4		T135	1
no_err	secret2	5297	1			T2	13		T4	1		T5	26
no_err	secret1	9806	1			T1	3		T2	46		T5	16
no_err	secret0	9109	1			T1	3		T2	38		T5	9
no_err	hw_cfg1	11013	1			T1	3		T2	19		T5	10
no_err	hw_cfg0	12431	1			T1	6		T2	29		T4	2
no_err	rot_creator_auth_state	8559	1			T1	4		T2	20		T4	3
no_err	rot_creator_auth_codesign	9461	1			T1	5		T2	30		T4	1
no_err	owner_sw_cfg	9443	1			T1	9		T2	40		T5	14
no_err	creator_sw_cfg	8437	1			T1	1		T2	34		T5	19
no_err	vendor_test	9903	1			T1	1		T2	23		T5	31

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded