Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

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Summary for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
otbn_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
otbn_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
otbn_req_during_lc_esc	2	0	2	100.00	100	1	1	0
otbn_req_during_otp_idle	2	0	2	100.00	100	1	1	2
otbn_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
otbn_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable otbn_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12521

1

T2

103

T3

6

T4

2

auto[1]

695

1

T2

3

T14

3

T95

10

---

Summary for Variable otbn_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12339

1

T2

99

T3

6

T4

2

auto[1]

877

1

T2

7

T14

7

T95

16

---

Summary for Variable otbn_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for otbn_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

13178

1

T2

105

T3

6

T4

2

lc_esc_on

38

1

T2

1

T5

1

T182

1

---

Summary for Variable otbn_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2364

1

T2

1

T4

1

T24

15

auto[1]

10852

1

T2

105

T3

6

T4

1

---

Summary for Variable otbn_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12357

1

T2

101

T3

6

T4

2

auto[1]

859

1

T2

5

T14

11

T95

7

---

Summary for Variable otbn_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12920

1

T2

100

T3

6

T4

2

auto[1]

296

1

T2

6

T14

1

T95

1