Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	51437	1			T2	259		T3	174		T65	69
access_err	68507	1			T2	117		T3	9		T4	2
write_blank_err	517	1			T2	2		T107	3		T5	9
ecc_uncorr_err	74788	1			T2	477		T9	34		T10	68
ecc_corr_err	1315	1			T3	20		T9	3		T107	1
no_err	95726	1			T2	334		T3	53		T4	10

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	739	1			T2	6		T5	16		T6	5
secret2	25782	1			T2	76		T3	10		T8	46
secret1	31118	1			T2	45		T3	6		T4	2
secret0	37843	1			T2	323		T3	13		T4	1
hw_cfg1	41969	1			T2	228		T3	5		T8	41
hw_cfg0	31776	1			T2	50		T3	10		T4	3
rot_creator_auth_state	25660	1			T2	276		T3	10		T8	36
rot_creator_auth_codesign	24933	1			T2	42		T3	3		T4	6
owner_sw_cfg	21721	1			T2	44		T3	12		T8	56
creator_sw_cfg	21599	1			T2	57		T3	6		T8	45
vendor_test	29150	1			T2	42		T3	181		T8	51

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3710	1			T2	26		T122	79		T305	535
fsm_err	secret1	3656	1			T133	267		T306	22		T141	35
fsm_err	secret0	5336	1			T70	498		T147	61		T307	165
fsm_err	hw_cfg1	4960	1			T140	128		T308	448		T142	182
fsm_err	hw_cfg0	7384	1			T106	366		T5	224		T182	73
fsm_err	rot_creator_auth_state	5397	1			T2	233		T156	25		T209	443
fsm_err	rot_creator_auth_codesign	4713	1			T108	284		T146	42		T309	74
fsm_err	owner_sw_cfg	2696	1			T150	43		T156	15		T300	153
fsm_err	creator_sw_cfg	3304	1			T146	53		T101	351		T216	70
fsm_err	vendor_test	10281	1			T3	174		T65	69		T69	51
access_err	life_cycle	739	1			T2	6		T5	16		T6	5
access_err	secret2	11661	1			T2	33		T3	1		T8	34
access_err	secret1	6384	1			T8	42		T34	4		T95	33
access_err	secret0	5446	1			T2	3		T8	43		T34	5
access_err	hw_cfg1	1391	1			T2	2		T8	4		T34	3
access_err	hw_cfg0	2510	1			T3	2		T8	16		T95	12
access_err	rot_creator_auth_state	6548	1			T2	17		T3	3		T8	20
access_err	rot_creator_auth_codesign	8905	1			T2	6		T4	2		T8	28
access_err	owner_sw_cfg	7882	1			T2	10		T8	47		T24	1
access_err	creator_sw_cfg	8603	1			T2	22		T3	3		T8	28
access_err	vendor_test	8438	1			T2	18		T8	24		T106	6
write_blank_err	secret2	11	1			T107	1		T179	1		T241	1
write_blank_err	secret1	31	1			T5	1		T240	2		T179	3
write_blank_err	secret0	45	1			T2	1		T5	2		T6	1
write_blank_err	hw_cfg1	76	1			T2	1		T107	1		T97	1
write_blank_err	hw_cfg0	21	1			T6	1		T101	1		T70	1
write_blank_err	rot_creator_auth_state	165	1			T5	3		T6	2		T97	11
write_blank_err	rot_creator_auth_codesign	74	1			T5	2		T131	1		T179	1
write_blank_err	owner_sw_cfg	54	1			T107	1		T6	8		T97	2
write_blank_err	creator_sw_cfg	12	1			T97	1		T128	2		T310	1
write_blank_err	vendor_test	28	1			T5	1		T293	2		T240	1
ecc_uncorr_err	secret2	4719	1			T107	221		T151	51		T156	14
ecc_uncorr_err	secret1	11547	1			T5	632		T152	39		T240	411
ecc_uncorr_err	secret0	17828	1			T2	276		T5	1019		T6	294
ecc_uncorr_err	hw_cfg1	24034	1			T2	201		T150	35		T151	102
ecc_uncorr_err	hw_cfg0	8625	1			T6	338		T150	73		T152	44
ecc_uncorr_err	rot_creator_auth_state	4703	1			T150	45		T146	22		T97	601
ecc_uncorr_err	rot_creator_auth_codesign	1669	1			T10	68		T150	90		T156	15
ecc_uncorr_err	owner_sw_cfg	927	1			T9	34		T146	60		T151	45
ecc_uncorr_err	creator_sw_cfg	736	1			T146	60		T152	123		T156	18
ecc_corr_err	secret2	77	1			T3	4		T63	2		T42	1
ecc_corr_err	secret1	124	1			T146	3		T151	1		T63	1
ecc_corr_err	secret0	183	1			T3	9		T146	1		T69	1
ecc_corr_err	hw_cfg1	258	1			T9	2		T107	1		T150	2
ecc_corr_err	hw_cfg0	222	1			T3	2		T146	6		T69	3
ecc_corr_err	rot_creator_auth_state	90	1			T3	1		T146	1		T97	1
ecc_corr_err	rot_creator_auth_codesign	138	1			T3	1		T146	2		T151	4
ecc_corr_err	owner_sw_cfg	98	1			T3	1		T150	1		T55	1
ecc_corr_err	creator_sw_cfg	125	1			T3	2		T9	1		T150	1
no_err	secret2	5604	1			T2	17		T3	5		T8	12
no_err	secret1	9376	1			T2	45		T3	6		T4	2
no_err	secret0	9005	1			T2	43		T3	4		T4	1
no_err	hw_cfg1	11250	1			T2	24		T3	5		T8	37
no_err	hw_cfg0	13014	1			T2	50		T3	6		T4	3
no_err	rot_creator_auth_state	8757	1			T2	26		T3	6		T8	16
no_err	rot_creator_auth_codesign	9434	1			T2	36		T3	2		T4	4
no_err	owner_sw_cfg	10064	1			T2	34		T3	11		T8	9
no_err	creator_sw_cfg	8819	1			T2	35		T3	1		T8	17
no_err	vendor_test	10403	1			T2	24		T3	7		T8	27

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded