Summary for Variable keymgr_rd_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for keymgr_rd_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3956 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
5 |
auto[1] |
2600 |
1 |
|
|
T2 |
5 |
|
T3 |
2 |
|
T4 |
1 |
Summary for Variable secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret2_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4523 |
1 |
|
|
T1 |
1 |
|
T2 |
13 |
|
T3 |
4 |
auto[1] |
2033 |
1 |
|
|
T3 |
3 |
|
T8 |
5 |
|
T11 |
1 |
Summary for Cross keymgr_output_conditions
Samples crossed: keymgr_rd_en secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for keymgr_output_conditions
Bins
keymgr_rd_en | secret2_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
2718 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
2 |
auto[0] |
auto[1] |
1238 |
1 |
|
|
T3 |
3 |
|
T8 |
4 |
|
T11 |
1 |
auto[1] |
auto[0] |
1805 |
1 |
|
|
T2 |
5 |
|
T3 |
2 |
|
T4 |
1 |
auto[1] |
auto[1] |
795 |
1 |
|
|
T8 |
1 |
|
T12 |
1 |
|
T24 |
5 |