Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.79 93.76 96.25 95.87 90.93 97.05 96.34 93.35


Total test records in report: 1326
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1259 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2718454369 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:28 PM PDT 24 572684218 ps
T1260 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2911138093 Aug 04 05:31:16 PM PDT 24 Aug 04 05:31:18 PM PDT 24 109500579 ps
T1261 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.895537644 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:28 PM PDT 24 142142056 ps
T1262 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1852281485 Aug 04 05:31:23 PM PDT 24 Aug 04 05:31:25 PM PDT 24 562685278 ps
T1263 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2905685554 Aug 04 05:31:21 PM PDT 24 Aug 04 05:31:22 PM PDT 24 136758304 ps
T1264 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.624016284 Aug 04 05:31:11 PM PDT 24 Aug 04 05:31:21 PM PDT 24 431891674 ps
T269 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.4047250170 Aug 04 05:31:14 PM PDT 24 Aug 04 05:31:17 PM PDT 24 281723897 ps
T1265 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3681854003 Aug 04 05:31:28 PM PDT 24 Aug 04 05:31:29 PM PDT 24 85397529 ps
T1266 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1939514910 Aug 04 05:31:24 PM PDT 24 Aug 04 05:31:25 PM PDT 24 43890369 ps
T1267 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3346107175 Aug 04 05:31:19 PM PDT 24 Aug 04 05:31:21 PM PDT 24 153850850 ps
T281 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3867026758 Aug 04 05:31:19 PM PDT 24 Aug 04 05:31:20 PM PDT 24 40199850 ps
T1268 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3144243175 Aug 04 05:31:16 PM PDT 24 Aug 04 05:31:36 PM PDT 24 2333964560 ps
T1269 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2209189363 Aug 04 05:31:28 PM PDT 24 Aug 04 05:31:30 PM PDT 24 75872243 ps
T1270 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.558311815 Aug 04 05:31:25 PM PDT 24 Aug 04 05:31:28 PM PDT 24 110080119 ps
T1271 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.919364086 Aug 04 05:31:20 PM PDT 24 Aug 04 05:31:25 PM PDT 24 234079653 ps
T1272 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3395358449 Aug 04 05:31:18 PM PDT 24 Aug 04 05:31:20 PM PDT 24 67636663 ps
T1273 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2988155784 Aug 04 05:31:22 PM PDT 24 Aug 04 05:31:33 PM PDT 24 71381317 ps
T1274 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.552690818 Aug 04 05:31:16 PM PDT 24 Aug 04 05:31:18 PM PDT 24 38027241 ps
T1275 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1084599232 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:29 PM PDT 24 72132965 ps
T237 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3346890085 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:45 PM PDT 24 1295045103 ps
T1276 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1954502424 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:37 PM PDT 24 1242570164 ps
T1277 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.154624473 Aug 04 05:31:16 PM PDT 24 Aug 04 05:31:17 PM PDT 24 37628893 ps
T1278 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1750252100 Aug 04 05:31:24 PM PDT 24 Aug 04 05:31:29 PM PDT 24 1027442433 ps
T1279 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3412255988 Aug 04 05:31:25 PM PDT 24 Aug 04 05:31:27 PM PDT 24 79107805 ps
T1280 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3934378265 Aug 04 05:31:23 PM PDT 24 Aug 04 05:31:26 PM PDT 24 193277432 ps
T1281 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3343840809 Aug 04 05:31:17 PM PDT 24 Aug 04 05:31:18 PM PDT 24 124277846 ps
T1282 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2605826202 Aug 04 05:31:24 PM PDT 24 Aug 04 05:31:26 PM PDT 24 83228935 ps
T1283 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.2782568951 Aug 04 05:31:42 PM PDT 24 Aug 04 05:31:46 PM PDT 24 495794706 ps
T270 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3432922466 Aug 04 05:31:23 PM PDT 24 Aug 04 05:31:25 PM PDT 24 133877476 ps
T1284 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1005362682 Aug 04 05:31:16 PM PDT 24 Aug 04 05:31:18 PM PDT 24 98759921 ps
T1285 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.334507152 Aug 04 05:31:25 PM PDT 24 Aug 04 05:31:27 PM PDT 24 72664550 ps
T1286 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2594811459 Aug 04 05:31:20 PM PDT 24 Aug 04 05:31:22 PM PDT 24 40350122 ps
T319 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.289144189 Aug 04 05:31:16 PM PDT 24 Aug 04 05:31:28 PM PDT 24 1574010855 ps
T1287 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.927810766 Aug 04 05:31:16 PM PDT 24 Aug 04 05:31:20 PM PDT 24 1240345636 ps
T1288 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.4020103935 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:28 PM PDT 24 582451109 ps
T1289 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.4069841124 Aug 04 05:31:22 PM PDT 24 Aug 04 05:31:25 PM PDT 24 147707416 ps
T1290 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.841193855 Aug 04 05:31:18 PM PDT 24 Aug 04 05:31:20 PM PDT 24 171137916 ps
T1291 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1745319278 Aug 04 05:31:22 PM PDT 24 Aug 04 05:31:25 PM PDT 24 384879031 ps
T1292 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2120935247 Aug 04 05:31:18 PM PDT 24 Aug 04 05:31:20 PM PDT 24 635538024 ps
T1293 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.235428908 Aug 04 05:31:13 PM PDT 24 Aug 04 05:31:15 PM PDT 24 532322345 ps
T318 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2340521566 Aug 04 05:31:27 PM PDT 24 Aug 04 05:31:48 PM PDT 24 5519984944 ps
T1294 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2883779553 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:28 PM PDT 24 136827410 ps
T1295 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.424428480 Aug 04 05:31:16 PM PDT 24 Aug 04 05:31:20 PM PDT 24 886702707 ps
T317 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.998521454 Aug 04 05:31:22 PM PDT 24 Aug 04 05:31:43 PM PDT 24 1271975049 ps
T1296 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3797196135 Aug 04 05:31:25 PM PDT 24 Aug 04 05:31:29 PM PDT 24 98506294 ps
T1297 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.4203818944 Aug 04 05:31:19 PM PDT 24 Aug 04 05:31:21 PM PDT 24 86844691 ps
T1298 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2298833845 Aug 04 05:31:23 PM PDT 24 Aug 04 05:31:25 PM PDT 24 147067997 ps
T1299 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.3673506131 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:27 PM PDT 24 136298843 ps
T1300 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.4024317089 Aug 04 05:31:23 PM PDT 24 Aug 04 05:31:41 PM PDT 24 1346258098 ps
T1301 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.244825222 Aug 04 05:31:22 PM PDT 24 Aug 04 05:31:28 PM PDT 24 285669628 ps
T1302 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.2861942697 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:27 PM PDT 24 82462170 ps
T1303 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.636243635 Aug 04 05:31:22 PM PDT 24 Aug 04 05:31:28 PM PDT 24 1496898719 ps
T1304 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.4157482062 Aug 04 05:31:27 PM PDT 24 Aug 04 05:31:35 PM PDT 24 94699266 ps
T1305 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3450136218 Aug 04 05:31:22 PM PDT 24 Aug 04 05:31:25 PM PDT 24 424787152 ps
T1306 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.297972431 Aug 04 05:31:17 PM PDT 24 Aug 04 05:31:19 PM PDT 24 51675063 ps
T235 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.4130879690 Aug 04 05:31:21 PM PDT 24 Aug 04 05:31:31 PM PDT 24 2393269448 ps
T1307 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.1938410337 Aug 04 05:31:18 PM PDT 24 Aug 04 05:31:19 PM PDT 24 129341842 ps
T1308 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3663822005 Aug 04 05:31:19 PM PDT 24 Aug 04 05:31:21 PM PDT 24 154553452 ps
T1309 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.846662161 Aug 04 05:31:20 PM PDT 24 Aug 04 05:31:22 PM PDT 24 68734925 ps
T1310 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.560304593 Aug 04 05:31:18 PM PDT 24 Aug 04 05:31:23 PM PDT 24 1771349662 ps
T1311 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.191531310 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:27 PM PDT 24 105621588 ps
T1312 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.589977798 Aug 04 05:31:22 PM PDT 24 Aug 04 05:31:27 PM PDT 24 85069434 ps
T1313 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3796937032 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:28 PM PDT 24 44160615 ps
T1314 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.4263864635 Aug 04 05:31:23 PM PDT 24 Aug 04 05:31:38 PM PDT 24 2590069509 ps
T1315 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2402646264 Aug 04 05:31:23 PM PDT 24 Aug 04 05:31:25 PM PDT 24 531753033 ps
T1316 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3541524849 Aug 04 05:31:15 PM PDT 24 Aug 04 05:31:17 PM PDT 24 39892003 ps
T1317 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1313802599 Aug 04 05:31:21 PM PDT 24 Aug 04 05:31:22 PM PDT 24 71751984 ps
T1318 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1103999634 Aug 04 05:31:14 PM PDT 24 Aug 04 05:31:17 PM PDT 24 216980400 ps
T1319 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1228154031 Aug 04 05:31:21 PM PDT 24 Aug 04 05:31:23 PM PDT 24 42428415 ps
T1320 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3136598920 Aug 04 05:31:18 PM PDT 24 Aug 04 05:31:21 PM PDT 24 223459764 ps
T1321 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.143628135 Aug 04 05:31:48 PM PDT 24 Aug 04 05:31:51 PM PDT 24 75740714 ps
T1322 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1691424106 Aug 04 05:31:25 PM PDT 24 Aug 04 05:31:28 PM PDT 24 205073624 ps
T1323 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.1441799410 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:27 PM PDT 24 118974542 ps
T1324 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1293052100 Aug 04 05:31:18 PM PDT 24 Aug 04 05:31:20 PM PDT 24 140045098 ps
T1325 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1878321949 Aug 04 05:31:24 PM PDT 24 Aug 04 05:31:30 PM PDT 24 554812149 ps
T1326 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.4231489011 Aug 04 05:31:18 PM PDT 24 Aug 04 05:31:20 PM PDT 24 146980918 ps

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.2793337840
Short name T2
Test name
Test status
Simulation time 71269785451 ps
CPU time 733.87 seconds
Started Aug 04 05:24:35 PM PDT 24
Finished Aug 04 05:36:49 PM PDT 24
Peak memory 280624 kb
Host smart-9b3ee897-d67c-4562-9e8b-1c0558e67571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793337840 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.2793337840
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.578763191
Short name T97
Test name
Test status
Simulation time 23057284304 ps
CPU time 191.66 seconds
Started Aug 04 05:25:21 PM PDT 24
Finished Aug 04 05:28:32 PM PDT 24
Peak memory 289612 kb
Host smart-d4fa5046-82f3-4334-a922-1a1113b642d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578763191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.
578763191
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.2415147491
Short name T3
Test name
Test status
Simulation time 458036533 ps
CPU time 15.96 seconds
Started Aug 04 05:25:55 PM PDT 24
Finished Aug 04 05:26:11 PM PDT 24
Peak memory 248620 kb
Host smart-da544dfc-1dae-4072-817c-6db6f5cc844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415147491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2415147491
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.535978813
Short name T101
Test name
Test status
Simulation time 14210089013 ps
CPU time 170.28 seconds
Started Aug 04 05:25:41 PM PDT 24
Finished Aug 04 05:28:32 PM PDT 24
Peak memory 265068 kb
Host smart-e5fdafb6-7e02-4315-863e-57a0dc5a80eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535978813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.
535978813
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.3918494531
Short name T185
Test name
Test status
Simulation time 49332907556 ps
CPU time 173.46 seconds
Started Aug 04 05:25:33 PM PDT 24
Finished Aug 04 05:28:26 PM PDT 24
Peak memory 257332 kb
Host smart-df21a8c5-d618-4483-9ee6-cc088fc4ae0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918494531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.3918494531
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.4224508526
Short name T18
Test name
Test status
Simulation time 41360217913 ps
CPU time 208.34 seconds
Started Aug 04 05:24:24 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 266160 kb
Host smart-a779a68a-9b29-497e-9422-ab99b7f2dc0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224508526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.4224508526
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.3740273915
Short name T70
Test name
Test status
Simulation time 47193422495 ps
CPU time 226.65 seconds
Started Aug 04 05:25:17 PM PDT 24
Finished Aug 04 05:29:04 PM PDT 24
Peak memory 265020 kb
Host smart-bd13f0a5-3144-4a9c-b261-080406de79ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740273915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.3740273915
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.2702360732
Short name T122
Test name
Test status
Simulation time 447096009684 ps
CPU time 3128.77 seconds
Started Aug 04 05:26:44 PM PDT 24
Finished Aug 04 06:18:54 PM PDT 24
Peak memory 693228 kb
Host smart-f70dbde6-0941-4e1e-8e1e-8ead4622cc1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702360732 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.2702360732
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.3352133015
Short name T40
Test name
Test status
Simulation time 366829107 ps
CPU time 3.63 seconds
Started Aug 04 05:27:26 PM PDT 24
Finished Aug 04 05:27:30 PM PDT 24
Peak memory 242208 kb
Host smart-a61be434-0152-4fcd-8170-a95be1811ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352133015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3352133015
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2944142657
Short name T230
Test name
Test status
Simulation time 1756943880 ps
CPU time 21.42 seconds
Started Aug 04 05:31:13 PM PDT 24
Finished Aug 04 05:31:35 PM PDT 24
Peak memory 239008 kb
Host smart-a25ec8c7-e873-4ae1-af22-b1788698dd78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944142657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.2944142657
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.3435886533
Short name T154
Test name
Test status
Simulation time 487931823 ps
CPU time 3.75 seconds
Started Aug 04 05:27:12 PM PDT 24
Finished Aug 04 05:27:15 PM PDT 24
Peak memory 242384 kb
Host smart-7478c919-bc8b-4719-9175-1d49dcf4552c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435886533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.3435886533
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.3107000899
Short name T7
Test name
Test status
Simulation time 1952573679 ps
CPU time 7.32 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:36 PM PDT 24
Peak memory 242056 kb
Host smart-a745225c-f330-4693-99eb-f87c2d41b439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107000899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3107000899
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.1823963601
Short name T156
Test name
Test status
Simulation time 2855882508 ps
CPU time 26.93 seconds
Started Aug 04 05:24:46 PM PDT 24
Finished Aug 04 05:25:13 PM PDT 24
Peak memory 244756 kb
Host smart-4f351a85-2782-4751-a711-56c66cd7403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823963601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1823963601
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.1825352117
Short name T8
Test name
Test status
Simulation time 1487774792 ps
CPU time 31.18 seconds
Started Aug 04 05:25:31 PM PDT 24
Finished Aug 04 05:26:02 PM PDT 24
Peak memory 242428 kb
Host smart-96d2bf3b-bf9f-4e88-aff2-4c3e93d4feaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825352117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.1825352117
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.2484162180
Short name T16
Test name
Test status
Simulation time 143173591898 ps
CPU time 2875.17 seconds
Started Aug 04 05:26:45 PM PDT 24
Finished Aug 04 06:14:40 PM PDT 24
Peak memory 378876 kb
Host smart-13d91cf9-6b01-43eb-9437-ac4f0769a7db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484162180 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.2484162180
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.2905945027
Short name T22
Test name
Test status
Simulation time 2140649813 ps
CPU time 5.12 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 242176 kb
Host smart-a20d6d90-42ee-4a1d-a765-e147ac23969a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905945027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2905945027
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.1554791087
Short name T153
Test name
Test status
Simulation time 1792257625 ps
CPU time 6.9 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:31 PM PDT 24
Peak memory 242332 kb
Host smart-14610a0f-656d-4ce3-bd3b-dfcf99980414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554791087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1554791087
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.732135426
Short name T137
Test name
Test status
Simulation time 38467236034 ps
CPU time 189.46 seconds
Started Aug 04 05:25:00 PM PDT 24
Finished Aug 04 05:28:10 PM PDT 24
Peak memory 273236 kb
Host smart-636d14af-29c2-49ca-9b3b-9d25457258b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732135426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.
732135426
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.1021109679
Short name T111
Test name
Test status
Simulation time 3915080985 ps
CPU time 13.4 seconds
Started Aug 04 05:26:18 PM PDT 24
Finished Aug 04 05:26:32 PM PDT 24
Peak memory 243272 kb
Host smart-9f820220-f2ed-4957-9a7d-4dea70dadd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021109679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.1021109679
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.3663776002
Short name T61
Test name
Test status
Simulation time 2539514946 ps
CPU time 7.54 seconds
Started Aug 04 05:24:43 PM PDT 24
Finished Aug 04 05:24:51 PM PDT 24
Peak memory 242028 kb
Host smart-5194d3ce-2468-4d05-8e84-13b443851877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663776002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.3663776002
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.3397132905
Short name T51
Test name
Test status
Simulation time 184491240 ps
CPU time 5.17 seconds
Started Aug 04 05:26:56 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 242256 kb
Host smart-19386cba-a5fa-406e-9e0e-62646f6897e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397132905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3397132905
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.1551140856
Short name T493
Test name
Test status
Simulation time 492087301 ps
CPU time 4.2 seconds
Started Aug 04 05:27:30 PM PDT 24
Finished Aug 04 05:27:35 PM PDT 24
Peak memory 242156 kb
Host smart-7cc1b9a2-95a2-4979-887b-9ef9e5f7499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551140856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.1551140856
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.1526837613
Short name T45
Test name
Test status
Simulation time 2342361090 ps
CPU time 5.3 seconds
Started Aug 04 05:27:26 PM PDT 24
Finished Aug 04 05:27:32 PM PDT 24
Peak memory 242412 kb
Host smart-c20d38dc-f385-42a4-a4f5-f6f3294fe674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526837613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1526837613
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.823237253
Short name T30
Test name
Test status
Simulation time 675064399 ps
CPU time 5.55 seconds
Started Aug 04 05:27:13 PM PDT 24
Finished Aug 04 05:27:18 PM PDT 24
Peak memory 242400 kb
Host smart-6af40bd8-8ecf-40c3-becf-a272faa7f342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823237253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.823237253
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.3097303355
Short name T179
Test name
Test status
Simulation time 182137577888 ps
CPU time 295.24 seconds
Started Aug 04 05:25:05 PM PDT 24
Finished Aug 04 05:30:01 PM PDT 24
Peak memory 330460 kb
Host smart-d034e623-e9c0-4ae6-8cf1-a2a595efcf01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097303355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.3097303355
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.2529830906
Short name T44
Test name
Test status
Simulation time 3095579565 ps
CPU time 33.82 seconds
Started Aug 04 05:25:25 PM PDT 24
Finished Aug 04 05:25:59 PM PDT 24
Peak memory 245556 kb
Host smart-43a89f73-dd7b-45be-b679-cbed6cdfbfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529830906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.2529830906
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.960606130
Short name T363
Test name
Test status
Simulation time 110347006666 ps
CPU time 295.22 seconds
Started Aug 04 05:25:29 PM PDT 24
Finished Aug 04 05:30:24 PM PDT 24
Peak memory 281476 kb
Host smart-10e387e0-965a-4fe9-b658-48eb10c9c151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960606130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.
960606130
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.1409033933
Short name T168
Test name
Test status
Simulation time 237033641 ps
CPU time 4.29 seconds
Started Aug 04 05:27:25 PM PDT 24
Finished Aug 04 05:27:30 PM PDT 24
Peak memory 242176 kb
Host smart-0f096c4a-748a-44c1-80f8-955be9d801c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409033933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.1409033933
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2314804488
Short name T245
Test name
Test status
Simulation time 78677344484 ps
CPU time 1751.39 seconds
Started Aug 04 05:26:41 PM PDT 24
Finished Aug 04 05:55:53 PM PDT 24
Peak memory 465292 kb
Host smart-6d543353-4c3e-473d-a611-458d2f57781f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314804488 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.2314804488
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.189756990
Short name T37
Test name
Test status
Simulation time 300160643 ps
CPU time 4.58 seconds
Started Aug 04 05:27:25 PM PDT 24
Finished Aug 04 05:27:30 PM PDT 24
Peak memory 242168 kb
Host smart-12ba3c0b-8e86-4983-87b4-56953c604f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189756990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.189756990
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.1642554489
Short name T321
Test name
Test status
Simulation time 4534424707 ps
CPU time 16.33 seconds
Started Aug 04 05:24:36 PM PDT 24
Finished Aug 04 05:24:52 PM PDT 24
Peak memory 242640 kb
Host smart-8c608e72-d96d-4ecb-a3a5-bc63eb8041eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642554489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.1642554489
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.31467612
Short name T188
Test name
Test status
Simulation time 1075956184 ps
CPU time 26.16 seconds
Started Aug 04 05:25:48 PM PDT 24
Finished Aug 04 05:26:14 PM PDT 24
Peak memory 242964 kb
Host smart-196344f1-d3c1-4b4c-b81d-ddd35680419a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31467612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.31467612
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.2667127809
Short name T140
Test name
Test status
Simulation time 8539424776 ps
CPU time 87.46 seconds
Started Aug 04 05:24:46 PM PDT 24
Finished Aug 04 05:26:14 PM PDT 24
Peak memory 245716 kb
Host smart-64738e94-a91b-4cd9-99cf-32873a28c30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667127809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
2667127809
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.1600989082
Short name T195
Test name
Test status
Simulation time 129944541 ps
CPU time 3.59 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:03 PM PDT 24
Peak memory 242156 kb
Host smart-2ee4edc2-ae50-4c48-95e4-e13b3296afb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600989082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1600989082
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.3742368111
Short name T133
Test name
Test status
Simulation time 1750214370 ps
CPU time 12.96 seconds
Started Aug 04 05:26:44 PM PDT 24
Finished Aug 04 05:26:57 PM PDT 24
Peak memory 242356 kb
Host smart-9bef5a65-708e-4918-924b-58588dc03f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742368111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.3742368111
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.3803874383
Short name T220
Test name
Test status
Simulation time 671451628 ps
CPU time 2.11 seconds
Started Aug 04 05:24:53 PM PDT 24
Finished Aug 04 05:24:56 PM PDT 24
Peak memory 240708 kb
Host smart-9c8d6854-8ec4-4746-af94-401962fd3c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803874383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3803874383
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.2780766814
Short name T219
Test name
Test status
Simulation time 10874239032 ps
CPU time 193.61 seconds
Started Aug 04 05:24:33 PM PDT 24
Finished Aug 04 05:27:46 PM PDT 24
Peak memory 264192 kb
Host smart-7c88a327-177c-40cf-877c-88550b0a0783
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780766814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2780766814
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.3152705295
Short name T41
Test name
Test status
Simulation time 288405601 ps
CPU time 3.91 seconds
Started Aug 04 05:26:56 PM PDT 24
Finished Aug 04 05:27:00 PM PDT 24
Peak memory 241912 kb
Host smart-a3dbf690-3cc6-48b2-bc64-d7f0fdd7bb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152705295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3152705295
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.1592918147
Short name T142
Test name
Test status
Simulation time 253785390831 ps
CPU time 1026.87 seconds
Started Aug 04 05:25:38 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 361780 kb
Host smart-862e0864-1274-4cb7-a42c-24627132ac21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592918147 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.1592918147
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.3635006430
Short name T82
Test name
Test status
Simulation time 1319088954 ps
CPU time 24.94 seconds
Started Aug 04 05:26:22 PM PDT 24
Finished Aug 04 05:26:47 PM PDT 24
Peak memory 248576 kb
Host smart-9f7c8cf1-c19e-4cf5-8673-e168ee8887b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635006430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3635006430
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3928067712
Short name T238
Test name
Test status
Simulation time 2467957083 ps
CPU time 21.25 seconds
Started Aug 04 05:31:19 PM PDT 24
Finished Aug 04 05:31:40 PM PDT 24
Peak memory 245356 kb
Host smart-643c28c5-acd2-44be-ac9c-55078abf1468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928067712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.3928067712
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.1984701229
Short name T48
Test name
Test status
Simulation time 172241756 ps
CPU time 4.41 seconds
Started Aug 04 05:24:58 PM PDT 24
Finished Aug 04 05:25:02 PM PDT 24
Peak memory 242124 kb
Host smart-88837b0a-60fb-4084-ac7c-977d06e7e6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984701229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.1984701229
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.3574892626
Short name T23
Test name
Test status
Simulation time 215090192 ps
CPU time 4.44 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:26:59 PM PDT 24
Peak memory 241888 kb
Host smart-7699c769-dc90-4bc9-a805-7208edbc452d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574892626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3574892626
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.4281404598
Short name T247
Test name
Test status
Simulation time 196154850690 ps
CPU time 1944.11 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:59:22 PM PDT 24
Peak memory 360760 kb
Host smart-1374b40f-f814-406c-90eb-e8ec786fdb19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281404598 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.4281404598
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.3094522552
Short name T25
Test name
Test status
Simulation time 13248799421 ps
CPU time 43.14 seconds
Started Aug 04 05:26:15 PM PDT 24
Finished Aug 04 05:26:58 PM PDT 24
Peak memory 243344 kb
Host smart-9b245cf1-3630-4f7c-8b66-0fae01ea8425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094522552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.3094522552
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3346890085
Short name T237
Test name
Test status
Simulation time 1295045103 ps
CPU time 18.84 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:45 PM PDT 24
Peak memory 238828 kb
Host smart-519066cf-a3b8-469d-a1dd-4eaf9e8f7b47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346890085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.3346890085
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.2767809630
Short name T1029
Test name
Test status
Simulation time 317623552 ps
CPU time 4.32 seconds
Started Aug 04 05:26:52 PM PDT 24
Finished Aug 04 05:26:56 PM PDT 24
Peak memory 241936 kb
Host smart-5b719d27-999f-4382-9242-5fc854948af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767809630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2767809630
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2745112810
Short name T132
Test name
Test status
Simulation time 216690259 ps
CPU time 6.2 seconds
Started Aug 04 05:26:55 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 242276 kb
Host smart-4befd050-a5f4-42be-9084-a2a8105059ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745112810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2745112810
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.1418244627
Short name T299
Test name
Test status
Simulation time 130351841 ps
CPU time 5.37 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:04 PM PDT 24
Peak memory 241956 kb
Host smart-82c1cae3-8ae0-47ea-ac4e-1717d110ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418244627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1418244627
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.3918048773
Short name T119
Test name
Test status
Simulation time 203755360 ps
CPU time 5.23 seconds
Started Aug 04 05:27:10 PM PDT 24
Finished Aug 04 05:27:15 PM PDT 24
Peak memory 241912 kb
Host smart-4e5216ae-e54a-480b-a2e7-7163464e290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918048773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3918048773
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.4032017007
Short name T183
Test name
Test status
Simulation time 435460402 ps
CPU time 6.34 seconds
Started Aug 04 05:25:58 PM PDT 24
Finished Aug 04 05:26:05 PM PDT 24
Peak memory 241808 kb
Host smart-c5f5cc21-208b-41de-b502-55c3add37eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032017007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.4032017007
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3655083843
Short name T1145
Test name
Test status
Simulation time 855647921 ps
CPU time 8.59 seconds
Started Aug 04 05:24:25 PM PDT 24
Finished Aug 04 05:24:34 PM PDT 24
Peak memory 241872 kb
Host smart-9550970c-c048-4e22-b8f0-390e433f1a26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655083843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3655083843
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.420798102
Short name T264
Test name
Test status
Simulation time 39703609 ps
CPU time 1.58 seconds
Started Aug 04 05:31:17 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 238784 kb
Host smart-935da88a-0287-4da7-99ae-4ed46f2cb046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420798102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.420798102
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.1540266641
Short name T35
Test name
Test status
Simulation time 2536510376 ps
CPU time 19.92 seconds
Started Aug 04 05:26:25 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 242324 kb
Host smart-a9da7ab7-6f1c-4bf8-9486-ca4682ed95cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540266641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1540266641
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.2480549703
Short name T146
Test name
Test status
Simulation time 1398284938 ps
CPU time 18.07 seconds
Started Aug 04 05:26:25 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 248608 kb
Host smart-505ae22f-28b5-4874-b104-08e64e5427d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480549703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2480549703
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.1292084708
Short name T521
Test name
Test status
Simulation time 39250911135 ps
CPU time 608.92 seconds
Started Aug 04 05:24:57 PM PDT 24
Finished Aug 04 05:35:06 PM PDT 24
Peak memory 323492 kb
Host smart-8ddc8a51-2145-4ad6-81b4-761214e858c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292084708 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.1292084708
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.4208590753
Short name T359
Test name
Test status
Simulation time 459560184935 ps
CPU time 1302.63 seconds
Started Aug 04 05:26:39 PM PDT 24
Finished Aug 04 05:48:22 PM PDT 24
Peak memory 429168 kb
Host smart-cd2071e3-f804-470e-b8e6-9742fc92e65d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208590753 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.4208590753
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.4243458210
Short name T324
Test name
Test status
Simulation time 655460406 ps
CPU time 9.8 seconds
Started Aug 04 05:25:07 PM PDT 24
Finished Aug 04 05:25:17 PM PDT 24
Peak memory 242184 kb
Host smart-61c542e4-9205-4478-ac66-5b22b0892624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4243458210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.4243458210
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.645834511
Short name T96
Test name
Test status
Simulation time 1459217071 ps
CPU time 19.19 seconds
Started Aug 04 05:25:13 PM PDT 24
Finished Aug 04 05:25:32 PM PDT 24
Peak memory 248472 kb
Host smart-dc97c7a5-0c40-46d4-9c0c-9f492c43a2cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645834511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.645834511
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.781371487
Short name T68
Test name
Test status
Simulation time 54961826569 ps
CPU time 300.98 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 265108 kb
Host smart-011787cd-8524-4b2a-8816-b151eeaf3efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781371487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.781371487
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.2995887858
Short name T59
Test name
Test status
Simulation time 1548643469 ps
CPU time 32.7 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:25:51 PM PDT 24
Peak memory 248560 kb
Host smart-59f3a9d7-da55-4a68-855e-ff0822896e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995887858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2995887858
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.597573931
Short name T169
Test name
Test status
Simulation time 370472190 ps
CPU time 3.82 seconds
Started Aug 04 05:26:51 PM PDT 24
Finished Aug 04 05:26:55 PM PDT 24
Peak memory 241936 kb
Host smart-c392b9a7-8e6d-4f3d-bcc7-34cb941115fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597573931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.597573931
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.2988597922
Short name T960
Test name
Test status
Simulation time 126503430 ps
CPU time 3.34 seconds
Started Aug 04 05:26:52 PM PDT 24
Finished Aug 04 05:26:56 PM PDT 24
Peak memory 242096 kb
Host smart-5a47fd05-8c72-421b-bc0e-4ea088b3958d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988597922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.2988597922
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.4209269947
Short name T204
Test name
Test status
Simulation time 200603069 ps
CPU time 4.24 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 242040 kb
Host smart-66be2567-ad1d-42c9-ae9f-bc17a4ff3f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209269947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.4209269947
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.3983458523
Short name T664
Test name
Test status
Simulation time 5422582149 ps
CPU time 177.64 seconds
Started Aug 04 05:24:29 PM PDT 24
Finished Aug 04 05:27:26 PM PDT 24
Peak memory 259888 kb
Host smart-523121b4-ae6b-46a6-a604-a7af9df23433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983458523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
3983458523
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1819840525
Short name T314
Test name
Test status
Simulation time 4805091848 ps
CPU time 18.83 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:37 PM PDT 24
Peak memory 244580 kb
Host smart-7708c4fa-fca5-41b1-8b8e-3964808d52b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819840525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.1819840525
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.1526794820
Short name T323
Test name
Test status
Simulation time 1806092834 ps
CPU time 7.13 seconds
Started Aug 04 05:25:01 PM PDT 24
Finished Aug 04 05:25:08 PM PDT 24
Peak memory 248496 kb
Host smart-e3703b84-e033-4038-8466-7ac008631534
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526794820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1526794820
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.3996774989
Short name T367
Test name
Test status
Simulation time 25132347945 ps
CPU time 188.92 seconds
Started Aug 04 05:26:33 PM PDT 24
Finished Aug 04 05:29:42 PM PDT 24
Peak memory 273656 kb
Host smart-72f59129-1c14-4c76-877a-9ef80e56110a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996774989 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.3996774989
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.612078480
Short name T234
Test name
Test status
Simulation time 107128382 ps
CPU time 2.9 seconds
Started Aug 04 05:31:35 PM PDT 24
Finished Aug 04 05:31:38 PM PDT 24
Peak memory 241120 kb
Host smart-9f88e439-1627-4f23-866e-0a1c09e30f37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612078480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alias
ing.612078480
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.3936331100
Short name T125
Test name
Test status
Simulation time 225886112244 ps
CPU time 547.76 seconds
Started Aug 04 05:25:04 PM PDT 24
Finished Aug 04 05:34:12 PM PDT 24
Peak memory 301276 kb
Host smart-0a61d774-8acb-4c9b-9dda-008b0d503e32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936331100 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.3936331100
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.1323228727
Short name T87
Test name
Test status
Simulation time 1662603048 ps
CPU time 4.87 seconds
Started Aug 04 05:26:34 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 241992 kb
Host smart-e184c644-20cd-4771-a34b-98122b9416f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323228727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.1323228727
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.1445588894
Short name T149
Test name
Test status
Simulation time 193324516 ps
CPU time 2.15 seconds
Started Aug 04 05:24:19 PM PDT 24
Finished Aug 04 05:24:21 PM PDT 24
Peak memory 240652 kb
Host smart-ee8e0b3e-2cb1-457c-872a-1a0bdf1645cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1445588894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1445588894
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.4196815044
Short name T408
Test name
Test status
Simulation time 17428395971 ps
CPU time 43.19 seconds
Started Aug 04 05:25:07 PM PDT 24
Finished Aug 04 05:25:50 PM PDT 24
Peak memory 242992 kb
Host smart-c59d805f-aeb1-4bbb-899c-255d39bf52ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196815044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.4196815044
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.4130879690
Short name T235
Test name
Test status
Simulation time 2393269448 ps
CPU time 9.42 seconds
Started Aug 04 05:31:21 PM PDT 24
Finished Aug 04 05:31:31 PM PDT 24
Peak memory 238960 kb
Host smart-5b1fa5df-215c-4464-8968-55eaa0dc6124
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130879690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.4130879690
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.4223512996
Short name T128
Test name
Test status
Simulation time 467731394 ps
CPU time 11.28 seconds
Started Aug 04 05:26:08 PM PDT 24
Finished Aug 04 05:26:20 PM PDT 24
Peak memory 248528 kb
Host smart-e0dd36f4-5642-4166-97ca-bacb1dc4f95e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223512996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.4223512996
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.3286978352
Short name T343
Test name
Test status
Simulation time 457400520 ps
CPU time 10.81 seconds
Started Aug 04 05:26:03 PM PDT 24
Finished Aug 04 05:26:14 PM PDT 24
Peak memory 241884 kb
Host smart-22964a66-6da1-4b92-9fbd-90bc6350e959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286978352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.3286978352
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.3973254892
Short name T339
Test name
Test status
Simulation time 23421166012 ps
CPU time 46.83 seconds
Started Aug 04 05:26:14 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 248652 kb
Host smart-b472130a-bb57-4072-9b06-837b67c0c2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973254892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.3973254892
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.858172765
Short name T80
Test name
Test status
Simulation time 586216016 ps
CPU time 4.38 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 241984 kb
Host smart-d2ea726c-bb94-4efa-999c-5a2d17671fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858172765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.858172765
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.1790822463
Short name T86
Test name
Test status
Simulation time 158466412 ps
CPU time 4.65 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:38 PM PDT 24
Peak memory 242112 kb
Host smart-a9f61e1a-219a-4ec6-9804-bed90df7adb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790822463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1790822463
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.63153332
Short name T88
Test name
Test status
Simulation time 677665932 ps
CPU time 4.5 seconds
Started Aug 04 05:26:39 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 242096 kb
Host smart-412dce8e-63cc-4312-84d6-686016790629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63153332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.63153332
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2414866193
Short name T1253
Test name
Test status
Simulation time 731189251 ps
CPU time 5.03 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 238812 kb
Host smart-f12b26c7-67dd-4ff1-8c8e-c7ba7d878feb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414866193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.2414866193
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1005362682
Short name T1284
Test name
Test status
Simulation time 98759921 ps
CPU time 1.79 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:18 PM PDT 24
Peak memory 238800 kb
Host smart-2fc7405b-7451-46d3-b202-57663a0e97dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005362682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.1005362682
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2911138093
Short name T1260
Test name
Test status
Simulation time 109500579 ps
CPU time 2.64 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:18 PM PDT 24
Peak memory 246400 kb
Host smart-abd3621e-f742-4825-ab99-8891c6443d4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911138093 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.2911138093
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1771149845
Short name T286
Test name
Test status
Simulation time 721360918 ps
CPU time 2.36 seconds
Started Aug 04 05:31:10 PM PDT 24
Finished Aug 04 05:31:12 PM PDT 24
Peak memory 240784 kb
Host smart-8c6decf3-31ab-4daa-bdb2-09f5401fa6fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771149845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1771149845
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3108463860
Short name T1218
Test name
Test status
Simulation time 114050247 ps
CPU time 1.56 seconds
Started Aug 04 05:31:06 PM PDT 24
Finished Aug 04 05:31:08 PM PDT 24
Peak memory 229884 kb
Host smart-b8f38704-201b-4ea4-8ce2-9fd1a1902e50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108463860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.3108463860
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1905787166
Short name T1198
Test name
Test status
Simulation time 45971085 ps
CPU time 1.4 seconds
Started Aug 04 05:31:13 PM PDT 24
Finished Aug 04 05:31:14 PM PDT 24
Peak memory 229732 kb
Host smart-3c88e8e1-0df0-480d-b1c1-b8d39d360b0d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905787166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.1905787166
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1916708361
Short name T1217
Test name
Test status
Simulation time 529422354 ps
CPU time 1.67 seconds
Started Aug 04 05:31:11 PM PDT 24
Finished Aug 04 05:31:13 PM PDT 24
Peak memory 230672 kb
Host smart-3b27eacc-7851-4660-b3e4-8edc0f078dd6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916708361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.1916708361
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1103999634
Short name T1318
Test name
Test status
Simulation time 216980400 ps
CPU time 3.44 seconds
Started Aug 04 05:31:14 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 238820 kb
Host smart-bf611c0a-3e7e-4bc4-a94a-608ddaa8595d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103999634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.1103999634
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2541792383
Short name T1196
Test name
Test status
Simulation time 91932147 ps
CPU time 5.11 seconds
Started Aug 04 05:31:11 PM PDT 24
Finished Aug 04 05:31:16 PM PDT 24
Peak memory 238888 kb
Host smart-2f498c6f-1e15-4219-9168-edd895734599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541792383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2541792383
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2197496836
Short name T1241
Test name
Test status
Simulation time 1242637079 ps
CPU time 9.11 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 243596 kb
Host smart-95207646-e364-4816-963e-a18502500b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197496836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.2197496836
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4212509138
Short name T1258
Test name
Test status
Simulation time 224252138 ps
CPU time 3.92 seconds
Started Aug 04 05:31:15 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 238884 kb
Host smart-101d57df-213c-4247-a9d1-a58a2a991630
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212509138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.4212509138
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.624016284
Short name T1264
Test name
Test status
Simulation time 431891674 ps
CPU time 9.33 seconds
Started Aug 04 05:31:11 PM PDT 24
Finished Aug 04 05:31:21 PM PDT 24
Peak memory 238836 kb
Host smart-44748c78-fadf-428c-afcf-9c6501c79399
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624016284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_b
ash.624016284
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.846662161
Short name T1309
Test name
Test status
Simulation time 68734925 ps
CPU time 1.77 seconds
Started Aug 04 05:31:20 PM PDT 24
Finished Aug 04 05:31:22 PM PDT 24
Peak memory 240400 kb
Host smart-bf51ec2c-e8cd-456a-a247-a91a401d3685
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846662161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_re
set.846662161
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.826816432
Short name T236
Test name
Test status
Simulation time 187602573 ps
CPU time 2.87 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 247120 kb
Host smart-aed44c31-5627-41f3-a5d4-f60c1ae8a9d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826816432 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.826816432
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1884887756
Short name T283
Test name
Test status
Simulation time 71504360 ps
CPU time 1.73 seconds
Started Aug 04 05:31:15 PM PDT 24
Finished Aug 04 05:31:16 PM PDT 24
Peak memory 240716 kb
Host smart-60fc67bd-b4d3-4c9c-8c2d-9bdf82c7b1fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884887756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1884887756
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1161332700
Short name T1192
Test name
Test status
Simulation time 41677615 ps
CPU time 1.38 seconds
Started Aug 04 05:31:11 PM PDT 24
Finished Aug 04 05:31:12 PM PDT 24
Peak memory 229924 kb
Host smart-aeb97e88-464a-4aa9-b8da-073cb79f429a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161332700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.1161332700
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.235428908
Short name T1293
Test name
Test status
Simulation time 532322345 ps
CPU time 1.43 seconds
Started Aug 04 05:31:13 PM PDT 24
Finished Aug 04 05:31:15 PM PDT 24
Peak memory 230308 kb
Host smart-5e371b80-dae4-4d03-8f31-2569575e6815
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235428908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl
_mem_partial_access.235428908
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2905685554
Short name T1263
Test name
Test status
Simulation time 136758304 ps
CPU time 1.31 seconds
Started Aug 04 05:31:21 PM PDT 24
Finished Aug 04 05:31:22 PM PDT 24
Peak memory 230064 kb
Host smart-df676bcc-c524-4950-9bb3-a5a8354ef290
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905685554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.2905685554
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1772054712
Short name T287
Test name
Test status
Simulation time 57321499 ps
CPU time 2.02 seconds
Started Aug 04 05:31:13 PM PDT 24
Finished Aug 04 05:31:15 PM PDT 24
Peak memory 238624 kb
Host smart-55078278-ddad-49f2-8691-7cb7f031e3ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772054712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.1772054712
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.721623426
Short name T1255
Test name
Test status
Simulation time 104380483 ps
CPU time 3.04 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 245812 kb
Host smart-cf237992-d38a-4963-b53a-a00368e864d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721623426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.721623426
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3144243175
Short name T1268
Test name
Test status
Simulation time 2333964560 ps
CPU time 19.21 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:36 PM PDT 24
Peak memory 244156 kb
Host smart-92c90f15-5f91-44e3-98d4-71dd0b4e2cff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144243175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.3144243175
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.4231489011
Short name T1326
Test name
Test status
Simulation time 146980918 ps
CPU time 2.26 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 245312 kb
Host smart-eeea1a65-c9f2-403e-94d4-e99c0407327a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231489011 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.4231489011
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3541524849
Short name T1316
Test name
Test status
Simulation time 39892003 ps
CPU time 1.5 seconds
Started Aug 04 05:31:15 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 240508 kb
Host smart-837ff3e5-4b15-4563-ac58-bbc41be865ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541524849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3541524849
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.297972431
Short name T1306
Test name
Test status
Simulation time 51675063 ps
CPU time 1.47 seconds
Started Aug 04 05:31:17 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 229936 kb
Host smart-cb779370-7d9c-4e9d-9c4f-444a7c8335b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297972431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.297972431
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2421683215
Short name T289
Test name
Test status
Simulation time 249651061 ps
CPU time 2.09 seconds
Started Aug 04 05:31:21 PM PDT 24
Finished Aug 04 05:31:24 PM PDT 24
Peak memory 238792 kb
Host smart-4a4a2b15-1152-4b68-a429-068cd97ab6d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421683215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.2421683215
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.244825222
Short name T1301
Test name
Test status
Simulation time 285669628 ps
CPU time 5.47 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 246292 kb
Host smart-3ea83391-b562-46a9-a07f-948029d2fcbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244825222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.244825222
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.4011824301
Short name T312
Test name
Test status
Simulation time 2404419054 ps
CPU time 19.95 seconds
Started Aug 04 05:31:15 PM PDT 24
Finished Aug 04 05:31:35 PM PDT 24
Peak memory 244372 kb
Host smart-d2db8cb3-7363-4c31-a6cb-9f9d77f3ee57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011824301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.4011824301
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1691424106
Short name T1322
Test name
Test status
Simulation time 205073624 ps
CPU time 3.65 seconds
Started Aug 04 05:31:25 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 246292 kb
Host smart-cd4a74c0-a398-46fd-90df-35d757957a72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691424106 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.1691424106
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3143129670
Short name T263
Test name
Test status
Simulation time 580836488 ps
CPU time 1.53 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:24 PM PDT 24
Peak memory 238748 kb
Host smart-66322271-3640-4926-b256-515eb7a14099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143129670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3143129670
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.676383357
Short name T1252
Test name
Test status
Simulation time 40861038 ps
CPU time 1.49 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:24 PM PDT 24
Peak memory 229928 kb
Host smart-4cb37166-b38f-47da-904a-31fde2d88dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676383357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.676383357
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2767059240
Short name T1240
Test name
Test status
Simulation time 149530284 ps
CPU time 2.44 seconds
Started Aug 04 05:31:17 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 238808 kb
Host smart-e37280f8-f658-4c9c-a332-704f461ec804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767059240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.2767059240
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.919364086
Short name T1271
Test name
Test status
Simulation time 234079653 ps
CPU time 4.55 seconds
Started Aug 04 05:31:20 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 246792 kb
Host smart-6807af72-20c8-4f5a-adf7-eda0b2e3f96e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919364086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.919364086
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.998521454
Short name T317
Test name
Test status
Simulation time 1271975049 ps
CPU time 20.57 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:43 PM PDT 24
Peak memory 238932 kb
Host smart-62ce9d7f-1779-4bc3-994d-414fe8ece9d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998521454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_in
tg_err.998521454
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1352072890
Short name T1228
Test name
Test status
Simulation time 155524975 ps
CPU time 2.24 seconds
Started Aug 04 05:31:19 PM PDT 24
Finished Aug 04 05:31:22 PM PDT 24
Peak memory 246880 kb
Host smart-7777a8e4-fdce-4c8e-b808-d4cdf64a85ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352072890 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1352072890
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2614192054
Short name T261
Test name
Test status
Simulation time 591854156 ps
CPU time 2.37 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:26 PM PDT 24
Peak memory 241184 kb
Host smart-29f79367-7c0b-47f4-8dff-e7a4311f7b30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614192054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.2614192054
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3663822005
Short name T1308
Test name
Test status
Simulation time 154553452 ps
CPU time 1.63 seconds
Started Aug 04 05:31:19 PM PDT 24
Finished Aug 04 05:31:21 PM PDT 24
Peak memory 230012 kb
Host smart-7a07d092-ff29-4fd1-8d9d-376020a7322a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663822005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3663822005
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.511171290
Short name T282
Test name
Test status
Simulation time 87481615 ps
CPU time 1.95 seconds
Started Aug 04 05:31:20 PM PDT 24
Finished Aug 04 05:31:22 PM PDT 24
Peak memory 241840 kb
Host smart-d2441ac5-7f0c-43b6-a345-6449694abd53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511171290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_c
trl_same_csr_outstanding.511171290
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1310397595
Short name T1194
Test name
Test status
Simulation time 80944819 ps
CPU time 5.2 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:22 PM PDT 24
Peak memory 246120 kb
Host smart-f27be83a-b5c5-4734-bd26-63db2fbc9e01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310397595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.1310397595
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1989807338
Short name T1205
Test name
Test status
Simulation time 384296518 ps
CPU time 3.58 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 247152 kb
Host smart-3de81cc9-e2de-4a33-a3e2-2ecf75a11661
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989807338 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.1989807338
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1999109184
Short name T265
Test name
Test status
Simulation time 526814931 ps
CPU time 2.01 seconds
Started Aug 04 05:31:24 PM PDT 24
Finished Aug 04 05:31:26 PM PDT 24
Peak memory 240840 kb
Host smart-e3df77d8-8608-4862-b1a5-f465dd6812e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999109184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.1999109184
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1313802599
Short name T1317
Test name
Test status
Simulation time 71751984 ps
CPU time 1.44 seconds
Started Aug 04 05:31:21 PM PDT 24
Finished Aug 04 05:31:22 PM PDT 24
Peak memory 230568 kb
Host smart-292ecbb8-bb2d-4428-b496-97460586239c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313802599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1313802599
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3346107175
Short name T1267
Test name
Test status
Simulation time 153850850 ps
CPU time 2.3 seconds
Started Aug 04 05:31:19 PM PDT 24
Finished Aug 04 05:31:21 PM PDT 24
Peak memory 238856 kb
Host smart-f0f43497-13fa-4bcb-ad48-0fd57b13c9c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346107175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.3346107175
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3136598920
Short name T1320
Test name
Test status
Simulation time 223459764 ps
CPU time 3.25 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:21 PM PDT 24
Peak memory 245828 kb
Host smart-103760d1-29e0-4a37-bf8f-aa293c727d4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136598920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3136598920
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.4069841124
Short name T1289
Test name
Test status
Simulation time 147707416 ps
CPU time 2.75 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 238896 kb
Host smart-5658a016-f0c2-4395-ab2c-9e0e1f4a8b4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069841124 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.4069841124
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2278160121
Short name T284
Test name
Test status
Simulation time 44136267 ps
CPU time 1.47 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 238684 kb
Host smart-21302a00-62a3-4346-bb76-e79154adcf20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278160121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2278160121
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.4021360249
Short name T1231
Test name
Test status
Simulation time 43605410 ps
CPU time 1.46 seconds
Started Aug 04 05:31:25 PM PDT 24
Finished Aug 04 05:31:32 PM PDT 24
Peak memory 229952 kb
Host smart-ff64d36c-617f-4d9e-abfc-df283cb89d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021360249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.4021360249
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.92831714
Short name T1244
Test name
Test status
Simulation time 136024829 ps
CPU time 3.63 seconds
Started Aug 04 05:31:25 PM PDT 24
Finished Aug 04 05:31:29 PM PDT 24
Peak memory 238584 kb
Host smart-484ca314-2cf8-4314-a003-8ccca03de624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92831714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ct
rl_same_csr_outstanding.92831714
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.589977798
Short name T1312
Test name
Test status
Simulation time 85069434 ps
CPU time 5 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 246076 kb
Host smart-105cdcee-a28e-413d-8c3f-588ea653026d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589977798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.589977798
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2679120387
Short name T315
Test name
Test status
Simulation time 1592448283 ps
CPU time 11.18 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:33 PM PDT 24
Peak memory 243364 kb
Host smart-83f0bb78-05a2-46cb-b278-126e90be9843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679120387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.2679120387
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1595742058
Short name T1254
Test name
Test status
Simulation time 376328022 ps
CPU time 3.55 seconds
Started Aug 04 05:31:20 PM PDT 24
Finished Aug 04 05:31:23 PM PDT 24
Peak memory 247092 kb
Host smart-ca4d1689-ff1e-40a6-9f67-3ebcb3adcaab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595742058 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.1595742058
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.4255207087
Short name T335
Test name
Test status
Simulation time 59353654 ps
CPU time 1.56 seconds
Started Aug 04 05:31:27 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 240952 kb
Host smart-917fd8c9-7e57-4c7f-aedb-68ad3f4a9600
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255207087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.4255207087
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1007424013
Short name T1249
Test name
Test status
Simulation time 40648480 ps
CPU time 1.42 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:24 PM PDT 24
Peak memory 229852 kb
Host smart-320baee1-562c-4e71-91fd-36d4592263b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007424013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1007424013
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2298833845
Short name T1298
Test name
Test status
Simulation time 147067997 ps
CPU time 2.4 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 238820 kb
Host smart-46bf162d-b9cf-4932-b850-bfe0f6dccc04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298833845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.2298833845
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1933578135
Short name T1201
Test name
Test status
Simulation time 1034788440 ps
CPU time 5.29 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 246004 kb
Host smart-aee8b597-802a-40d6-9e6d-419b4fe28837
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933578135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1933578135
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.4024317089
Short name T1300
Test name
Test status
Simulation time 1346258098 ps
CPU time 17.66 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:41 PM PDT 24
Peak memory 244964 kb
Host smart-87644cc0-4412-449b-8315-0deb942a1e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024317089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.4024317089
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3035710561
Short name T1209
Test name
Test status
Simulation time 165491673 ps
CPU time 1.78 seconds
Started Aug 04 05:31:17 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 240828 kb
Host smart-ec427caa-5d6f-4aa4-a180-92c788b9c853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035710561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3035710561
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3985127664
Short name T1203
Test name
Test status
Simulation time 142468134 ps
CPU time 1.39 seconds
Started Aug 04 05:31:21 PM PDT 24
Finished Aug 04 05:31:23 PM PDT 24
Peak memory 230168 kb
Host smart-d5b96395-a017-4d76-8685-56c4ce355a38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985127664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3985127664
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.558311815
Short name T1270
Test name
Test status
Simulation time 110080119 ps
CPU time 2.86 seconds
Started Aug 04 05:31:25 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 238752 kb
Host smart-1e4e81af-c516-4e34-848d-e06118c3e9f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558311815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c
trl_same_csr_outstanding.558311815
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.636243635
Short name T1303
Test name
Test status
Simulation time 1496898719 ps
CPU time 5.56 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 245660 kb
Host smart-e5698202-d5ff-4f9c-b474-f500d95715ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636243635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.636243635
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2369002044
Short name T313
Test name
Test status
Simulation time 1321086759 ps
CPU time 19.92 seconds
Started Aug 04 05:31:25 PM PDT 24
Finished Aug 04 05:31:45 PM PDT 24
Peak memory 238880 kb
Host smart-0d334c71-498e-4a75-8391-299b5b43cd8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369002044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.2369002044
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3934378265
Short name T1280
Test name
Test status
Simulation time 193277432 ps
CPU time 3.1 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:26 PM PDT 24
Peak memory 247140 kb
Host smart-c3f522f4-d4b5-4103-9e41-46261d47e6ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934378265 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.3934378265
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1228154031
Short name T1319
Test name
Test status
Simulation time 42428415 ps
CPU time 1.6 seconds
Started Aug 04 05:31:21 PM PDT 24
Finished Aug 04 05:31:23 PM PDT 24
Peak memory 240880 kb
Host smart-2b95656b-7ce1-454d-9f86-39bbabb32503
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228154031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.1228154031
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.895537644
Short name T1261
Test name
Test status
Simulation time 142142056 ps
CPU time 1.38 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 230240 kb
Host smart-05535902-04f5-4b20-ada3-1ba502f71111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895537644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.895537644
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2045625358
Short name T285
Test name
Test status
Simulation time 240271636 ps
CPU time 2.17 seconds
Started Aug 04 05:31:25 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 241816 kb
Host smart-94540f21-33f3-4ea3-8d7c-ebd0672afe70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045625358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.2045625358
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1643660443
Short name T1200
Test name
Test status
Simulation time 248968501 ps
CPU time 4.47 seconds
Started Aug 04 05:31:24 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 245784 kb
Host smart-d0ef4502-5628-46e9-8de6-a7d310c4bc13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643660443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1643660443
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1954502424
Short name T1276
Test name
Test status
Simulation time 1242570164 ps
CPU time 10.14 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:37 PM PDT 24
Peak memory 238840 kb
Host smart-23e01a0e-7229-4c0a-b57a-e46ead501632
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954502424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.1954502424
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1084599232
Short name T1275
Test name
Test status
Simulation time 72132965 ps
CPU time 2.21 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:29 PM PDT 24
Peak memory 244500 kb
Host smart-0f439dea-0d82-4607-8f9f-59fd33c8b7b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084599232 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1084599232
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3432922466
Short name T270
Test name
Test status
Simulation time 133877476 ps
CPU time 1.58 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 240500 kb
Host smart-df1b4367-a225-4e7d-a139-6fd72c4a101e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432922466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3432922466
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2402646264
Short name T1315
Test name
Test status
Simulation time 531753033 ps
CPU time 1.64 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 229804 kb
Host smart-8a058d98-c2a8-4293-8f8b-901a059b13bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402646264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2402646264
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.2782568951
Short name T1283
Test name
Test status
Simulation time 495794706 ps
CPU time 3.7 seconds
Started Aug 04 05:31:42 PM PDT 24
Finished Aug 04 05:31:46 PM PDT 24
Peak memory 241936 kb
Host smart-b36d5715-7e13-4e29-b1dc-f85ddbfdaf37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782568951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.2782568951
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3375718753
Short name T1242
Test name
Test status
Simulation time 226073795 ps
CPU time 4.22 seconds
Started Aug 04 05:31:27 PM PDT 24
Finished Aug 04 05:31:32 PM PDT 24
Peak memory 245936 kb
Host smart-773c8acb-8007-4b4f-a26c-58fc81c41f90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375718753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3375718753
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2605826202
Short name T1282
Test name
Test status
Simulation time 83228935 ps
CPU time 2.04 seconds
Started Aug 04 05:31:24 PM PDT 24
Finished Aug 04 05:31:26 PM PDT 24
Peak memory 244744 kb
Host smart-2911df71-3ae0-4d3d-a602-a013f6032f2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605826202 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.2605826202
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2718454369
Short name T1259
Test name
Test status
Simulation time 572684218 ps
CPU time 2.17 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 240920 kb
Host smart-a16458b7-07ae-452f-a62a-99f00e77bd8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718454369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.2718454369
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3398367981
Short name T1227
Test name
Test status
Simulation time 537045006 ps
CPU time 1.7 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 229956 kb
Host smart-00989bdd-c127-40ef-93b9-81234c2b21e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398367981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3398367981
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.143628135
Short name T1321
Test name
Test status
Simulation time 75740714 ps
CPU time 2.35 seconds
Started Aug 04 05:31:48 PM PDT 24
Finished Aug 04 05:31:51 PM PDT 24
Peak memory 238684 kb
Host smart-6cf1f2f1-a31b-4074-a555-e08279eaa497
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143628135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_c
trl_same_csr_outstanding.143628135
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2507601727
Short name T1232
Test name
Test status
Simulation time 203193246 ps
CPU time 3.4 seconds
Started Aug 04 05:31:31 PM PDT 24
Finished Aug 04 05:31:34 PM PDT 24
Peak memory 245792 kb
Host smart-eeac5db4-d78d-4d8b-9f79-5e137bf67dae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507601727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2507601727
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2340521566
Short name T318
Test name
Test status
Simulation time 5519984944 ps
CPU time 20.54 seconds
Started Aug 04 05:31:27 PM PDT 24
Finished Aug 04 05:31:48 PM PDT 24
Peak memory 245828 kb
Host smart-f6e88f0a-b290-495a-a55b-032603549405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340521566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.2340521566
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.4291082270
Short name T1219
Test name
Test status
Simulation time 156745410 ps
CPU time 4.79 seconds
Started Aug 04 05:31:11 PM PDT 24
Finished Aug 04 05:31:16 PM PDT 24
Peak memory 241516 kb
Host smart-7b980df7-5a3b-43b5-8d36-63f1b69b706f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291082270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.4291082270
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2971217259
Short name T1251
Test name
Test status
Simulation time 536155140 ps
CPU time 6.28 seconds
Started Aug 04 05:31:14 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 238976 kb
Host smart-a5268a77-1c59-45b3-9d89-fdb62f195b57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971217259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.2971217259
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.115427311
Short name T267
Test name
Test status
Simulation time 128225359 ps
CPU time 1.9 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:18 PM PDT 24
Peak memory 240956 kb
Host smart-ffe8332e-be55-40bd-abda-db1dd40b0906
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115427311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_re
set.115427311
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3121922210
Short name T1229
Test name
Test status
Simulation time 425560993 ps
CPU time 3.39 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:21 PM PDT 24
Peak memory 247048 kb
Host smart-fa217a96-198e-4c2c-af75-12e4d62e70cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121922210 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.3121922210
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.238282774
Short name T266
Test name
Test status
Simulation time 700059456 ps
CPU time 2.12 seconds
Started Aug 04 05:31:07 PM PDT 24
Finished Aug 04 05:31:09 PM PDT 24
Peak memory 238808 kb
Host smart-df084590-cda9-4632-a4d6-1dde0c059772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238282774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.238282774
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1966786
Short name T1221
Test name
Test status
Simulation time 137692791 ps
CPU time 1.36 seconds
Started Aug 04 05:31:15 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 230244 kb
Host smart-a3ac99a8-e1f3-4428-8cf7-2d444c31555e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1966786
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1689505778
Short name T1202
Test name
Test status
Simulation time 37262982 ps
CPU time 1.34 seconds
Started Aug 04 05:31:12 PM PDT 24
Finished Aug 04 05:31:14 PM PDT 24
Peak memory 229864 kb
Host smart-16f5eeb8-7963-4c37-b51f-17d448581682
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689505778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.1689505778
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2988155784
Short name T1273
Test name
Test status
Simulation time 71381317 ps
CPU time 1.37 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:33 PM PDT 24
Peak memory 230064 kb
Host smart-afcb9384-66c0-4619-ae2e-0fc6000d0cfa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988155784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.2988155784
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1130573584
Short name T288
Test name
Test status
Simulation time 288866653 ps
CPU time 2.51 seconds
Started Aug 04 05:31:07 PM PDT 24
Finished Aug 04 05:31:10 PM PDT 24
Peak memory 238592 kb
Host smart-5e5eee82-67ca-4cf8-9e56-18566dab6565
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130573584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.1130573584
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2371094400
Short name T1212
Test name
Test status
Simulation time 2667648974 ps
CPU time 7.44 seconds
Started Aug 04 05:31:05 PM PDT 24
Finished Aug 04 05:31:13 PM PDT 24
Peak memory 238916 kb
Host smart-360f5c2e-c7dd-4516-8f10-789688f0c4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371094400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2371094400
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1359377986
Short name T1224
Test name
Test status
Simulation time 75434343 ps
CPU time 1.35 seconds
Started Aug 04 05:31:20 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 230224 kb
Host smart-d701fd17-8e6a-46db-ba5a-751a3e7dcd12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359377986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1359377986
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.4282992999
Short name T1210
Test name
Test status
Simulation time 40184756 ps
CPU time 1.37 seconds
Started Aug 04 05:31:21 PM PDT 24
Finished Aug 04 05:31:23 PM PDT 24
Peak memory 229920 kb
Host smart-ac070775-134a-4c33-b95e-fbd95985c878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282992999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.4282992999
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.3278522254
Short name T1235
Test name
Test status
Simulation time 40093780 ps
CPU time 1.37 seconds
Started Aug 04 05:31:28 PM PDT 24
Finished Aug 04 05:31:30 PM PDT 24
Peak memory 230184 kb
Host smart-a67163c5-2c4a-4aa7-a4ca-523d6453e09f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278522254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.3278522254
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1465183426
Short name T1239
Test name
Test status
Simulation time 44937055 ps
CPU time 1.42 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 229980 kb
Host smart-745d06d1-a6b8-4903-aeb9-9a50b5733937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465183426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1465183426
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3456610117
Short name T1216
Test name
Test status
Simulation time 145806188 ps
CPU time 1.43 seconds
Started Aug 04 05:31:46 PM PDT 24
Finished Aug 04 05:31:48 PM PDT 24
Peak memory 230536 kb
Host smart-5950fb20-909c-4ea1-bd03-9defb2eb1d09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456610117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3456610117
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.2397120501
Short name T1223
Test name
Test status
Simulation time 41286956 ps
CPU time 1.39 seconds
Started Aug 04 05:31:38 PM PDT 24
Finished Aug 04 05:31:39 PM PDT 24
Peak memory 230540 kb
Host smart-d1d20504-68f8-4df1-95f6-750d32a27679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397120501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.2397120501
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1375582732
Short name T1208
Test name
Test status
Simulation time 588577185 ps
CPU time 1.7 seconds
Started Aug 04 05:31:28 PM PDT 24
Finished Aug 04 05:31:29 PM PDT 24
Peak memory 229996 kb
Host smart-4af0a398-576c-42bd-b12b-1cadfa3ef1ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375582732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1375582732
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2209189363
Short name T1269
Test name
Test status
Simulation time 75872243 ps
CPU time 1.46 seconds
Started Aug 04 05:31:28 PM PDT 24
Finished Aug 04 05:31:30 PM PDT 24
Peak memory 229944 kb
Host smart-af0da4db-4957-4906-ae96-806b374e748c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209189363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2209189363
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2197289728
Short name T1199
Test name
Test status
Simulation time 53613823 ps
CPU time 1.48 seconds
Started Aug 04 05:31:24 PM PDT 24
Finished Aug 04 05:31:26 PM PDT 24
Peak memory 229892 kb
Host smart-ed08e5c9-a72b-4fa8-83da-4383c5ce4ab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197289728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2197289728
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.3578152819
Short name T1234
Test name
Test status
Simulation time 81512420 ps
CPU time 1.36 seconds
Started Aug 04 05:31:43 PM PDT 24
Finished Aug 04 05:31:44 PM PDT 24
Peak memory 229856 kb
Host smart-d2ccf8ea-d02a-44b9-ba7e-618c65cb6d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578152819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.3578152819
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2709620544
Short name T280
Test name
Test status
Simulation time 100726368 ps
CPU time 3.6 seconds
Started Aug 04 05:31:14 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 238800 kb
Host smart-a054e84f-6936-41ad-990b-6a576940c9fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709620544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2709620544
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3562347380
Short name T233
Test name
Test status
Simulation time 5601824047 ps
CPU time 9.88 seconds
Started Aug 04 05:31:21 PM PDT 24
Finished Aug 04 05:31:31 PM PDT 24
Peak memory 238844 kb
Host smart-d249196f-db7b-49b3-8821-c25d9b545fe0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562347380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.3562347380
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3001620570
Short name T268
Test name
Test status
Simulation time 227161208 ps
CPU time 2.37 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:34 PM PDT 24
Peak memory 247024 kb
Host smart-4339ede7-ceec-4a2b-88cc-306fc9dc270e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001620570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.3001620570
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.4127386180
Short name T1206
Test name
Test status
Simulation time 110481192 ps
CPU time 3.79 seconds
Started Aug 04 05:31:24 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 247116 kb
Host smart-b6e727b5-ca1e-4fcf-93b2-1e582f729d5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127386180 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.4127386180
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.581447992
Short name T1214
Test name
Test status
Simulation time 156583091 ps
CPU time 1.52 seconds
Started Aug 04 05:31:21 PM PDT 24
Finished Aug 04 05:31:23 PM PDT 24
Peak memory 229936 kb
Host smart-4540a372-06ad-4cf9-9913-49c0ebb40b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581447992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.581447992
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2594811459
Short name T1286
Test name
Test status
Simulation time 40350122 ps
CPU time 1.32 seconds
Started Aug 04 05:31:20 PM PDT 24
Finished Aug 04 05:31:22 PM PDT 24
Peak memory 229692 kb
Host smart-a32edb87-3329-4050-8bc4-064da26c1aa1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594811459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.2594811459
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3318608616
Short name T1257
Test name
Test status
Simulation time 39472734 ps
CPU time 1.38 seconds
Started Aug 04 05:31:17 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 229672 kb
Host smart-346c4b75-6026-4f03-8dfe-5f77f1d16213
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318608616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.3318608616
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3929325716
Short name T1246
Test name
Test status
Simulation time 113594836 ps
CPU time 2.86 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 242076 kb
Host smart-87b1d0c0-02f1-484b-9a26-81becb4a2ed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929325716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.3929325716
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1878321949
Short name T1325
Test name
Test status
Simulation time 554812149 ps
CPU time 5.32 seconds
Started Aug 04 05:31:24 PM PDT 24
Finished Aug 04 05:31:30 PM PDT 24
Peak memory 238816 kb
Host smart-216d5000-2788-477c-83d5-75d7416f8a49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878321949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1878321949
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.225118406
Short name T231
Test name
Test status
Simulation time 10243069415 ps
CPU time 12.27 seconds
Started Aug 04 05:31:17 PM PDT 24
Finished Aug 04 05:31:30 PM PDT 24
Peak memory 244320 kb
Host smart-6921e6aa-5951-40c5-a320-3cc7f54b59c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225118406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_int
g_err.225118406
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2657601476
Short name T1230
Test name
Test status
Simulation time 42372550 ps
CPU time 1.42 seconds
Started Aug 04 05:31:27 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 230636 kb
Host smart-ec011485-36c6-4286-b1d9-6184a290b805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657601476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.2657601476
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3293977561
Short name T1256
Test name
Test status
Simulation time 44193210 ps
CPU time 1.42 seconds
Started Aug 04 05:31:45 PM PDT 24
Finished Aug 04 05:31:47 PM PDT 24
Peak memory 230532 kb
Host smart-7f3efbbc-ccd0-4ca2-a6fe-61a825807d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293977561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3293977561
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.191531310
Short name T1311
Test name
Test status
Simulation time 105621588 ps
CPU time 1.37 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 230644 kb
Host smart-3b5eaabb-74ab-4f95-9f0a-67dbbfbba904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191531310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.191531310
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2835324056
Short name T1204
Test name
Test status
Simulation time 144784285 ps
CPU time 1.36 seconds
Started Aug 04 05:31:25 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 230636 kb
Host smart-3aa7784d-7790-4cc1-b421-687ce264c21a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835324056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2835324056
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2165169302
Short name T1233
Test name
Test status
Simulation time 132029221 ps
CPU time 1.38 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 230180 kb
Host smart-1a825e89-74de-462b-b2f4-959f962dc4a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165169302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2165169302
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1971850862
Short name T1226
Test name
Test status
Simulation time 132065674 ps
CPU time 1.41 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 230208 kb
Host smart-28090c22-1b75-4d71-875c-0356d7940017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971850862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.1971850862
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1939514910
Short name T1266
Test name
Test status
Simulation time 43890369 ps
CPU time 1.39 seconds
Started Aug 04 05:31:24 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 229920 kb
Host smart-25895919-bd69-47ac-b074-3057c03f9841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939514910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1939514910
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.1441799410
Short name T1323
Test name
Test status
Simulation time 118974542 ps
CPU time 1.42 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 230648 kb
Host smart-3bd8ec1c-d996-49ed-a100-2f72d3438ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441799410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.1441799410
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2883779553
Short name T1294
Test name
Test status
Simulation time 136827410 ps
CPU time 1.37 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 230496 kb
Host smart-2e600dba-13bf-4bc4-b463-ec63715c1337
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883779553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2883779553
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3796937032
Short name T1313
Test name
Test status
Simulation time 44160615 ps
CPU time 1.49 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 230664 kb
Host smart-6397330d-3a48-4b85-b03c-6954fee68006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796937032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.3796937032
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4245745875
Short name T1225
Test name
Test status
Simulation time 873528701 ps
CPU time 3.84 seconds
Started Aug 04 05:31:15 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 238852 kb
Host smart-02234f2a-f381-4800-93b8-122c793cc6cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245745875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.4245745875
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.649045019
Short name T1248
Test name
Test status
Simulation time 3723897006 ps
CPU time 7.73 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:23 PM PDT 24
Peak memory 238848 kb
Host smart-1f4e75a8-8e89-496b-bdba-4a28227c4d85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649045019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b
ash.649045019
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.4047250170
Short name T269
Test name
Test status
Simulation time 281723897 ps
CPU time 1.9 seconds
Started Aug 04 05:31:14 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 240552 kb
Host smart-43dc5806-f25a-479f-bb13-bad2916a3749
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047250170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.4047250170
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.4012194333
Short name T1250
Test name
Test status
Simulation time 348001310 ps
CPU time 3.08 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 247156 kb
Host smart-25a1d9da-7604-42c2-aa3a-f78bab8ac3f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012194333 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.4012194333
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2120935247
Short name T1292
Test name
Test status
Simulation time 635538024 ps
CPU time 2.26 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 240864 kb
Host smart-90cfdd7f-7399-44e9-a6ba-f30a9ebea91b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120935247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2120935247
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.354309378
Short name T1215
Test name
Test status
Simulation time 37613298 ps
CPU time 1.41 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:24 PM PDT 24
Peak memory 230664 kb
Host smart-faefc0a9-fe73-4b6c-88e1-490b2fc5027e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354309378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.354309378
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.4289055926
Short name T1243
Test name
Test status
Simulation time 543450293 ps
CPU time 1.47 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 229564 kb
Host smart-d20472f3-c962-45dd-a7bd-13f2ac0e717e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289055926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.4289055926
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3343840809
Short name T1281
Test name
Test status
Simulation time 124277846 ps
CPU time 1.37 seconds
Started Aug 04 05:31:17 PM PDT 24
Finished Aug 04 05:31:18 PM PDT 24
Peak memory 229888 kb
Host smart-739686b0-967a-490a-a728-9ea9562fec0c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343840809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.3343840809
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1238595579
Short name T1247
Test name
Test status
Simulation time 186876770 ps
CPU time 1.95 seconds
Started Aug 04 05:31:15 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 241856 kb
Host smart-c415c6a0-7da1-49fc-8fd7-aadda21b324a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238595579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.1238595579
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.686844848
Short name T1193
Test name
Test status
Simulation time 54823209 ps
CPU time 2.76 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:21 PM PDT 24
Peak memory 238824 kb
Host smart-a517cca7-1d7d-4e18-91fe-4eca91ed5ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686844848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.686844848
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.3673506131
Short name T1299
Test name
Test status
Simulation time 136298843 ps
CPU time 1.44 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 229712 kb
Host smart-091566b1-0e1a-4b9f-b2eb-bd6d9e3024e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673506131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.3673506131
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1852281485
Short name T1262
Test name
Test status
Simulation time 562685278 ps
CPU time 1.97 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 230212 kb
Host smart-b2b00ee3-0b9b-4091-9408-ac06f9b4a0f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852281485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1852281485
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3412255988
Short name T1279
Test name
Test status
Simulation time 79107805 ps
CPU time 1.51 seconds
Started Aug 04 05:31:25 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 229936 kb
Host smart-cc29e792-19bb-4280-9801-9dbd14396a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412255988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.3412255988
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.675474025
Short name T1197
Test name
Test status
Simulation time 102526379 ps
CPU time 1.53 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 229896 kb
Host smart-f01959e1-5e08-4e97-978b-904bf183dd44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675474025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.675474025
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.4020103935
Short name T1288
Test name
Test status
Simulation time 582451109 ps
CPU time 1.57 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 230232 kb
Host smart-db39a9c4-5291-4f29-b47a-65aa7db180b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020103935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.4020103935
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3144682151
Short name T1207
Test name
Test status
Simulation time 524638014 ps
CPU time 1.48 seconds
Started Aug 04 05:31:33 PM PDT 24
Finished Aug 04 05:31:35 PM PDT 24
Peak memory 229944 kb
Host smart-e48aed28-a4a1-4aef-8c51-74604bfa218b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144682151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.3144682151
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.4209348827
Short name T1211
Test name
Test status
Simulation time 38844035 ps
CPU time 1.46 seconds
Started Aug 04 05:31:24 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 229940 kb
Host smart-2336f541-9261-402f-84cb-dad20f39f8ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209348827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.4209348827
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.2861942697
Short name T1302
Test name
Test status
Simulation time 82462170 ps
CPU time 1.38 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 230688 kb
Host smart-7ff5a727-f2fe-474d-8833-4f9f1aa6e62c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861942697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.2861942697
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.334507152
Short name T1285
Test name
Test status
Simulation time 72664550 ps
CPU time 1.44 seconds
Started Aug 04 05:31:25 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 230624 kb
Host smart-8eb87b34-b59a-4a2a-b4e5-2c181f44927d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334507152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.334507152
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3681854003
Short name T1265
Test name
Test status
Simulation time 85397529 ps
CPU time 1.45 seconds
Started Aug 04 05:31:28 PM PDT 24
Finished Aug 04 05:31:29 PM PDT 24
Peak memory 229932 kb
Host smart-b7319059-5ebf-4c54-b5fe-c12dfbadd226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681854003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3681854003
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.403531479
Short name T1237
Test name
Test status
Simulation time 197978402 ps
CPU time 3.52 seconds
Started Aug 04 05:31:14 PM PDT 24
Finished Aug 04 05:31:18 PM PDT 24
Peak memory 247132 kb
Host smart-e8dfa37a-d035-41d1-8ad4-958fa579efc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403531479 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.403531479
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3867026758
Short name T281
Test name
Test status
Simulation time 40199850 ps
CPU time 1.52 seconds
Started Aug 04 05:31:19 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 240468 kb
Host smart-09f7e604-33e1-4f9f-afe6-685cdabf07c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867026758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3867026758
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.154624473
Short name T1277
Test name
Test status
Simulation time 37628893 ps
CPU time 1.39 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 229992 kb
Host smart-cbc23eae-4fb7-4b13-9545-20975723b46c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154624473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.154624473
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1255511449
Short name T1222
Test name
Test status
Simulation time 115517715 ps
CPU time 3.02 seconds
Started Aug 04 05:31:21 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 238912 kb
Host smart-310cea25-8b1e-4b31-aea1-832c024b20f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255511449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1255511449
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.892938236
Short name T1220
Test name
Test status
Simulation time 300254510 ps
CPU time 6.31 seconds
Started Aug 04 05:31:27 PM PDT 24
Finished Aug 04 05:31:38 PM PDT 24
Peak memory 246824 kb
Host smart-15e3641c-2b93-470a-ae0e-66bfd706fc4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892938236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.892938236
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.289144189
Short name T319
Test name
Test status
Simulation time 1574010855 ps
CPU time 11.74 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 243580 kb
Host smart-15379b6d-285f-4d7c-8cda-16f07649cd87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289144189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_int
g_err.289144189
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3579348749
Short name T1236
Test name
Test status
Simulation time 1073747398 ps
CPU time 3.66 seconds
Started Aug 04 05:31:15 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 238932 kb
Host smart-30d2f959-f1ea-421d-8d11-fb5bab177ac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579348749 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.3579348749
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.552690818
Short name T1274
Test name
Test status
Simulation time 38027241 ps
CPU time 1.61 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:18 PM PDT 24
Peak memory 240576 kb
Host smart-14cd3c12-2fe4-4ac3-bc98-31e21524f05f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552690818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.552690818
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2205568358
Short name T1213
Test name
Test status
Simulation time 72361189 ps
CPU time 1.4 seconds
Started Aug 04 05:31:15 PM PDT 24
Finished Aug 04 05:31:17 PM PDT 24
Peak memory 230184 kb
Host smart-2c7ca03d-b5f4-445c-99ec-d8f6f7cd5cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205568358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2205568358
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.4157482062
Short name T1304
Test name
Test status
Simulation time 94699266 ps
CPU time 2.97 seconds
Started Aug 04 05:31:27 PM PDT 24
Finished Aug 04 05:31:35 PM PDT 24
Peak memory 241956 kb
Host smart-a8eea109-c046-435b-af7f-fd09e28eb863
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157482062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.4157482062
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.560304593
Short name T1310
Test name
Test status
Simulation time 1771349662 ps
CPU time 4.82 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:23 PM PDT 24
Peak memory 245944 kb
Host smart-acf16c97-c912-4028-a397-4ccc8cf5b7bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560304593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.560304593
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.4263864635
Short name T1314
Test name
Test status
Simulation time 2590069509 ps
CPU time 14.21 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:38 PM PDT 24
Peak memory 243988 kb
Host smart-5fb5837c-4b91-42b0-8dbd-fd5c8aaddec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263864635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.4263864635
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3450136218
Short name T1305
Test name
Test status
Simulation time 424787152 ps
CPU time 3.31 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 246992 kb
Host smart-0a12ebc4-0fae-4da4-8bed-916e24c419a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450136218 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.3450136218
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3480472454
Short name T262
Test name
Test status
Simulation time 98705556 ps
CPU time 1.47 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:18 PM PDT 24
Peak memory 238864 kb
Host smart-043a7e2f-e63c-4e9f-912c-68a2d3171de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480472454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3480472454
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3395358449
Short name T1272
Test name
Test status
Simulation time 67636663 ps
CPU time 1.33 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 230560 kb
Host smart-a715c424-b1d0-4c3d-992f-e19ed335a7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395358449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3395358449
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.927810766
Short name T1287
Test name
Test status
Simulation time 1240345636 ps
CPU time 3.65 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 238788 kb
Host smart-126f638e-7f13-4c5d-b5bd-0de73f107b91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927810766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ct
rl_same_csr_outstanding.927810766
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1750252100
Short name T1278
Test name
Test status
Simulation time 1027442433 ps
CPU time 4.74 seconds
Started Aug 04 05:31:24 PM PDT 24
Finished Aug 04 05:31:29 PM PDT 24
Peak memory 245896 kb
Host smart-ecad5dff-45bd-41ff-ab87-90fa236109d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750252100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.1750252100
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.25273439
Short name T316
Test name
Test status
Simulation time 1497199333 ps
CPU time 9.22 seconds
Started Aug 04 05:31:19 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 238832 kb
Host smart-98b127d6-90e5-491b-9ca1-1ddf7683ffc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25273439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg
_err.25273439
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3797196135
Short name T1296
Test name
Test status
Simulation time 98506294 ps
CPU time 2.88 seconds
Started Aug 04 05:31:25 PM PDT 24
Finished Aug 04 05:31:29 PM PDT 24
Peak memory 247112 kb
Host smart-6b122da9-b37e-4952-b94e-7f16d0dc3b49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797196135 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.3797196135
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.4203818944
Short name T1297
Test name
Test status
Simulation time 86844691 ps
CPU time 1.54 seconds
Started Aug 04 05:31:19 PM PDT 24
Finished Aug 04 05:31:21 PM PDT 24
Peak memory 240472 kb
Host smart-ea682751-56d3-45de-b79c-91832f297336
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203818944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.4203818944
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.1938410337
Short name T1307
Test name
Test status
Simulation time 129341842 ps
CPU time 1.45 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:19 PM PDT 24
Peak memory 229880 kb
Host smart-10a4f4dc-d860-4cde-8353-3ce7bd435912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938410337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1938410337
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2193775539
Short name T1238
Test name
Test status
Simulation time 148975111 ps
CPU time 2.3 seconds
Started Aug 04 05:31:23 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 238812 kb
Host smart-65c3bf94-fb9b-4b7b-83ed-80be9a382fc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193775539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.2193775539
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3903804263
Short name T1195
Test name
Test status
Simulation time 346536620 ps
CPU time 6.22 seconds
Started Aug 04 05:31:19 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 238944 kb
Host smart-8d5ab5a6-6ed0-4c39-af4c-e068703c3880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903804263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3903804263
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3532674322
Short name T311
Test name
Test status
Simulation time 1188285483 ps
CPU time 16.64 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:35 PM PDT 24
Peak memory 243964 kb
Host smart-b58e441e-9984-4cbf-8f96-7bec9b9a6d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532674322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.3532674322
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1745319278
Short name T1291
Test name
Test status
Simulation time 384879031 ps
CPU time 2.98 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:25 PM PDT 24
Peak memory 246452 kb
Host smart-97c1c027-b2ab-4e72-b723-9506005f26e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745319278 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1745319278
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1293052100
Short name T1324
Test name
Test status
Simulation time 140045098 ps
CPU time 1.6 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 240772 kb
Host smart-e42c87fb-2da1-47de-94ef-b6a0bbcdf166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293052100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1293052100
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.607111123
Short name T1245
Test name
Test status
Simulation time 572966798 ps
CPU time 1.56 seconds
Started Aug 04 05:31:22 PM PDT 24
Finished Aug 04 05:31:24 PM PDT 24
Peak memory 230660 kb
Host smart-7288e9ff-1e88-44cb-8633-06d6ddceb773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607111123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.607111123
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.841193855
Short name T1290
Test name
Test status
Simulation time 171137916 ps
CPU time 1.91 seconds
Started Aug 04 05:31:18 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 238868 kb
Host smart-1c90cb06-ba00-4fb2-8964-99a8a491b521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841193855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct
rl_same_csr_outstanding.841193855
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.424428480
Short name T1295
Test name
Test status
Simulation time 886702707 ps
CPU time 4.06 seconds
Started Aug 04 05:31:16 PM PDT 24
Finished Aug 04 05:31:20 PM PDT 24
Peak memory 238924 kb
Host smart-e8b15da5-2403-4d5a-9d17-65ac86555c74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424428480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.424428480
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3390547713
Short name T232
Test name
Test status
Simulation time 891044252 ps
CPU time 13.39 seconds
Started Aug 04 05:31:20 PM PDT 24
Finished Aug 04 05:31:34 PM PDT 24
Peak memory 243420 kb
Host smart-14da1e1f-d3c4-4825-82ac-bc7e0681abb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390547713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.3390547713
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.3942065118
Short name T1034
Test name
Test status
Simulation time 159420287 ps
CPU time 1.7 seconds
Started Aug 04 05:24:26 PM PDT 24
Finished Aug 04 05:24:28 PM PDT 24
Peak memory 240732 kb
Host smart-ff7d4398-9e1c-47dd-8a7a-c67547f43678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942065118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3942065118
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.3539170954
Short name T1142
Test name
Test status
Simulation time 1375253506 ps
CPU time 28.48 seconds
Started Aug 04 05:24:20 PM PDT 24
Finished Aug 04 05:24:49 PM PDT 24
Peak memory 242180 kb
Host smart-0a5c3136-1b85-4b27-b3c2-eb39bf079aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539170954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3539170954
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.2743510075
Short name T63
Test name
Test status
Simulation time 374413864 ps
CPU time 9.19 seconds
Started Aug 04 05:24:26 PM PDT 24
Finished Aug 04 05:24:35 PM PDT 24
Peak memory 248600 kb
Host smart-e7acd6d9-d780-49ef-8d0d-1bf8f4ee38c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743510075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2743510075
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.3504605569
Short name T1104
Test name
Test status
Simulation time 1477647429 ps
CPU time 33.83 seconds
Started Aug 04 05:24:25 PM PDT 24
Finished Aug 04 05:24:59 PM PDT 24
Peak memory 242796 kb
Host smart-c414907f-b109-4d62-be35-d7a448113a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504605569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.3504605569
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.1672226757
Short name T1106
Test name
Test status
Simulation time 1356472101 ps
CPU time 24.42 seconds
Started Aug 04 05:24:21 PM PDT 24
Finished Aug 04 05:24:45 PM PDT 24
Peak memory 241996 kb
Host smart-c571f852-453f-495a-8d3b-6e100b82c82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672226757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1672226757
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.2977499415
Short name T1154
Test name
Test status
Simulation time 131837026 ps
CPU time 3.83 seconds
Started Aug 04 05:24:20 PM PDT 24
Finished Aug 04 05:24:24 PM PDT 24
Peak memory 241944 kb
Host smart-28c9874a-8cde-458f-ad77-b35f4f574a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977499415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.2977499415
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.1621739240
Short name T714
Test name
Test status
Simulation time 5939826070 ps
CPU time 14.76 seconds
Started Aug 04 05:24:21 PM PDT 24
Finished Aug 04 05:24:35 PM PDT 24
Peak memory 240700 kb
Host smart-f296e4fc-ce24-4693-85e6-10fe92aa15f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621739240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1621739240
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.781175165
Short name T152
Test name
Test status
Simulation time 1680990386 ps
CPU time 23.51 seconds
Started Aug 04 05:24:25 PM PDT 24
Finished Aug 04 05:24:49 PM PDT 24
Peak memory 244228 kb
Host smart-2e7d8cea-767e-4b7e-9211-04323b5dc3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781175165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.781175165
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.3984091914
Short name T95
Test name
Test status
Simulation time 2952865545 ps
CPU time 31.74 seconds
Started Aug 04 05:24:28 PM PDT 24
Finished Aug 04 05:25:00 PM PDT 24
Peak memory 248656 kb
Host smart-4ff4e01e-d7ed-464b-9f45-5603be850c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984091914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.3984091914
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.3668734652
Short name T926
Test name
Test status
Simulation time 126746610 ps
CPU time 5.61 seconds
Started Aug 04 05:24:20 PM PDT 24
Finished Aug 04 05:24:26 PM PDT 24
Peak memory 241784 kb
Host smart-8fc4ce59-f821-4174-9166-9602626db035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668734652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3668734652
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.2690449127
Short name T1139
Test name
Test status
Simulation time 7974108611 ps
CPU time 27.46 seconds
Started Aug 04 05:24:21 PM PDT 24
Finished Aug 04 05:24:48 PM PDT 24
Peak memory 241944 kb
Host smart-44658b1c-89d7-41e8-974d-f7247fc044a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2690449127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2690449127
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.2829773429
Short name T854
Test name
Test status
Simulation time 5110628854 ps
CPU time 26.93 seconds
Started Aug 04 05:24:22 PM PDT 24
Finished Aug 04 05:24:49 PM PDT 24
Peak memory 241596 kb
Host smart-e36de53b-6aa0-4803-b4d4-a9828f72fe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829773429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2829773429
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.1374014424
Short name T721
Test name
Test status
Simulation time 252990216 ps
CPU time 9.89 seconds
Started Aug 04 05:24:26 PM PDT 24
Finished Aug 04 05:24:35 PM PDT 24
Peak memory 242072 kb
Host smart-64452c3f-371b-4409-a8cc-f880fb06c4f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374014424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1374014424
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.149649772
Short name T657
Test name
Test status
Simulation time 807693232 ps
CPU time 11.22 seconds
Started Aug 04 05:24:21 PM PDT 24
Finished Aug 04 05:24:33 PM PDT 24
Peak memory 242080 kb
Host smart-380b5daf-9c60-4a55-9232-bb51878ade83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149649772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.149649772
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.1230052312
Short name T1140
Test name
Test status
Simulation time 48726512445 ps
CPU time 217.15 seconds
Started Aug 04 05:24:25 PM PDT 24
Finished Aug 04 05:28:03 PM PDT 24
Peak memory 259152 kb
Host smart-a57e2e55-0899-402e-a75a-54ab4860ea9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230052312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
1230052312
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3679655966
Short name T67
Test name
Test status
Simulation time 41359046244 ps
CPU time 607.98 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:34:38 PM PDT 24
Peak memory 285808 kb
Host smart-4fbf3f1e-43f9-4abb-9d59-5e2067778acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679655966 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.3679655966
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.2070713994
Short name T180
Test name
Test status
Simulation time 1497615702 ps
CPU time 17.38 seconds
Started Aug 04 05:24:24 PM PDT 24
Finished Aug 04 05:24:42 PM PDT 24
Peak memory 242252 kb
Host smart-41a82302-e666-4c33-b6fb-69144c3873b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070713994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2070713994
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.2720944001
Short name T554
Test name
Test status
Simulation time 175127195 ps
CPU time 1.96 seconds
Started Aug 04 05:24:31 PM PDT 24
Finished Aug 04 05:24:33 PM PDT 24
Peak memory 240620 kb
Host smart-daddd94a-d68d-4bad-a9f4-2f61e7ba4770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720944001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.2720944001
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.2369198018
Short name T451
Test name
Test status
Simulation time 6917698826 ps
CPU time 18.17 seconds
Started Aug 04 05:24:27 PM PDT 24
Finished Aug 04 05:24:46 PM PDT 24
Peak memory 242168 kb
Host smart-69e12faa-8f4e-4b23-861b-c7341bd686ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369198018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.2369198018
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.61719172
Short name T847
Test name
Test status
Simulation time 140627663 ps
CPU time 3.76 seconds
Started Aug 04 05:24:29 PM PDT 24
Finished Aug 04 05:24:33 PM PDT 24
Peak memory 248332 kb
Host smart-755f7643-db9a-439a-9842-0900e0db2f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61719172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.61719172
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.2792933684
Short name T1022
Test name
Test status
Simulation time 287307216 ps
CPU time 8.03 seconds
Started Aug 04 05:24:27 PM PDT 24
Finished Aug 04 05:24:35 PM PDT 24
Peak memory 242288 kb
Host smart-c5b7857a-fe03-4113-b555-fbd809876d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792933684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.2792933684
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.1641399441
Short name T681
Test name
Test status
Simulation time 7333163733 ps
CPU time 27.24 seconds
Started Aug 04 05:24:25 PM PDT 24
Finished Aug 04 05:24:53 PM PDT 24
Peak memory 241812 kb
Host smart-3c674997-e689-4067-8cd8-33d3c12cd199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641399441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1641399441
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.2404149729
Short name T1168
Test name
Test status
Simulation time 117825319 ps
CPU time 3.58 seconds
Started Aug 04 05:24:24 PM PDT 24
Finished Aug 04 05:24:27 PM PDT 24
Peak memory 242300 kb
Host smart-02597698-2487-4096-83ca-39c2b81b6f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404149729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2404149729
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.3486003396
Short name T191
Test name
Test status
Simulation time 165511067 ps
CPU time 4.08 seconds
Started Aug 04 05:24:25 PM PDT 24
Finished Aug 04 05:24:29 PM PDT 24
Peak memory 242392 kb
Host smart-2d9f2a0f-05ff-46f6-8b80-59c527d7ec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486003396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3486003396
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.2007015249
Short name T887
Test name
Test status
Simulation time 616298362 ps
CPU time 6.7 seconds
Started Aug 04 05:24:28 PM PDT 24
Finished Aug 04 05:24:35 PM PDT 24
Peak memory 242104 kb
Host smart-8085ba77-214d-4128-8730-e9d7aeed3a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007015249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.2007015249
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.1352430386
Short name T875
Test name
Test status
Simulation time 675706539 ps
CPU time 13.88 seconds
Started Aug 04 05:24:25 PM PDT 24
Finished Aug 04 05:24:39 PM PDT 24
Peak memory 241776 kb
Host smart-2c4b1301-d3a5-4f95-9114-61d9769327b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352430386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1352430386
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.3818786495
Short name T1014
Test name
Test status
Simulation time 2621634783 ps
CPU time 23.11 seconds
Started Aug 04 05:24:27 PM PDT 24
Finished Aug 04 05:24:51 PM PDT 24
Peak memory 242228 kb
Host smart-68cc84c5-cab2-4860-a751-30da820212d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3818786495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3818786495
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.883037875
Short name T19
Test name
Test status
Simulation time 22080653737 ps
CPU time 207.16 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:27:57 PM PDT 24
Peak memory 273524 kb
Host smart-53fe5c58-bf09-446e-9bd2-a0cd24875c95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883037875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.883037875
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.3064665778
Short name T465
Test name
Test status
Simulation time 774512547 ps
CPU time 5.05 seconds
Started Aug 04 05:24:29 PM PDT 24
Finished Aug 04 05:24:34 PM PDT 24
Peak memory 242256 kb
Host smart-c1049124-5ba8-4660-83bc-890984d7f86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064665778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3064665778
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.1455385389
Short name T295
Test name
Test status
Simulation time 200756040933 ps
CPU time 810.75 seconds
Started Aug 04 05:24:28 PM PDT 24
Finished Aug 04 05:37:59 PM PDT 24
Peak memory 387496 kb
Host smart-8a631df5-03e4-4642-a7c5-1406a27ca295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455385389 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.1455385389
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.1161601744
Short name T350
Test name
Test status
Simulation time 2091467070 ps
CPU time 22.34 seconds
Started Aug 04 05:24:29 PM PDT 24
Finished Aug 04 05:24:52 PM PDT 24
Peak memory 241992 kb
Host smart-363d5dd8-6754-4169-855e-d33c934a4a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161601744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.1161601744
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.2598257107
Short name T726
Test name
Test status
Simulation time 11119532505 ps
CPU time 27.29 seconds
Started Aug 04 05:24:54 PM PDT 24
Finished Aug 04 05:25:21 PM PDT 24
Peak memory 244556 kb
Host smart-7ca4bfc3-cc6d-4b7d-9338-79364b3a9d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598257107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.2598257107
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.4158937598
Short name T467
Test name
Test status
Simulation time 244917401 ps
CPU time 15.82 seconds
Started Aug 04 05:24:54 PM PDT 24
Finished Aug 04 05:25:10 PM PDT 24
Peak memory 241920 kb
Host smart-50931f3f-962a-46f3-8afb-8e9ce1363f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158937598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.4158937598
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.2136784163
Short name T382
Test name
Test status
Simulation time 1100273866 ps
CPU time 7.93 seconds
Started Aug 04 05:24:59 PM PDT 24
Finished Aug 04 05:25:07 PM PDT 24
Peak memory 242420 kb
Host smart-d4b81557-0066-4a69-8ad1-d77aa32ed10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136784163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2136784163
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.979667723
Short name T544
Test name
Test status
Simulation time 260145143 ps
CPU time 3.1 seconds
Started Aug 04 05:24:55 PM PDT 24
Finished Aug 04 05:24:58 PM PDT 24
Peak memory 241928 kb
Host smart-b73db099-6b1d-4681-99e6-42c2e3c78783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979667723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.979667723
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.458911929
Short name T825
Test name
Test status
Simulation time 1988624408 ps
CPU time 14.56 seconds
Started Aug 04 05:24:53 PM PDT 24
Finished Aug 04 05:25:07 PM PDT 24
Peak memory 242352 kb
Host smart-e716966e-22ab-42d5-b315-56dd06be2b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458911929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.458911929
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.4270609228
Short name T92
Test name
Test status
Simulation time 1064416953 ps
CPU time 19.29 seconds
Started Aug 04 05:24:53 PM PDT 24
Finished Aug 04 05:25:13 PM PDT 24
Peak memory 241900 kb
Host smart-de27d439-42db-4ee7-88f2-556418245edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270609228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.4270609228
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.2785498654
Short name T962
Test name
Test status
Simulation time 733140604 ps
CPU time 10.53 seconds
Started Aug 04 05:24:55 PM PDT 24
Finished Aug 04 05:25:06 PM PDT 24
Peak memory 241872 kb
Host smart-c7874150-b9db-4b2c-9048-deed6dd8d8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785498654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.2785498654
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.3241231408
Short name T478
Test name
Test status
Simulation time 348863670 ps
CPU time 10.62 seconds
Started Aug 04 05:24:54 PM PDT 24
Finished Aug 04 05:25:05 PM PDT 24
Peak memory 242408 kb
Host smart-8374fb62-0cb8-4d2a-ad55-c565e5c889f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241231408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3241231408
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.4011809380
Short name T498
Test name
Test status
Simulation time 296208373 ps
CPU time 9.31 seconds
Started Aug 04 05:24:55 PM PDT 24
Finished Aug 04 05:25:05 PM PDT 24
Peak memory 241848 kb
Host smart-47babae6-f4b6-4d07-9822-c4868ac127d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4011809380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.4011809380
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.1900339273
Short name T654
Test name
Test status
Simulation time 261502722 ps
CPU time 4.86 seconds
Started Aug 04 05:24:58 PM PDT 24
Finished Aug 04 05:25:03 PM PDT 24
Peak memory 241812 kb
Host smart-58029996-2cb3-4526-a223-42cb43d2404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900339273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1900339273
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.1164711815
Short name T1098
Test name
Test status
Simulation time 59821789928 ps
CPU time 303.48 seconds
Started Aug 04 05:24:53 PM PDT 24
Finished Aug 04 05:29:57 PM PDT 24
Peak memory 280764 kb
Host smart-240c42c1-3770-4cdd-b026-b42beff9275e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164711815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.1164711815
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.3876955976
Short name T1054
Test name
Test status
Simulation time 21175753984 ps
CPU time 404.76 seconds
Started Aug 04 05:24:54 PM PDT 24
Finished Aug 04 05:31:39 PM PDT 24
Peak memory 257920 kb
Host smart-4f789b2c-948f-4b37-8da3-191168ecc437
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876955976 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.3876955976
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.2756287260
Short name T393
Test name
Test status
Simulation time 516396543 ps
CPU time 11.99 seconds
Started Aug 04 05:24:53 PM PDT 24
Finished Aug 04 05:25:05 PM PDT 24
Peak memory 242520 kb
Host smart-eb7aed87-6f8d-4e9a-a7be-1f15100e95e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756287260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.2756287260
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.218241125
Short name T586
Test name
Test status
Simulation time 324827679 ps
CPU time 3.48 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 242056 kb
Host smart-48310dec-630f-4655-b3a5-360562f87f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218241125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.218241125
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.2846594893
Short name T1073
Test name
Test status
Simulation time 1347064151 ps
CPU time 16.31 seconds
Started Aug 04 05:26:47 PM PDT 24
Finished Aug 04 05:27:03 PM PDT 24
Peak memory 242424 kb
Host smart-dd929e6c-d7a8-4cb2-a6b0-f14991d979a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846594893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2846594893
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.3405558729
Short name T446
Test name
Test status
Simulation time 114173885 ps
CPU time 4.07 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 242008 kb
Host smart-0dbb703f-c618-436e-bd75-ba12bbe45ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405558729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3405558729
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.1804775757
Short name T440
Test name
Test status
Simulation time 459890190 ps
CPU time 11.63 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:26:58 PM PDT 24
Peak memory 242440 kb
Host smart-f5594fa4-b424-4948-bd9f-54f011b48ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804775757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1804775757
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.2285170933
Short name T384
Test name
Test status
Simulation time 210788995 ps
CPU time 4.79 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:26:51 PM PDT 24
Peak memory 242024 kb
Host smart-fdfd0c7a-b514-409b-a7f1-94f9b49abb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285170933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.2285170933
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.3126755516
Short name T377
Test name
Test status
Simulation time 1690739268 ps
CPU time 6.53 seconds
Started Aug 04 05:26:49 PM PDT 24
Finished Aug 04 05:26:56 PM PDT 24
Peak memory 242424 kb
Host smart-184bffec-2f0d-4e82-8cd1-bc988845c666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126755516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.3126755516
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.996074498
Short name T75
Test name
Test status
Simulation time 3042141805 ps
CPU time 8.71 seconds
Started Aug 04 05:26:52 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 241944 kb
Host smart-87deb2ac-063d-40c4-ad26-a39e081e830f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996074498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.996074498
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1237106933
Short name T383
Test name
Test status
Simulation time 83412265 ps
CPU time 3.12 seconds
Started Aug 04 05:26:49 PM PDT 24
Finished Aug 04 05:26:52 PM PDT 24
Peak memory 241752 kb
Host smart-716a0556-01c2-4a88-9cdf-b39afade3e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237106933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1237106933
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.2631713763
Short name T475
Test name
Test status
Simulation time 327124203 ps
CPU time 3.71 seconds
Started Aug 04 05:26:53 PM PDT 24
Finished Aug 04 05:26:57 PM PDT 24
Peak memory 242392 kb
Host smart-a23751b6-00ff-4735-8216-b310dcfffa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631713763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.2631713763
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.88997452
Short name T143
Test name
Test status
Simulation time 4175496786 ps
CPU time 9.69 seconds
Started Aug 04 05:26:51 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 242300 kb
Host smart-51663bf7-1256-476f-84bc-e854a78a6baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88997452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.88997452
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.717270173
Short name T459
Test name
Test status
Simulation time 118045329 ps
CPU time 3.64 seconds
Started Aug 04 05:26:48 PM PDT 24
Finished Aug 04 05:26:52 PM PDT 24
Peak memory 242228 kb
Host smart-82017345-d941-462a-98ee-262ef81232aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717270173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.717270173
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3307547950
Short name T439
Test name
Test status
Simulation time 148081162 ps
CPU time 3.5 seconds
Started Aug 04 05:26:50 PM PDT 24
Finished Aug 04 05:26:54 PM PDT 24
Peak memory 241820 kb
Host smart-0211bfb2-d5d8-4651-8dbc-bb3356d0e197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307547950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3307547950
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.2582995733
Short name T885
Test name
Test status
Simulation time 624425617 ps
CPU time 4.92 seconds
Started Aug 04 05:26:50 PM PDT 24
Finished Aug 04 05:26:55 PM PDT 24
Peak memory 242160 kb
Host smart-433ed3d9-8191-4f4a-9595-966af7edf07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582995733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.2582995733
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.3991154568
Short name T484
Test name
Test status
Simulation time 430330684 ps
CPU time 12.73 seconds
Started Aug 04 05:26:49 PM PDT 24
Finished Aug 04 05:27:02 PM PDT 24
Peak memory 241936 kb
Host smart-c1d79300-0a60-4096-839a-e69826aee5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991154568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3991154568
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.2389062069
Short name T659
Test name
Test status
Simulation time 320775059 ps
CPU time 4.77 seconds
Started Aug 04 05:26:52 PM PDT 24
Finished Aug 04 05:26:57 PM PDT 24
Peak memory 242096 kb
Host smart-46a99a0d-1397-4ef2-8fae-ad222851ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389062069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2389062069
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.3517480726
Short name T213
Test name
Test status
Simulation time 429171913 ps
CPU time 6.41 seconds
Started Aug 04 05:26:48 PM PDT 24
Finished Aug 04 05:26:54 PM PDT 24
Peak memory 241760 kb
Host smart-3848086b-32db-40b6-8676-db4cc0cf4099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517480726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3517480726
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3650758869
Short name T228
Test name
Test status
Simulation time 352982937 ps
CPU time 7.2 seconds
Started Aug 04 05:26:49 PM PDT 24
Finished Aug 04 05:26:57 PM PDT 24
Peak memory 242328 kb
Host smart-c1628ceb-9b59-436a-a158-19506f67c23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650758869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3650758869
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.1861578299
Short name T1165
Test name
Test status
Simulation time 136790560 ps
CPU time 5.05 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:02 PM PDT 24
Peak memory 241820 kb
Host smart-30be1895-05d7-407e-92fb-6e620a8674e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861578299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.1861578299
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.513576324
Short name T771
Test name
Test status
Simulation time 333544241 ps
CPU time 17.41 seconds
Started Aug 04 05:26:51 PM PDT 24
Finished Aug 04 05:27:09 PM PDT 24
Peak memory 241852 kb
Host smart-4a3502a1-0aa9-4931-b86b-1a0b5e48b0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513576324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.513576324
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.3935835586
Short name T644
Test name
Test status
Simulation time 596530284 ps
CPU time 1.51 seconds
Started Aug 04 05:24:59 PM PDT 24
Finished Aug 04 05:25:01 PM PDT 24
Peak memory 240864 kb
Host smart-fa4d39e7-1074-4afb-85ab-9bab8dda794c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935835586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.3935835586
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.3651257039
Short name T892
Test name
Test status
Simulation time 336169157 ps
CPU time 8.98 seconds
Started Aug 04 05:24:59 PM PDT 24
Finished Aug 04 05:25:08 PM PDT 24
Peak memory 248652 kb
Host smart-fc873ad2-39c0-4e65-9c2f-2fa0231fe4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651257039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3651257039
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.331465587
Short name T998
Test name
Test status
Simulation time 535856183 ps
CPU time 15.93 seconds
Started Aug 04 05:24:59 PM PDT 24
Finished Aug 04 05:25:15 PM PDT 24
Peak memory 242144 kb
Host smart-dc1c6a2b-6f18-484b-b708-e01505a3479d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331465587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.331465587
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.1392488603
Short name T988
Test name
Test status
Simulation time 257840132 ps
CPU time 7.24 seconds
Started Aug 04 05:25:03 PM PDT 24
Finished Aug 04 05:25:10 PM PDT 24
Peak memory 242064 kb
Host smart-910c0723-2b75-4365-a4b4-0289a949160e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392488603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1392488603
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.429150225
Short name T148
Test name
Test status
Simulation time 12395383601 ps
CPU time 77.6 seconds
Started Aug 04 05:25:01 PM PDT 24
Finished Aug 04 05:26:18 PM PDT 24
Peak memory 243892 kb
Host smart-ead94442-92a1-47bd-9209-b99a69ab53cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429150225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.429150225
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.1081136602
Short name T374
Test name
Test status
Simulation time 1047609665 ps
CPU time 11.88 seconds
Started Aug 04 05:25:00 PM PDT 24
Finished Aug 04 05:25:12 PM PDT 24
Peak memory 242200 kb
Host smart-9f1b2d1e-2065-4f2f-8a10-8fd87a4f993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081136602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.1081136602
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.3355455120
Short name T572
Test name
Test status
Simulation time 511044765 ps
CPU time 8.12 seconds
Started Aug 04 05:24:53 PM PDT 24
Finished Aug 04 05:25:02 PM PDT 24
Peak memory 241796 kb
Host smart-9420f523-6714-4d40-a46e-d67902533d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355455120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.3355455120
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.3179954472
Short name T784
Test name
Test status
Simulation time 2639359438 ps
CPU time 22.71 seconds
Started Aug 04 05:24:52 PM PDT 24
Finished Aug 04 05:25:15 PM PDT 24
Peak memory 242476 kb
Host smart-1a97cf75-1fa1-4c99-87fa-c476a7a3dd2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179954472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3179954472
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.2066983091
Short name T1043
Test name
Test status
Simulation time 3397911430 ps
CPU time 9.62 seconds
Started Aug 04 05:25:00 PM PDT 24
Finished Aug 04 05:25:10 PM PDT 24
Peak memory 242348 kb
Host smart-b34a505e-933e-4773-a21f-3662fdacaa8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066983091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2066983091
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.17366085
Short name T388
Test name
Test status
Simulation time 493183704 ps
CPU time 3.88 seconds
Started Aug 04 05:24:59 PM PDT 24
Finished Aug 04 05:25:03 PM PDT 24
Peak memory 241940 kb
Host smart-e0239732-4a4b-46b1-b5c6-c629ee558f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17366085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.17366085
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.2302374521
Short name T1129
Test name
Test status
Simulation time 1827736592 ps
CPU time 33.02 seconds
Started Aug 04 05:25:00 PM PDT 24
Finished Aug 04 05:25:33 PM PDT 24
Peak memory 242008 kb
Host smart-e6835c8b-1b5c-4fbd-9dbb-1c8a4410325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302374521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2302374521
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.1298403968
Short name T397
Test name
Test status
Simulation time 3899127258 ps
CPU time 25.96 seconds
Started Aug 04 05:26:50 PM PDT 24
Finished Aug 04 05:27:16 PM PDT 24
Peak memory 242304 kb
Host smart-e60fa073-cf38-43b1-8e6c-dbb18b0f3d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298403968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1298403968
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.1029238519
Short name T64
Test name
Test status
Simulation time 391388018 ps
CPU time 3.31 seconds
Started Aug 04 05:26:49 PM PDT 24
Finished Aug 04 05:26:53 PM PDT 24
Peak memory 242084 kb
Host smart-02f61c0e-e2b6-4b1e-b50e-6eaee20e13bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029238519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.1029238519
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.1385686117
Short name T936
Test name
Test status
Simulation time 555925683 ps
CPU time 11.98 seconds
Started Aug 04 05:26:49 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 242372 kb
Host smart-31ee6492-e6ad-4f07-ad54-6e062374095f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385686117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1385686117
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.1416091632
Short name T126
Test name
Test status
Simulation time 260926776 ps
CPU time 3.62 seconds
Started Aug 04 05:26:51 PM PDT 24
Finished Aug 04 05:26:54 PM PDT 24
Peak memory 242080 kb
Host smart-9518cc05-e02b-4d62-951f-02eedf75f0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416091632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.1416091632
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3014663378
Short name T499
Test name
Test status
Simulation time 804937679 ps
CPU time 11.5 seconds
Started Aug 04 05:26:53 PM PDT 24
Finished Aug 04 05:27:05 PM PDT 24
Peak memory 241860 kb
Host smart-33a3c416-7dc0-4b33-b8a7-69a6bf307053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014663378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3014663378
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3046107175
Short name T39
Test name
Test status
Simulation time 148688374 ps
CPU time 4.94 seconds
Started Aug 04 05:26:51 PM PDT 24
Finished Aug 04 05:26:56 PM PDT 24
Peak memory 242312 kb
Host smart-fa624687-e713-47d1-af04-5f91df963516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046107175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3046107175
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.4017981553
Short name T481
Test name
Test status
Simulation time 960987630 ps
CPU time 12.54 seconds
Started Aug 04 05:26:50 PM PDT 24
Finished Aug 04 05:27:02 PM PDT 24
Peak memory 241932 kb
Host smart-3635a1ee-ef30-49c4-8647-9efb20ae1404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017981553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.4017981553
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.1702922129
Short name T584
Test name
Test status
Simulation time 616440319 ps
CPU time 8.7 seconds
Started Aug 04 05:26:53 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 242228 kb
Host smart-07488611-d32a-45f4-a83d-6a5b346672db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702922129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.1702922129
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.691607453
Short name T767
Test name
Test status
Simulation time 245284402 ps
CPU time 5.11 seconds
Started Aug 04 05:26:51 PM PDT 24
Finished Aug 04 05:26:56 PM PDT 24
Peak memory 242284 kb
Host smart-161ccf78-e8df-4585-9cd6-c7e01ad6b058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691607453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.691607453
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.3562713221
Short name T1018
Test name
Test status
Simulation time 817196009 ps
CPU time 12.08 seconds
Started Aug 04 05:26:53 PM PDT 24
Finished Aug 04 05:27:06 PM PDT 24
Peak memory 242372 kb
Host smart-e6cddcf6-7152-4859-983d-f5ffbb59035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562713221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3562713221
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.755167337
Short name T172
Test name
Test status
Simulation time 2214557882 ps
CPU time 6.48 seconds
Started Aug 04 05:26:53 PM PDT 24
Finished Aug 04 05:26:59 PM PDT 24
Peak memory 241820 kb
Host smart-3a5d6c44-8697-4208-a888-32ff53c020bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755167337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.755167337
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.306059619
Short name T108
Test name
Test status
Simulation time 715761856 ps
CPU time 10.19 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:27:04 PM PDT 24
Peak memory 242236 kb
Host smart-bfcc3b84-66e3-4704-84b5-3fc5abd023be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306059619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.306059619
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.1157541508
Short name T540
Test name
Test status
Simulation time 233129546 ps
CPU time 4.69 seconds
Started Aug 04 05:27:02 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 242112 kb
Host smart-ec2594e4-2496-4d11-bf85-7b452433250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157541508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1157541508
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.2621024162
Short name T505
Test name
Test status
Simulation time 265815410 ps
CPU time 7.93 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:27:02 PM PDT 24
Peak memory 242288 kb
Host smart-15ca9d8a-d523-469a-b79c-4a5116972196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621024162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2621024162
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.2336961826
Short name T861
Test name
Test status
Simulation time 628545224 ps
CPU time 4.44 seconds
Started Aug 04 05:26:53 PM PDT 24
Finished Aug 04 05:26:58 PM PDT 24
Peak memory 242436 kb
Host smart-f1df7f50-4d2d-4cf6-9942-85b00f5f49b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336961826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.2336961826
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.3156417082
Short name T1110
Test name
Test status
Simulation time 227559026 ps
CPU time 3.9 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:26:58 PM PDT 24
Peak memory 242128 kb
Host smart-4c98bece-f0e5-4dd9-9693-9d35c5ab7c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156417082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3156417082
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.2366627061
Short name T583
Test name
Test status
Simulation time 640335667 ps
CPU time 16.97 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:27:11 PM PDT 24
Peak memory 241864 kb
Host smart-05d109cc-f3a6-4553-be26-4740f738f5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366627061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2366627061
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.2001250812
Short name T651
Test name
Test status
Simulation time 93475746 ps
CPU time 1.87 seconds
Started Aug 04 05:25:03 PM PDT 24
Finished Aug 04 05:25:05 PM PDT 24
Peak memory 240596 kb
Host smart-079aa2ba-9200-4514-8680-77f1a82a8b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001250812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.2001250812
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.2319933790
Short name T848
Test name
Test status
Simulation time 945052455 ps
CPU time 7.86 seconds
Started Aug 04 05:25:03 PM PDT 24
Finished Aug 04 05:25:11 PM PDT 24
Peak memory 241840 kb
Host smart-28a417d4-d271-4753-ace1-bf2fe47323db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319933790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.2319933790
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.2185807523
Short name T409
Test name
Test status
Simulation time 1144345311 ps
CPU time 28.92 seconds
Started Aug 04 05:25:02 PM PDT 24
Finished Aug 04 05:25:31 PM PDT 24
Peak memory 241988 kb
Host smart-a833f1b3-4a5f-48b2-9ad1-5ce8ac869f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185807523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2185807523
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.2485379514
Short name T1144
Test name
Test status
Simulation time 1445454351 ps
CPU time 10.89 seconds
Started Aug 04 05:24:58 PM PDT 24
Finished Aug 04 05:25:09 PM PDT 24
Peak memory 241884 kb
Host smart-5e459444-dbe9-46a5-b229-c649251ee3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485379514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2485379514
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.2991610899
Short name T717
Test name
Test status
Simulation time 126197531 ps
CPU time 3.97 seconds
Started Aug 04 05:24:57 PM PDT 24
Finished Aug 04 05:25:01 PM PDT 24
Peak memory 242116 kb
Host smart-a0eeee59-0589-4f5a-a206-85671613f97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991610899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.2991610899
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.2965190952
Short name T598
Test name
Test status
Simulation time 235360080 ps
CPU time 6.09 seconds
Started Aug 04 05:25:03 PM PDT 24
Finished Aug 04 05:25:09 PM PDT 24
Peak memory 242368 kb
Host smart-266c79e5-47be-4c63-bd65-3b668e3c9021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965190952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2965190952
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.2048004960
Short name T520
Test name
Test status
Simulation time 302153504 ps
CPU time 6.96 seconds
Started Aug 04 05:25:01 PM PDT 24
Finished Aug 04 05:25:08 PM PDT 24
Peak memory 242160 kb
Host smart-ca6c71e7-5ca5-4a0f-912f-6b4c27ff2bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048004960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.2048004960
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.1534091289
Short name T141
Test name
Test status
Simulation time 128778063 ps
CPU time 4.29 seconds
Started Aug 04 05:24:59 PM PDT 24
Finished Aug 04 05:25:04 PM PDT 24
Peak memory 241848 kb
Host smart-8cf86122-ee29-4fbf-bb0e-e69474df2e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534091289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1534091289
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.87772417
Short name T627
Test name
Test status
Simulation time 3192731922 ps
CPU time 16.79 seconds
Started Aug 04 05:24:59 PM PDT 24
Finished Aug 04 05:25:16 PM PDT 24
Peak memory 241936 kb
Host smart-dcde171e-4b90-4800-9615-b8b850c97454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87772417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.87772417
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.661667478
Short name T910
Test name
Test status
Simulation time 2969978348 ps
CPU time 6.3 seconds
Started Aug 04 05:25:03 PM PDT 24
Finished Aug 04 05:25:09 PM PDT 24
Peak memory 242204 kb
Host smart-d21e6eda-6c24-4a54-9e3c-ffee3d8ea89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661667478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.661667478
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.2000321708
Short name T136
Test name
Test status
Simulation time 3371869771 ps
CPU time 57.66 seconds
Started Aug 04 05:25:05 PM PDT 24
Finished Aug 04 05:26:03 PM PDT 24
Peak memory 246868 kb
Host smart-bb25ea37-bdd5-43b8-a49b-12099847d835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000321708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.2000321708
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1080751497
Short name T575
Test name
Test status
Simulation time 58705737381 ps
CPU time 1725.32 seconds
Started Aug 04 05:25:03 PM PDT 24
Finished Aug 04 05:53:48 PM PDT 24
Peak memory 357700 kb
Host smart-e89abaab-fc14-43bc-b5c4-6ee43f096867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080751497 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.1080751497
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1799430128
Short name T804
Test name
Test status
Simulation time 4427920000 ps
CPU time 26.69 seconds
Started Aug 04 05:25:03 PM PDT 24
Finished Aug 04 05:25:30 PM PDT 24
Peak memory 242736 kb
Host smart-887e795e-5602-4e87-aa00-7531f82c04cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799430128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1799430128
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.4258983403
Short name T537
Test name
Test status
Simulation time 1359719278 ps
CPU time 17.09 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:27:11 PM PDT 24
Peak memory 241888 kb
Host smart-0a2a2d3a-62c1-4bce-8f29-2a654a5cfa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258983403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.4258983403
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.524911923
Short name T127
Test name
Test status
Simulation time 246841625 ps
CPU time 4.79 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:26:59 PM PDT 24
Peak memory 242060 kb
Host smart-8ef706a1-7673-4994-8c3b-716e82889eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524911923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.524911923
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.627338059
Short name T984
Test name
Test status
Simulation time 231711386 ps
CPU time 6 seconds
Started Aug 04 05:26:55 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 241984 kb
Host smart-fba7a321-ab5b-4bb6-a1d6-44c9d324ecf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627338059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.627338059
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.2354659342
Short name T473
Test name
Test status
Simulation time 162398662 ps
CPU time 4.8 seconds
Started Aug 04 05:26:53 PM PDT 24
Finished Aug 04 05:26:58 PM PDT 24
Peak memory 241892 kb
Host smart-7704632a-bcfb-4f4f-9d41-80f459a33bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354659342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.2354659342
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.26524455
Short name T896
Test name
Test status
Simulation time 2307864105 ps
CPU time 9.01 seconds
Started Aug 04 05:26:55 PM PDT 24
Finished Aug 04 05:27:04 PM PDT 24
Peak memory 241848 kb
Host smart-f7d1af56-f543-46e0-80b8-2c3d36098512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26524455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.26524455
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.1664615634
Short name T909
Test name
Test status
Simulation time 394900547 ps
CPU time 4.92 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:26:59 PM PDT 24
Peak memory 242228 kb
Host smart-7ea810ff-bf0a-4f79-8406-58a968e962e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664615634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.1664615634
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.1243185156
Short name T948
Test name
Test status
Simulation time 116027515 ps
CPU time 3.76 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 241740 kb
Host smart-f5db726d-c8be-4edd-8263-fadb7511eb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243185156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1243185156
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.1178676343
Short name T574
Test name
Test status
Simulation time 300699509 ps
CPU time 6.86 seconds
Started Aug 04 05:26:53 PM PDT 24
Finished Aug 04 05:27:00 PM PDT 24
Peak memory 241784 kb
Host smart-f3a09dbe-6a99-4917-aacf-422718d962ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178676343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1178676343
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.1736526187
Short name T176
Test name
Test status
Simulation time 525606908 ps
CPU time 4.18 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:02 PM PDT 24
Peak memory 241824 kb
Host smart-288fe220-adfc-4351-bda5-58647061a8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736526187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1736526187
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.1421320364
Short name T405
Test name
Test status
Simulation time 657507693 ps
CPU time 19.39 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:27:14 PM PDT 24
Peak memory 242288 kb
Host smart-40368074-a9a4-4e99-a2e9-dca90d7e7753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421320364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1421320364
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.710365293
Short name T406
Test name
Test status
Simulation time 1963481000 ps
CPU time 5.62 seconds
Started Aug 04 05:27:02 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 242528 kb
Host smart-9af96620-3ea0-446c-ac13-d533c5859450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710365293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.710365293
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.296559261
Short name T435
Test name
Test status
Simulation time 574635974 ps
CPU time 3.71 seconds
Started Aug 04 05:27:00 PM PDT 24
Finished Aug 04 05:27:04 PM PDT 24
Peak memory 242516 kb
Host smart-0a32727e-201d-44b5-85c5-9b8ccff6afe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296559261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.296559261
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.272826387
Short name T817
Test name
Test status
Simulation time 423611988 ps
CPU time 4.9 seconds
Started Aug 04 05:27:01 PM PDT 24
Finished Aug 04 05:27:06 PM PDT 24
Peak memory 242608 kb
Host smart-377a4ff8-34d0-4999-9d88-5a50e4e368d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272826387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.272826387
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.3809072212
Short name T1057
Test name
Test status
Simulation time 1614370413 ps
CPU time 23.69 seconds
Started Aug 04 05:27:02 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 242376 kb
Host smart-f30ef36b-0bb6-42d9-ba0c-99c7f6f2837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809072212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3809072212
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.2070202844
Short name T167
Test name
Test status
Simulation time 1936844613 ps
CPU time 4.06 seconds
Started Aug 04 05:26:55 PM PDT 24
Finished Aug 04 05:26:59 PM PDT 24
Peak memory 242284 kb
Host smart-12245dab-46f3-49fb-9e0d-b8ce5e8d60ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070202844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2070202844
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.1552200434
Short name T1141
Test name
Test status
Simulation time 1248050918 ps
CPU time 10.68 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:08 PM PDT 24
Peak memory 242208 kb
Host smart-432591ef-339a-456c-a9ac-91de6942ab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552200434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.1552200434
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.1521474667
Short name T411
Test name
Test status
Simulation time 2251705698 ps
CPU time 6.83 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:04 PM PDT 24
Peak memory 241848 kb
Host smart-f38e188e-82b4-4399-82eb-6d1be88c55a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521474667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1521474667
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.3830476037
Short name T211
Test name
Test status
Simulation time 673775256 ps
CPU time 13.07 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 242416 kb
Host smart-9e867e06-00bb-4dcc-a7cc-4d631e823946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830476037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.3830476037
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.1036987669
Short name T1075
Test name
Test status
Simulation time 82625871 ps
CPU time 1.94 seconds
Started Aug 04 05:25:05 PM PDT 24
Finished Aug 04 05:25:07 PM PDT 24
Peak memory 240476 kb
Host smart-08589fee-029f-46a1-a39b-80e58c6156fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036987669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1036987669
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.1033132989
Short name T112
Test name
Test status
Simulation time 19655653602 ps
CPU time 48.53 seconds
Started Aug 04 05:25:06 PM PDT 24
Finished Aug 04 05:25:55 PM PDT 24
Peak memory 246032 kb
Host smart-24589c85-24de-4298-a711-faf3d281f1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033132989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.1033132989
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.2614075699
Short name T653
Test name
Test status
Simulation time 726206681 ps
CPU time 24.48 seconds
Started Aug 04 05:25:01 PM PDT 24
Finished Aug 04 05:25:25 PM PDT 24
Peak memory 242240 kb
Host smart-9e005385-9652-4630-a524-5b9ceb43f89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614075699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.2614075699
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.1189325946
Short name T968
Test name
Test status
Simulation time 969813423 ps
CPU time 11.06 seconds
Started Aug 04 05:25:00 PM PDT 24
Finished Aug 04 05:25:11 PM PDT 24
Peak memory 242444 kb
Host smart-b75f6c15-0cd9-4b62-84ff-51e2609caf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189325946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.1189325946
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.42593323
Short name T431
Test name
Test status
Simulation time 182897041 ps
CPU time 4.19 seconds
Started Aug 04 05:25:03 PM PDT 24
Finished Aug 04 05:25:08 PM PDT 24
Peak memory 242272 kb
Host smart-299b92b5-f6b0-405e-8066-b64719921c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42593323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.42593323
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.4248601766
Short name T1089
Test name
Test status
Simulation time 411136836 ps
CPU time 9.3 seconds
Started Aug 04 05:25:02 PM PDT 24
Finished Aug 04 05:25:12 PM PDT 24
Peak memory 242084 kb
Host smart-a4756881-9c13-4cbd-b450-68c6d4101970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248601766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.4248601766
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.1112266627
Short name T387
Test name
Test status
Simulation time 4713341875 ps
CPU time 11.33 seconds
Started Aug 04 05:25:14 PM PDT 24
Finished Aug 04 05:25:25 PM PDT 24
Peak memory 242144 kb
Host smart-812e416b-969c-4be8-87a2-2185ce0b7a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112266627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.1112266627
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.3489260671
Short name T786
Test name
Test status
Simulation time 674908908 ps
CPU time 17.79 seconds
Started Aug 04 05:25:02 PM PDT 24
Finished Aug 04 05:25:20 PM PDT 24
Peak memory 241956 kb
Host smart-9e62b34d-e5d7-4084-bed1-51ffc6234234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489260671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.3489260671
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.219328698
Short name T341
Test name
Test status
Simulation time 2443081046 ps
CPU time 16.85 seconds
Started Aug 04 05:25:03 PM PDT 24
Finished Aug 04 05:25:20 PM PDT 24
Peak memory 242028 kb
Host smart-34431c03-d246-4eea-97a7-ef254d84dd7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219328698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.219328698
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.917256100
Short name T1086
Test name
Test status
Simulation time 275138469 ps
CPU time 8.56 seconds
Started Aug 04 05:25:01 PM PDT 24
Finished Aug 04 05:25:09 PM PDT 24
Peak memory 242096 kb
Host smart-87e429fd-3c79-494c-b5ee-a16fa7968c25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917256100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.917256100
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.3742849545
Short name T425
Test name
Test status
Simulation time 742415027 ps
CPU time 7.46 seconds
Started Aug 04 05:25:03 PM PDT 24
Finished Aug 04 05:25:10 PM PDT 24
Peak memory 242100 kb
Host smart-1c2c49f1-53c9-448e-8f2e-36afe77c6e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742849545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.3742849545
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.97125582
Short name T250
Test name
Test status
Simulation time 186901633909 ps
CPU time 2566.28 seconds
Started Aug 04 05:25:06 PM PDT 24
Finished Aug 04 06:07:53 PM PDT 24
Peak memory 522340 kb
Host smart-db350c67-5a6b-4e57-9e0d-85719e456545
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97125582 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.97125582
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.1766441554
Short name T1006
Test name
Test status
Simulation time 5195558978 ps
CPU time 18.81 seconds
Started Aug 04 05:25:02 PM PDT 24
Finished Aug 04 05:25:21 PM PDT 24
Peak memory 242348 kb
Host smart-aa4f7522-5f74-4a21-a56a-24d2ac79f5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766441554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.1766441554
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.3955562186
Short name T278
Test name
Test status
Simulation time 114740764 ps
CPU time 4.01 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 242136 kb
Host smart-9740bfa1-7c58-4379-be71-19d1896191bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955562186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.3955562186
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3842443187
Short name T813
Test name
Test status
Simulation time 1176973206 ps
CPU time 9.51 seconds
Started Aug 04 05:26:54 PM PDT 24
Finished Aug 04 05:27:03 PM PDT 24
Peak memory 241868 kb
Host smart-2c03f5f8-b508-41bf-8a2b-aacaa31d8b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842443187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3842443187
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.3015653872
Short name T877
Test name
Test status
Simulation time 2003400453 ps
CPU time 5.78 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:03 PM PDT 24
Peak memory 242012 kb
Host smart-2b1d55a2-7b2f-4123-8999-1175a8771045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015653872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.3015653872
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.599365116
Short name T503
Test name
Test status
Simulation time 3862903968 ps
CPU time 23.79 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 242180 kb
Host smart-627fc5c7-8859-4ee6-af3d-33e407c8cffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599365116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.599365116
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.1564899205
Short name T821
Test name
Test status
Simulation time 2131683334 ps
CPU time 5.32 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:05 PM PDT 24
Peak memory 242032 kb
Host smart-ae7e9924-e98c-4793-ab7b-9a2b753a5994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564899205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1564899205
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.3028521412
Short name T138
Test name
Test status
Simulation time 396794704 ps
CPU time 8.97 seconds
Started Aug 04 05:27:00 PM PDT 24
Finished Aug 04 05:27:09 PM PDT 24
Peak memory 241840 kb
Host smart-9968f0e1-9f7c-42e0-8e96-ad81e8526299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028521412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.3028521412
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.1678606794
Short name T1024
Test name
Test status
Simulation time 220252898 ps
CPU time 4.32 seconds
Started Aug 04 05:27:02 PM PDT 24
Finished Aug 04 05:27:06 PM PDT 24
Peak memory 242328 kb
Host smart-db3a2ad4-b0f4-4a68-89ea-f1f36133d674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678606794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1678606794
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.1703845457
Short name T254
Test name
Test status
Simulation time 297550366 ps
CPU time 9.26 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:08 PM PDT 24
Peak memory 248428 kb
Host smart-3077c575-40eb-40aa-830e-15a569beb127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703845457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.1703845457
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2906676684
Short name T684
Test name
Test status
Simulation time 956272142 ps
CPU time 13.61 seconds
Started Aug 04 05:27:00 PM PDT 24
Finished Aug 04 05:27:13 PM PDT 24
Peak memory 242436 kb
Host smart-30389c3d-d4ea-4ffb-a360-f5a6415f9f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906676684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2906676684
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.1276068822
Short name T117
Test name
Test status
Simulation time 1628863594 ps
CPU time 5.84 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:05 PM PDT 24
Peak memory 241956 kb
Host smart-33adb30a-d38e-439f-b88a-63f83fa15f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276068822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1276068822
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.3336165322
Short name T609
Test name
Test status
Simulation time 1370396475 ps
CPU time 18.63 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:17 PM PDT 24
Peak memory 242032 kb
Host smart-f1d80ed6-9d49-4880-927d-6d029d6ac1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336165322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3336165322
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.4212075247
Short name T680
Test name
Test status
Simulation time 131275564 ps
CPU time 4.63 seconds
Started Aug 04 05:27:01 PM PDT 24
Finished Aug 04 05:27:05 PM PDT 24
Peak memory 242044 kb
Host smart-29f5396c-db45-4873-830a-3289dea62c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212075247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.4212075247
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.2339080182
Short name T139
Test name
Test status
Simulation time 169854128 ps
CPU time 5.92 seconds
Started Aug 04 05:26:58 PM PDT 24
Finished Aug 04 05:27:04 PM PDT 24
Peak memory 242284 kb
Host smart-9186f112-df02-44b7-bf35-2ac3878be3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339080182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2339080182
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.2122146942
Short name T863
Test name
Test status
Simulation time 290005067 ps
CPU time 3.29 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:00 PM PDT 24
Peak memory 242252 kb
Host smart-5ac822fb-5460-468b-90c7-98574626ea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122146942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.2122146942
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.3598478156
Short name T1123
Test name
Test status
Simulation time 323077656 ps
CPU time 8.64 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:08 PM PDT 24
Peak memory 248228 kb
Host smart-54a16ae8-5735-4fde-a3f9-2766f27c20cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598478156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.3598478156
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.1648448585
Short name T1115
Test name
Test status
Simulation time 397828162 ps
CPU time 3.96 seconds
Started Aug 04 05:27:01 PM PDT 24
Finished Aug 04 05:27:05 PM PDT 24
Peak memory 242216 kb
Host smart-b1236f9f-0896-4332-b525-0cd406cbcf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648448585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.1648448585
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.3895031592
Short name T599
Test name
Test status
Simulation time 2496478071 ps
CPU time 19.72 seconds
Started Aug 04 05:27:00 PM PDT 24
Finished Aug 04 05:27:19 PM PDT 24
Peak memory 242184 kb
Host smart-b5338d0e-ac70-4546-85dc-16c92f2e6286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895031592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.3895031592
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2307294433
Short name T713
Test name
Test status
Simulation time 504475620 ps
CPU time 4.31 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 242264 kb
Host smart-ad6b6235-c50e-491a-a3f6-eff7a6821462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307294433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2307294433
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.3495001194
Short name T1156
Test name
Test status
Simulation time 77954415 ps
CPU time 1.92 seconds
Started Aug 04 05:25:11 PM PDT 24
Finished Aug 04 05:25:13 PM PDT 24
Peak memory 240508 kb
Host smart-4ab1525c-5ccb-424b-b9bb-2cceec9d36c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495001194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.3495001194
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.3846274709
Short name T55
Test name
Test status
Simulation time 3720787749 ps
CPU time 36.6 seconds
Started Aug 04 05:25:05 PM PDT 24
Finished Aug 04 05:25:42 PM PDT 24
Peak memory 242544 kb
Host smart-524e0283-eced-4c23-9422-ac53d7d8414a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846274709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.3846274709
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.598023118
Short name T1062
Test name
Test status
Simulation time 729003094 ps
CPU time 20.65 seconds
Started Aug 04 05:25:06 PM PDT 24
Finished Aug 04 05:25:27 PM PDT 24
Peak memory 241948 kb
Host smart-df95febb-cade-4dff-98d1-326ee5f108ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598023118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.598023118
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.320360406
Short name T903
Test name
Test status
Simulation time 144075408 ps
CPU time 3.55 seconds
Started Aug 04 05:25:04 PM PDT 24
Finished Aug 04 05:25:07 PM PDT 24
Peak memory 241948 kb
Host smart-220c8d02-de97-40db-a440-afca9001357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320360406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.320360406
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.1575990252
Short name T826
Test name
Test status
Simulation time 8047679232 ps
CPU time 51.19 seconds
Started Aug 04 05:25:04 PM PDT 24
Finished Aug 04 05:25:56 PM PDT 24
Peak memory 249100 kb
Host smart-c95af7c3-ca16-4f93-992e-be72db722874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575990252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1575990252
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.468880804
Short name T389
Test name
Test status
Simulation time 7201976890 ps
CPU time 23.39 seconds
Started Aug 04 05:25:06 PM PDT 24
Finished Aug 04 05:25:30 PM PDT 24
Peak memory 242988 kb
Host smart-6e67afcf-80b2-49a9-b9aa-d9f2f930ea68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468880804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.468880804
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.1347116028
Short name T182
Test name
Test status
Simulation time 1399214509 ps
CPU time 4.44 seconds
Started Aug 04 05:25:05 PM PDT 24
Finished Aug 04 05:25:09 PM PDT 24
Peak memory 242044 kb
Host smart-c6cd0e8f-0157-44fe-9996-9a0f6d46f2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347116028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.1347116028
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.1853741575
Short name T761
Test name
Test status
Simulation time 342826859 ps
CPU time 8.85 seconds
Started Aug 04 05:25:06 PM PDT 24
Finished Aug 04 05:25:15 PM PDT 24
Peak memory 241912 kb
Host smart-b36bc1e3-18bc-43ae-910f-6a99c45f40f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853741575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.1853741575
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.1145853907
Short name T864
Test name
Test status
Simulation time 166180006 ps
CPU time 3.58 seconds
Started Aug 04 05:25:06 PM PDT 24
Finished Aug 04 05:25:10 PM PDT 24
Peak memory 242048 kb
Host smart-10412c23-e95b-4a4a-9da6-3c8946ec665b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145853907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1145853907
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.2907170490
Short name T715
Test name
Test status
Simulation time 5195790358 ps
CPU time 96.49 seconds
Started Aug 04 05:25:10 PM PDT 24
Finished Aug 04 05:26:47 PM PDT 24
Peak memory 248368 kb
Host smart-50741884-3542-4ab4-8eb2-4c95a0a34304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907170490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.2907170490
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.2610978915
Short name T639
Test name
Test status
Simulation time 140742955 ps
CPU time 5.44 seconds
Started Aug 04 05:25:06 PM PDT 24
Finished Aug 04 05:25:12 PM PDT 24
Peak memory 242148 kb
Host smart-b1fa4e25-ff27-423f-b5ac-6b835cff525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610978915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2610978915
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.2833569964
Short name T637
Test name
Test status
Simulation time 262953040 ps
CPU time 3.86 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:03 PM PDT 24
Peak memory 242384 kb
Host smart-0b886200-2c38-4064-b568-56b50202f941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833569964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2833569964
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.2102192676
Short name T862
Test name
Test status
Simulation time 238833447 ps
CPU time 5.68 seconds
Started Aug 04 05:27:00 PM PDT 24
Finished Aug 04 05:27:05 PM PDT 24
Peak memory 242132 kb
Host smart-123fff36-57fd-4b2c-97cc-02acb37a9f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102192676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.2102192676
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.2982028581
Short name T466
Test name
Test status
Simulation time 1635399102 ps
CPU time 5.08 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:08 PM PDT 24
Peak memory 242016 kb
Host smart-a39d79e2-74c0-4338-ae67-76e9583da80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982028581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2982028581
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.2288732106
Short name T768
Test name
Test status
Simulation time 1016908688 ps
CPU time 7.03 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:10 PM PDT 24
Peak memory 242404 kb
Host smart-48662d30-f327-4e3f-a5aa-9574d2f4bcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288732106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2288732106
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.3339836033
Short name T679
Test name
Test status
Simulation time 308163008 ps
CPU time 4.17 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 242000 kb
Host smart-18830b15-0c55-4d45-8741-e6c6933df0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339836033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3339836033
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.150959546
Short name T580
Test name
Test status
Simulation time 152796557 ps
CPU time 2.74 seconds
Started Aug 04 05:26:57 PM PDT 24
Finished Aug 04 05:27:00 PM PDT 24
Peak memory 242028 kb
Host smart-1fe40aec-ef26-4b78-9108-473225e1302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150959546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.150959546
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.1302831305
Short name T556
Test name
Test status
Simulation time 394860905 ps
CPU time 5.25 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:04 PM PDT 24
Peak memory 241612 kb
Host smart-d4e7fdca-e3d3-4424-9875-a42e76285607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302831305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.1302831305
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.3647063965
Short name T1074
Test name
Test status
Simulation time 214986734 ps
CPU time 4.14 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 242220 kb
Host smart-6d5b9d40-bd01-4ebd-8727-673e4976c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647063965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.3647063965
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1504202483
Short name T1053
Test name
Test status
Simulation time 2965869419 ps
CPU time 10.73 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:10 PM PDT 24
Peak memory 241840 kb
Host smart-4b1fb8c4-c6d4-4895-9567-854823da78b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504202483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1504202483
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.3408533669
Short name T123
Test name
Test status
Simulation time 188539459 ps
CPU time 4.54 seconds
Started Aug 04 05:26:59 PM PDT 24
Finished Aug 04 05:27:04 PM PDT 24
Peak memory 241512 kb
Host smart-e004656b-9297-498f-a6fb-e54b292f10a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408533669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3408533669
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.1698178371
Short name T1084
Test name
Test status
Simulation time 126327013 ps
CPU time 5.18 seconds
Started Aug 04 05:27:00 PM PDT 24
Finished Aug 04 05:27:05 PM PDT 24
Peak memory 241812 kb
Host smart-2f750fe9-cd04-4444-90f0-694527674e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698178371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.1698178371
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.1770698577
Short name T983
Test name
Test status
Simulation time 288096869 ps
CPU time 5 seconds
Started Aug 04 05:27:00 PM PDT 24
Finished Aug 04 05:27:05 PM PDT 24
Peak memory 241984 kb
Host smart-51e785b7-52e9-45f5-b8a3-033db103c9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770698577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.1770698577
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.3278574852
Short name T486
Test name
Test status
Simulation time 6030960900 ps
CPU time 10.37 seconds
Started Aug 04 05:27:07 PM PDT 24
Finished Aug 04 05:27:18 PM PDT 24
Peak memory 241920 kb
Host smart-a44b6b78-2ba9-4915-be6d-2819d604f5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278574852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.3278574852
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.2673525062
Short name T816
Test name
Test status
Simulation time 250311269 ps
CPU time 4.03 seconds
Started Aug 04 05:27:01 PM PDT 24
Finished Aug 04 05:27:05 PM PDT 24
Peak memory 241912 kb
Host smart-0cb9d398-38a8-4f40-9de8-9fc01c990d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673525062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2673525062
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.2972609997
Short name T733
Test name
Test status
Simulation time 1797445212 ps
CPU time 14.46 seconds
Started Aug 04 05:27:02 PM PDT 24
Finished Aug 04 05:27:17 PM PDT 24
Peak memory 241792 kb
Host smart-15b9f4a7-3a53-4193-a491-afa83c478311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972609997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2972609997
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.3829318168
Short name T794
Test name
Test status
Simulation time 435208767 ps
CPU time 4.14 seconds
Started Aug 04 05:27:02 PM PDT 24
Finished Aug 04 05:27:06 PM PDT 24
Peak memory 241968 kb
Host smart-8cb5b4c5-e3a0-4bbe-9ff9-2336fd929df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829318168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3829318168
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.1317255909
Short name T581
Test name
Test status
Simulation time 178511403 ps
CPU time 7.57 seconds
Started Aug 04 05:27:00 PM PDT 24
Finished Aug 04 05:27:08 PM PDT 24
Peak memory 241908 kb
Host smart-d6120ea5-8929-4a31-aa0c-5cb00a10d4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317255909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1317255909
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.3056475062
Short name T52
Test name
Test status
Simulation time 266552201 ps
CPU time 5.35 seconds
Started Aug 04 05:27:02 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 241960 kb
Host smart-ef0541f3-34de-4d43-a1ab-2c1429e7fa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056475062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3056475062
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.2479441362
Short name T649
Test name
Test status
Simulation time 663803528 ps
CPU time 17.55 seconds
Started Aug 04 05:27:04 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 241952 kb
Host smart-01b74b2e-93c9-45b4-950f-5ac861ded1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479441362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.2479441362
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.2073644156
Short name T671
Test name
Test status
Simulation time 90495948 ps
CPU time 1.76 seconds
Started Aug 04 05:25:13 PM PDT 24
Finished Aug 04 05:25:15 PM PDT 24
Peak memory 240620 kb
Host smart-fb236d8d-0d76-4f01-91da-a733a6de8654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073644156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2073644156
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.1338929338
Short name T36
Test name
Test status
Simulation time 3756680118 ps
CPU time 31.84 seconds
Started Aug 04 05:25:09 PM PDT 24
Finished Aug 04 05:25:41 PM PDT 24
Peak memory 242944 kb
Host smart-211b8f32-18d7-46b6-9181-4575117d5e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338929338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1338929338
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.2787896669
Short name T876
Test name
Test status
Simulation time 421765990 ps
CPU time 11.22 seconds
Started Aug 04 05:25:12 PM PDT 24
Finished Aug 04 05:25:23 PM PDT 24
Peak memory 241800 kb
Host smart-3e36bc50-c4b2-42cc-9602-a34d1a1db637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787896669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2787896669
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.1931789229
Short name T438
Test name
Test status
Simulation time 22466007581 ps
CPU time 59.22 seconds
Started Aug 04 05:25:11 PM PDT 24
Finished Aug 04 05:26:10 PM PDT 24
Peak memory 243412 kb
Host smart-4c74ad25-8e34-47f9-ae3e-06e52138af17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931789229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.1931789229
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.1575404073
Short name T1059
Test name
Test status
Simulation time 118965195 ps
CPU time 3.49 seconds
Started Aug 04 05:25:09 PM PDT 24
Finished Aug 04 05:25:13 PM PDT 24
Peak memory 242096 kb
Host smart-239a29e0-664f-457e-afae-dbda457590be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575404073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1575404073
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.2454210177
Short name T866
Test name
Test status
Simulation time 6135502506 ps
CPU time 44.15 seconds
Started Aug 04 05:25:10 PM PDT 24
Finished Aug 04 05:25:54 PM PDT 24
Peak memory 258916 kb
Host smart-fe7c8009-ca01-4817-b00b-e41a4f7bedb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454210177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.2454210177
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.4180908676
Short name T342
Test name
Test status
Simulation time 9420011435 ps
CPU time 26.33 seconds
Started Aug 04 05:25:11 PM PDT 24
Finished Aug 04 05:25:37 PM PDT 24
Peak memory 242656 kb
Host smart-34f30a04-7749-46f1-a6f7-81337a3a368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180908676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.4180908676
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.1410468746
Short name T908
Test name
Test status
Simulation time 610566614 ps
CPU time 17.78 seconds
Started Aug 04 05:25:11 PM PDT 24
Finished Aug 04 05:25:29 PM PDT 24
Peak memory 241876 kb
Host smart-5beb0f08-44c4-47b8-99e7-82cc6c6c1938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410468746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.1410468746
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.3746212998
Short name T290
Test name
Test status
Simulation time 359568243 ps
CPU time 11.41 seconds
Started Aug 04 05:25:12 PM PDT 24
Finished Aug 04 05:25:23 PM PDT 24
Peak memory 242060 kb
Host smart-c26afd14-5d8d-4e87-8c1c-34ad255bc529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746212998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3746212998
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.1462656869
Short name T727
Test name
Test status
Simulation time 4187971731 ps
CPU time 12.47 seconds
Started Aug 04 05:25:11 PM PDT 24
Finished Aug 04 05:25:23 PM PDT 24
Peak memory 242524 kb
Host smart-9790106a-d1e8-49b6-9e33-e93918f16bf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462656869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.1462656869
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.2708632045
Short name T533
Test name
Test status
Simulation time 297177648 ps
CPU time 8.89 seconds
Started Aug 04 05:25:10 PM PDT 24
Finished Aug 04 05:25:19 PM PDT 24
Peak memory 242252 kb
Host smart-9cfa56b1-125d-4547-9d0b-072d93df984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708632045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2708632045
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.3201449468
Short name T423
Test name
Test status
Simulation time 38040027904 ps
CPU time 74.82 seconds
Started Aug 04 05:25:13 PM PDT 24
Finished Aug 04 05:26:27 PM PDT 24
Peak memory 248492 kb
Host smart-eb29db6b-912c-4341-a17b-eea09825c63b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201449468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.3201449468
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.2093777271
Short name T340
Test name
Test status
Simulation time 13195365772 ps
CPU time 32.98 seconds
Started Aug 04 05:25:13 PM PDT 24
Finished Aug 04 05:25:46 PM PDT 24
Peak memory 242424 kb
Host smart-2fddabe6-e8fb-4726-aecd-046034d5c4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093777271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.2093777271
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.2374968033
Short name T1101
Test name
Test status
Simulation time 456545542 ps
CPU time 3.51 seconds
Started Aug 04 05:27:04 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 242332 kb
Host smart-89217e00-bfc9-4ade-9d21-c7ac3c51b332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374968033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.2374968033
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.2042891885
Short name T633
Test name
Test status
Simulation time 501395476 ps
CPU time 6.31 seconds
Started Aug 04 05:27:02 PM PDT 24
Finished Aug 04 05:27:09 PM PDT 24
Peak memory 242376 kb
Host smart-a1252410-ea77-42e7-90dc-1a69e30aa734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042891885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2042891885
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.4189270961
Short name T975
Test name
Test status
Simulation time 441253880 ps
CPU time 4.98 seconds
Started Aug 04 05:27:05 PM PDT 24
Finished Aug 04 05:27:10 PM PDT 24
Peak memory 241892 kb
Host smart-b8feb417-2a6b-4b98-a9e5-7764df1a00a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189270961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.4189270961
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.455806511
Short name T1114
Test name
Test status
Simulation time 760724206 ps
CPU time 6.29 seconds
Started Aug 04 05:27:05 PM PDT 24
Finished Aug 04 05:27:11 PM PDT 24
Peak memory 247996 kb
Host smart-161e7748-fe48-437a-88af-6b81c7f23a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455806511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.455806511
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.732657259
Short name T1002
Test name
Test status
Simulation time 2383307890 ps
CPU time 6.8 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:10 PM PDT 24
Peak memory 242340 kb
Host smart-353d8976-8acf-49ad-a7cf-4ebbf0136bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732657259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.732657259
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.3845103809
Short name T527
Test name
Test status
Simulation time 1716079018 ps
CPU time 5.95 seconds
Started Aug 04 05:27:05 PM PDT 24
Finished Aug 04 05:27:11 PM PDT 24
Peak memory 242060 kb
Host smart-9d58275b-506f-4f9c-98ac-52870d741d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845103809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.3845103809
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.1574606244
Short name T483
Test name
Test status
Simulation time 296412827 ps
CPU time 8.53 seconds
Started Aug 04 05:27:02 PM PDT 24
Finished Aug 04 05:27:10 PM PDT 24
Peak memory 242040 kb
Host smart-1424e719-4351-48a0-b342-a5d6854d8cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574606244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1574606244
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.4031885939
Short name T1079
Test name
Test status
Simulation time 165437955 ps
CPU time 3.65 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:06 PM PDT 24
Peak memory 241912 kb
Host smart-e07b4150-a5be-4ae1-93b3-29de6b313366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031885939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.4031885939
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.4261473200
Short name T967
Test name
Test status
Simulation time 114000540 ps
CPU time 4.74 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:08 PM PDT 24
Peak memory 241824 kb
Host smart-8274c406-7e75-4fff-8601-34e3da56bced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261473200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.4261473200
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.3495044843
Short name T450
Test name
Test status
Simulation time 213072646 ps
CPU time 3.39 seconds
Started Aug 04 05:27:07 PM PDT 24
Finished Aug 04 05:27:10 PM PDT 24
Peak memory 241960 kb
Host smart-e185759d-f01b-418c-85f5-bcc1b5f53b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495044843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.3495044843
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.2805205842
Short name T711
Test name
Test status
Simulation time 6471723010 ps
CPU time 11.9 seconds
Started Aug 04 05:27:04 PM PDT 24
Finished Aug 04 05:27:16 PM PDT 24
Peak memory 242284 kb
Host smart-6eeed26c-a9fe-4bcd-8a51-f07151f7e759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805205842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.2805205842
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3486689157
Short name T432
Test name
Test status
Simulation time 198082799 ps
CPU time 4.21 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:08 PM PDT 24
Peak memory 242296 kb
Host smart-48cea028-3250-4aca-92d1-c5dee2670bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486689157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3486689157
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.3604639570
Short name T102
Test name
Test status
Simulation time 150913053 ps
CPU time 3.04 seconds
Started Aug 04 05:27:04 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 241916 kb
Host smart-5b863b54-1d6f-48b3-af9f-6f86b4562f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604639570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.3604639570
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.190271341
Short name T675
Test name
Test status
Simulation time 391135344 ps
CPU time 4.25 seconds
Started Aug 04 05:27:02 PM PDT 24
Finished Aug 04 05:27:06 PM PDT 24
Peak memory 242004 kb
Host smart-2a7fbe88-b27f-41ea-8bcc-be6c169f4df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190271341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.190271341
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.745408000
Short name T900
Test name
Test status
Simulation time 136610643 ps
CPU time 6.72 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:10 PM PDT 24
Peak memory 241908 kb
Host smart-104b8d8c-1b48-4bf4-8e30-312e8359301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745408000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.745408000
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.1363346778
Short name T542
Test name
Test status
Simulation time 276052380 ps
CPU time 3.85 seconds
Started Aug 04 05:27:05 PM PDT 24
Finished Aug 04 05:27:09 PM PDT 24
Peak memory 242020 kb
Host smart-cd5088fc-e44a-458c-bec8-8f58d91575c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363346778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.1363346778
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.576871653
Short name T535
Test name
Test status
Simulation time 5364981536 ps
CPU time 11.67 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:15 PM PDT 24
Peak memory 242088 kb
Host smart-9442bf17-0107-4f94-a790-81b2d46e68b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576871653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.576871653
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.2047967127
Short name T1020
Test name
Test status
Simulation time 158394210 ps
CPU time 4.44 seconds
Started Aug 04 05:27:03 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 241936 kb
Host smart-cd38bc69-1f72-4156-b006-53b7430238de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047967127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2047967127
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1019263050
Short name T227
Test name
Test status
Simulation time 579991593 ps
CPU time 7.13 seconds
Started Aug 04 05:27:05 PM PDT 24
Finished Aug 04 05:27:12 PM PDT 24
Peak memory 242356 kb
Host smart-8abea518-0b68-4dce-92ad-1b25c2e627cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019263050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1019263050
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.1971063033
Short name T913
Test name
Test status
Simulation time 90602482 ps
CPU time 1.84 seconds
Started Aug 04 05:25:12 PM PDT 24
Finished Aug 04 05:25:14 PM PDT 24
Peak memory 240616 kb
Host smart-9e17da63-750f-403a-bb2c-ff9efa86fd19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971063033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.1971063033
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.55173649
Short name T258
Test name
Test status
Simulation time 1361515556 ps
CPU time 7.88 seconds
Started Aug 04 05:25:10 PM PDT 24
Finished Aug 04 05:25:18 PM PDT 24
Peak memory 248572 kb
Host smart-b75735c0-5325-4030-be02-e10e560a6efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55173649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.55173649
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.1582567795
Short name T749
Test name
Test status
Simulation time 11893536022 ps
CPU time 28.95 seconds
Started Aug 04 05:25:22 PM PDT 24
Finished Aug 04 05:25:51 PM PDT 24
Peak memory 242248 kb
Host smart-3d7ccee8-28a4-4c85-8237-abc5b33dd194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582567795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1582567795
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.797288824
Short name T842
Test name
Test status
Simulation time 1514643111 ps
CPU time 26.05 seconds
Started Aug 04 05:25:10 PM PDT 24
Finished Aug 04 05:25:37 PM PDT 24
Peak memory 241948 kb
Host smart-bf58e761-3218-43b1-ac2c-f79e243fc81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797288824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.797288824
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.48442831
Short name T959
Test name
Test status
Simulation time 106468603 ps
CPU time 3.13 seconds
Started Aug 04 05:25:21 PM PDT 24
Finished Aug 04 05:25:24 PM PDT 24
Peak memory 242056 kb
Host smart-e248f39a-fa49-4a3f-90de-04ddedbe4360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48442831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.48442831
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.466633344
Short name T206
Test name
Test status
Simulation time 1869660130 ps
CPU time 25.25 seconds
Started Aug 04 05:25:10 PM PDT 24
Finished Aug 04 05:25:36 PM PDT 24
Peak memory 250004 kb
Host smart-a3d1b777-82d7-4cc2-b11d-60e6b53e23ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466633344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.466633344
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.3883331476
Short name T687
Test name
Test status
Simulation time 1052975054 ps
CPU time 18.44 seconds
Started Aug 04 05:25:10 PM PDT 24
Finished Aug 04 05:25:29 PM PDT 24
Peak memory 242460 kb
Host smart-431a1d02-a4b8-4f4e-a3c6-358e4f4b089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883331476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3883331476
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.1898473437
Short name T941
Test name
Test status
Simulation time 1054480663 ps
CPU time 8.17 seconds
Started Aug 04 05:25:22 PM PDT 24
Finished Aug 04 05:25:30 PM PDT 24
Peak memory 241900 kb
Host smart-26233867-7ca3-4d27-afae-646e989c8d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898473437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.1898473437
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.1711581053
Short name T1188
Test name
Test status
Simulation time 1258290578 ps
CPU time 17.46 seconds
Started Aug 04 05:25:12 PM PDT 24
Finished Aug 04 05:25:29 PM PDT 24
Peak memory 248684 kb
Host smart-72725706-1cfc-470e-b189-c1ed9141796e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711581053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.1711581053
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.2640220858
Short name T619
Test name
Test status
Simulation time 288337125 ps
CPU time 9.47 seconds
Started Aug 04 05:25:09 PM PDT 24
Finished Aug 04 05:25:18 PM PDT 24
Peak memory 241864 kb
Host smart-5e94142c-1c5e-48df-b1a3-a60c906cfccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640220858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2640220858
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2604704102
Short name T995
Test name
Test status
Simulation time 3182601666 ps
CPU time 8.38 seconds
Started Aug 04 05:25:11 PM PDT 24
Finished Aug 04 05:25:19 PM PDT 24
Peak memory 241976 kb
Host smart-3c81a6c7-5b15-4c48-acf2-62d49cff412f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604704102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2604704102
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.4080021598
Short name T683
Test name
Test status
Simulation time 65019647684 ps
CPU time 181.29 seconds
Started Aug 04 05:25:15 PM PDT 24
Finished Aug 04 05:28:16 PM PDT 24
Peak memory 248688 kb
Host smart-574245f6-e437-450e-bdfc-80659ea45507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080021598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.4080021598
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.881498698
Short name T1164
Test name
Test status
Simulation time 3237981217 ps
CPU time 7.33 seconds
Started Aug 04 05:25:14 PM PDT 24
Finished Aug 04 05:25:21 PM PDT 24
Peak memory 241960 kb
Host smart-67be712b-3043-4e99-8c40-4e263fefd815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881498698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.881498698
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.809446989
Short name T830
Test name
Test status
Simulation time 157621585 ps
CPU time 4.04 seconds
Started Aug 04 05:27:05 PM PDT 24
Finished Aug 04 05:27:09 PM PDT 24
Peak memory 241972 kb
Host smart-ce9c418f-5ca0-4a68-84ba-0051ac68f6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809446989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.809446989
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3079779122
Short name T846
Test name
Test status
Simulation time 296791381 ps
CPU time 7.68 seconds
Started Aug 04 05:27:06 PM PDT 24
Finished Aug 04 05:27:14 PM PDT 24
Peak memory 242304 kb
Host smart-8529217c-e5e0-4199-ba88-bc292a264700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079779122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3079779122
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.3487216767
Short name T754
Test name
Test status
Simulation time 237022143 ps
CPU time 4.5 seconds
Started Aug 04 05:27:08 PM PDT 24
Finished Aug 04 05:27:13 PM PDT 24
Peak memory 241936 kb
Host smart-d45bcdfd-a483-4262-99d8-c81c8f5fb94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487216767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3487216767
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.4176421648
Short name T1067
Test name
Test status
Simulation time 505138051 ps
CPU time 12.1 seconds
Started Aug 04 05:27:05 PM PDT 24
Finished Aug 04 05:27:17 PM PDT 24
Peak memory 242156 kb
Host smart-31ac1806-f9af-4c6c-9b88-dced629f9014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176421648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.4176421648
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.446853140
Short name T932
Test name
Test status
Simulation time 107638135 ps
CPU time 3.78 seconds
Started Aug 04 05:27:08 PM PDT 24
Finished Aug 04 05:27:12 PM PDT 24
Peak memory 242000 kb
Host smart-b51658f4-f40b-4488-9abd-2e7373d27cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446853140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.446853140
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.4130305467
Short name T1134
Test name
Test status
Simulation time 888241102 ps
CPU time 7.62 seconds
Started Aug 04 05:27:08 PM PDT 24
Finished Aug 04 05:27:16 PM PDT 24
Peak memory 241920 kb
Host smart-5802d2e2-ea4d-42de-8268-6e141b89ad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130305467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.4130305467
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.577782619
Short name T196
Test name
Test status
Simulation time 2177459303 ps
CPU time 5.4 seconds
Started Aug 04 05:27:04 PM PDT 24
Finished Aug 04 05:27:10 PM PDT 24
Peak memory 242428 kb
Host smart-dd18ab3e-fac8-4b42-af14-583ea876f3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577782619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.577782619
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.3438853560
Short name T1096
Test name
Test status
Simulation time 1272619341 ps
CPU time 9.91 seconds
Started Aug 04 05:27:07 PM PDT 24
Finished Aug 04 05:27:17 PM PDT 24
Peak memory 242308 kb
Host smart-51313655-4f11-4d2f-9a7c-fe7f6bde14b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438853560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3438853560
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.505170551
Short name T577
Test name
Test status
Simulation time 603605037 ps
CPU time 4.01 seconds
Started Aug 04 05:27:10 PM PDT 24
Finished Aug 04 05:27:14 PM PDT 24
Peak memory 241904 kb
Host smart-9eb13c9b-6704-4f75-a5b3-24b5f75f87d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505170551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.505170551
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.3759926720
Short name T292
Test name
Test status
Simulation time 236092505 ps
CPU time 5.4 seconds
Started Aug 04 05:27:08 PM PDT 24
Finished Aug 04 05:27:14 PM PDT 24
Peak memory 241816 kb
Host smart-e8abe5f2-0a3b-4c1d-b766-6ed4a6ea26e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759926720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.3759926720
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.3504900218
Short name T688
Test name
Test status
Simulation time 161099815 ps
CPU time 4.51 seconds
Started Aug 04 05:27:07 PM PDT 24
Finished Aug 04 05:27:12 PM PDT 24
Peak memory 242284 kb
Host smart-abbda477-8b78-448c-a3f0-9e2a52b56397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504900218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.3504900218
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.4150527171
Short name T1191
Test name
Test status
Simulation time 1841161671 ps
CPU time 5.68 seconds
Started Aug 04 05:27:05 PM PDT 24
Finished Aug 04 05:27:11 PM PDT 24
Peak memory 241992 kb
Host smart-921d428d-b9dc-4427-a3ff-d71faaa534d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150527171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.4150527171
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.698893666
Short name T792
Test name
Test status
Simulation time 110001792 ps
CPU time 3.04 seconds
Started Aug 04 05:27:10 PM PDT 24
Finished Aug 04 05:27:13 PM PDT 24
Peak memory 241968 kb
Host smart-ec9e6fdd-ad96-4d02-8bf3-4a95bb0684f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698893666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.698893666
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.2360731381
Short name T596
Test name
Test status
Simulation time 294358530 ps
CPU time 16.65 seconds
Started Aug 04 05:27:05 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 241988 kb
Host smart-17d92df2-4a06-466a-90ea-4d25a2b28839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360731381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2360731381
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.1440780982
Short name T613
Test name
Test status
Simulation time 213842625 ps
CPU time 4.12 seconds
Started Aug 04 05:27:07 PM PDT 24
Finished Aug 04 05:27:11 PM PDT 24
Peak memory 242136 kb
Host smart-3030e3e2-3584-459f-a645-85a8545cf6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440780982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1440780982
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.1594011778
Short name T184
Test name
Test status
Simulation time 524718432 ps
CPU time 5.09 seconds
Started Aug 04 05:27:05 PM PDT 24
Finished Aug 04 05:27:10 PM PDT 24
Peak memory 241860 kb
Host smart-d99e6687-14be-4da1-9fdf-bbcea8ab770d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594011778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1594011778
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.2545618648
Short name T1130
Test name
Test status
Simulation time 107573061 ps
CPU time 3.1 seconds
Started Aug 04 05:27:08 PM PDT 24
Finished Aug 04 05:27:11 PM PDT 24
Peak memory 241992 kb
Host smart-78ea65fc-90e8-4cb9-b2a6-9b6c0e81ec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545618648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.2545618648
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.1482649331
Short name T718
Test name
Test status
Simulation time 126866686 ps
CPU time 5.16 seconds
Started Aug 04 05:27:06 PM PDT 24
Finished Aug 04 05:27:11 PM PDT 24
Peak memory 241968 kb
Host smart-deaea246-9014-47bb-8b30-d5bcdf250d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482649331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1482649331
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.2549783387
Short name T1112
Test name
Test status
Simulation time 1877488909 ps
CPU time 5.52 seconds
Started Aug 04 05:27:07 PM PDT 24
Finished Aug 04 05:27:13 PM PDT 24
Peak memory 242416 kb
Host smart-90abd030-abf1-4f68-ba5d-c8765aa998b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549783387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2549783387
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.3693687081
Short name T565
Test name
Test status
Simulation time 352031265 ps
CPU time 5.22 seconds
Started Aug 04 05:27:07 PM PDT 24
Finished Aug 04 05:27:12 PM PDT 24
Peak memory 242088 kb
Host smart-797af8d8-bf6f-4e27-99af-2c84a4bc28ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693687081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.3693687081
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.3933496346
Short name T479
Test name
Test status
Simulation time 842260932 ps
CPU time 2.76 seconds
Started Aug 04 05:25:13 PM PDT 24
Finished Aug 04 05:25:16 PM PDT 24
Peak memory 240576 kb
Host smart-f8b64f3b-7fef-4b3f-bb1d-1e910e4bb72b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933496346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3933496346
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.1428283591
Short name T907
Test name
Test status
Simulation time 1197149999 ps
CPU time 11.96 seconds
Started Aug 04 05:25:14 PM PDT 24
Finished Aug 04 05:25:26 PM PDT 24
Peak memory 248492 kb
Host smart-d5c032b9-dc07-46b6-95be-d2e0d32f87f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428283591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1428283591
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.3050076660
Short name T917
Test name
Test status
Simulation time 10107301149 ps
CPU time 21.78 seconds
Started Aug 04 05:25:13 PM PDT 24
Finished Aug 04 05:25:35 PM PDT 24
Peak memory 242284 kb
Host smart-58099d4c-a7e1-4f0d-8012-192da98b43c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050076660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.3050076660
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.4003782525
Short name T105
Test name
Test status
Simulation time 3000046626 ps
CPU time 28.33 seconds
Started Aug 04 05:25:15 PM PDT 24
Finished Aug 04 05:25:43 PM PDT 24
Peak memory 248696 kb
Host smart-b02b062e-b331-4430-845b-c4b5d4c9e9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003782525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.4003782525
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.4232838842
Short name T601
Test name
Test status
Simulation time 241520536 ps
CPU time 4.28 seconds
Started Aug 04 05:25:15 PM PDT 24
Finished Aug 04 05:25:19 PM PDT 24
Peak memory 242476 kb
Host smart-4d8084c5-cde6-46f5-b230-38121307a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232838842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.4232838842
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.3846268242
Short name T1035
Test name
Test status
Simulation time 1669622069 ps
CPU time 5.3 seconds
Started Aug 04 05:25:14 PM PDT 24
Finished Aug 04 05:25:20 PM PDT 24
Peak memory 241912 kb
Host smart-7f500b57-6227-41a0-8a1b-8140b3f4f420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846268242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3846268242
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.2799809068
Short name T508
Test name
Test status
Simulation time 2975878667 ps
CPU time 20.31 seconds
Started Aug 04 05:25:13 PM PDT 24
Finished Aug 04 05:25:34 PM PDT 24
Peak memory 242368 kb
Host smart-954f9e94-95c3-4a5e-aff4-9b8c9b3f5905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799809068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2799809068
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.2297230773
Short name T106
Test name
Test status
Simulation time 12787413765 ps
CPU time 27.7 seconds
Started Aug 04 05:25:13 PM PDT 24
Finished Aug 04 05:25:41 PM PDT 24
Peak memory 242096 kb
Host smart-fab845ee-48be-444f-bf1d-5c9bbf8c9688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297230773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.2297230773
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.3743336944
Short name T755
Test name
Test status
Simulation time 726526139 ps
CPU time 11.13 seconds
Started Aug 04 05:25:17 PM PDT 24
Finished Aug 04 05:25:28 PM PDT 24
Peak memory 241964 kb
Host smart-0f0ad36e-fa9f-47fe-ab50-b4b4c74de68e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743336944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3743336944
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.3427725610
Short name T226
Test name
Test status
Simulation time 293094189 ps
CPU time 5.1 seconds
Started Aug 04 05:25:17 PM PDT 24
Finished Aug 04 05:25:22 PM PDT 24
Peak memory 241920 kb
Host smart-6e7af557-b4d1-4278-9601-497824edaba2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3427725610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.3427725610
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.4030025030
Short name T1066
Test name
Test status
Simulation time 300380685 ps
CPU time 5 seconds
Started Aug 04 05:25:13 PM PDT 24
Finished Aug 04 05:25:18 PM PDT 24
Peak memory 248512 kb
Host smart-262979bb-d1d8-4509-ae30-667a45909506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030025030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.4030025030
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.3780723572
Short name T781
Test name
Test status
Simulation time 16896775888 ps
CPU time 42.45 seconds
Started Aug 04 05:25:15 PM PDT 24
Finished Aug 04 05:25:57 PM PDT 24
Peak memory 242860 kb
Host smart-53aa3794-99a2-4dbe-a653-4e2578e4fd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780723572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.3780723572
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.2530767215
Short name T38
Test name
Test status
Simulation time 562924834 ps
CPU time 6.22 seconds
Started Aug 04 05:27:11 PM PDT 24
Finished Aug 04 05:27:18 PM PDT 24
Peak memory 242380 kb
Host smart-a8ae8a11-b09d-4e86-a18a-1a3c54a17db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530767215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.2530767215
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.591072842
Short name T1044
Test name
Test status
Simulation time 767733156 ps
CPU time 6.46 seconds
Started Aug 04 05:27:09 PM PDT 24
Finished Aug 04 05:27:16 PM PDT 24
Peak memory 242036 kb
Host smart-fea864bc-ad99-4bc6-be92-b24eaf6f8753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591072842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.591072842
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.458901908
Short name T404
Test name
Test status
Simulation time 1338544745 ps
CPU time 19.26 seconds
Started Aug 04 05:27:12 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 241956 kb
Host smart-6a1bd010-adcb-43a7-a038-883aa6d9301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458901908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.458901908
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.1284170177
Short name T386
Test name
Test status
Simulation time 1665274649 ps
CPU time 5.39 seconds
Started Aug 04 05:27:10 PM PDT 24
Finished Aug 04 05:27:16 PM PDT 24
Peak memory 242184 kb
Host smart-c11b50c0-72d8-4a24-8875-cc14241d7b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284170177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1284170177
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.355622743
Short name T309
Test name
Test status
Simulation time 230038536 ps
CPU time 4.65 seconds
Started Aug 04 05:27:09 PM PDT 24
Finished Aug 04 05:27:14 PM PDT 24
Peak memory 242032 kb
Host smart-581856b6-c900-49f6-afa2-ecc04bbb11b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355622743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.355622743
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.2830252835
Short name T124
Test name
Test status
Simulation time 2480519515 ps
CPU time 4.69 seconds
Started Aug 04 05:27:08 PM PDT 24
Finished Aug 04 05:27:13 PM PDT 24
Peak memory 242312 kb
Host smart-21fddad3-b113-4c0f-ba28-6d38f571ae0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830252835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2830252835
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.3035840478
Short name T215
Test name
Test status
Simulation time 427460099 ps
CPU time 10.71 seconds
Started Aug 04 05:27:10 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 242300 kb
Host smart-4c1dd6ef-ee43-41c3-bffc-fa120408f13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035840478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3035840478
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.1903579885
Short name T1049
Test name
Test status
Simulation time 161530869 ps
CPU time 4.03 seconds
Started Aug 04 05:27:10 PM PDT 24
Finished Aug 04 05:27:15 PM PDT 24
Peak memory 242052 kb
Host smart-8d13db61-8ba1-4777-a228-077a5119976b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903579885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.1903579885
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.3688181650
Short name T878
Test name
Test status
Simulation time 294418064 ps
CPU time 7.36 seconds
Started Aug 04 05:27:10 PM PDT 24
Finished Aug 04 05:27:18 PM PDT 24
Peak memory 242280 kb
Host smart-7bdb86eb-127b-49cc-8ed5-dd0239820bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688181650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3688181650
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.2249712826
Short name T496
Test name
Test status
Simulation time 188245831 ps
CPU time 4.37 seconds
Started Aug 04 05:27:11 PM PDT 24
Finished Aug 04 05:27:16 PM PDT 24
Peak memory 242088 kb
Host smart-ea755c3f-0b38-4ce4-b585-e264ee3546a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249712826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2249712826
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.2484700250
Short name T390
Test name
Test status
Simulation time 408449192 ps
CPU time 4.87 seconds
Started Aug 04 05:27:10 PM PDT 24
Finished Aug 04 05:27:15 PM PDT 24
Peak memory 241864 kb
Host smart-f20dce23-4026-4fbd-97b1-de585ff59d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484700250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.2484700250
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.3443639717
Short name T979
Test name
Test status
Simulation time 208024881 ps
CPU time 4.69 seconds
Started Aug 04 05:27:10 PM PDT 24
Finished Aug 04 05:27:15 PM PDT 24
Peak memory 242200 kb
Host smart-fab43f23-02f2-4e8e-a525-3430d58928f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443639717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3443639717
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.4204323212
Short name T1121
Test name
Test status
Simulation time 1194978987 ps
CPU time 8.62 seconds
Started Aug 04 05:27:10 PM PDT 24
Finished Aug 04 05:27:18 PM PDT 24
Peak memory 241736 kb
Host smart-28ca73c5-1fdc-4dcd-a5da-0f3e6abdb1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204323212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.4204323212
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.1262597963
Short name T525
Test name
Test status
Simulation time 1708961956 ps
CPU time 4.51 seconds
Started Aug 04 05:27:11 PM PDT 24
Finished Aug 04 05:27:16 PM PDT 24
Peak memory 242468 kb
Host smart-ae5b4646-1cff-4fde-9e5d-b519b0b08aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262597963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1262597963
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.460200671
Short name T32
Test name
Test status
Simulation time 2805937250 ps
CPU time 5.4 seconds
Started Aug 04 05:27:12 PM PDT 24
Finished Aug 04 05:27:17 PM PDT 24
Peak memory 242300 kb
Host smart-6723ad6c-b9b4-4576-9a0c-db9b5f38d3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460200671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.460200671
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.292229495
Short name T306
Test name
Test status
Simulation time 109258626 ps
CPU time 4.45 seconds
Started Aug 04 05:27:11 PM PDT 24
Finished Aug 04 05:27:16 PM PDT 24
Peak memory 241832 kb
Host smart-6db5df10-13de-4597-97d2-c6335157e3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292229495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.292229495
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.3561269982
Short name T904
Test name
Test status
Simulation time 1951018609 ps
CPU time 5.09 seconds
Started Aug 04 05:27:11 PM PDT 24
Finished Aug 04 05:27:16 PM PDT 24
Peak memory 242172 kb
Host smart-169cfd4a-674f-4df6-9308-400d9d386574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561269982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.3561269982
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.1331239037
Short name T134
Test name
Test status
Simulation time 3301130839 ps
CPU time 5.91 seconds
Started Aug 04 05:27:13 PM PDT 24
Finished Aug 04 05:27:19 PM PDT 24
Peak memory 242104 kb
Host smart-101ca60c-9863-4311-b9de-1b366793a031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331239037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1331239037
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.4155304282
Short name T217
Test name
Test status
Simulation time 80073117 ps
CPU time 1.65 seconds
Started Aug 04 05:25:15 PM PDT 24
Finished Aug 04 05:25:17 PM PDT 24
Peak memory 240380 kb
Host smart-ff919ed5-64e3-43c7-bd4b-d644d4d21cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155304282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.4155304282
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.385172553
Short name T888
Test name
Test status
Simulation time 40397517037 ps
CPU time 169.03 seconds
Started Aug 04 05:25:21 PM PDT 24
Finished Aug 04 05:28:10 PM PDT 24
Peak memory 244504 kb
Host smart-da9ea19d-1d72-468d-879b-eb7ae8a73f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385172553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.385172553
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.1303734096
Short name T515
Test name
Test status
Simulation time 793408966 ps
CPU time 18.9 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:25:37 PM PDT 24
Peak memory 241868 kb
Host smart-413a67ae-9756-4b5b-87e1-82d613a45cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303734096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.1303734096
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.1475735245
Short name T937
Test name
Test status
Simulation time 1315377527 ps
CPU time 10.27 seconds
Started Aug 04 05:25:15 PM PDT 24
Finished Aug 04 05:25:25 PM PDT 24
Peak memory 242328 kb
Host smart-fd95d239-72b2-4ce8-816a-96a958f2cd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475735245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1475735245
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.1530185094
Short name T1092
Test name
Test status
Simulation time 212114483 ps
CPU time 3.27 seconds
Started Aug 04 05:25:17 PM PDT 24
Finished Aug 04 05:25:21 PM PDT 24
Peak memory 241932 kb
Host smart-60e385e9-3863-4a0c-9f99-1b1d91820e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530185094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1530185094
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.4176425042
Short name T930
Test name
Test status
Simulation time 1382058481 ps
CPU time 22.9 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:25:41 PM PDT 24
Peak memory 244232 kb
Host smart-a34ef532-9ea1-4236-aff4-8f0018c44dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176425042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.4176425042
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.1629423581
Short name T956
Test name
Test status
Simulation time 3434830143 ps
CPU time 11.01 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:35 PM PDT 24
Peak memory 241904 kb
Host smart-b15d67f5-e47a-42c9-ab4d-264d92dec7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629423581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.1629423581
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.3830843641
Short name T216
Test name
Test status
Simulation time 645440871 ps
CPU time 4.55 seconds
Started Aug 04 05:25:17 PM PDT 24
Finished Aug 04 05:25:22 PM PDT 24
Peak memory 242236 kb
Host smart-67190948-ac30-4cc9-8174-31509e811166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830843641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3830843641
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.124271199
Short name T648
Test name
Test status
Simulation time 110523513 ps
CPU time 2.98 seconds
Started Aug 04 05:25:17 PM PDT 24
Finished Aug 04 05:25:20 PM PDT 24
Peak memory 241972 kb
Host smart-cc9763ed-5026-4b53-8a9c-924f38654bc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124271199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.124271199
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.2193132702
Short name T566
Test name
Test status
Simulation time 262698639 ps
CPU time 8.49 seconds
Started Aug 04 05:25:14 PM PDT 24
Finished Aug 04 05:25:23 PM PDT 24
Peak memory 242164 kb
Host smart-71c674e0-6cad-4091-b01b-b63f32ed14cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193132702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.2193132702
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.1264079976
Short name T921
Test name
Test status
Simulation time 8517378567 ps
CPU time 20.22 seconds
Started Aug 04 05:25:19 PM PDT 24
Finished Aug 04 05:25:39 PM PDT 24
Peak memory 242892 kb
Host smart-1fc9e72f-538a-4ed7-b55f-9124ca336f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264079976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.1264079976
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.2558321470
Short name T259
Test name
Test status
Simulation time 32221350067 ps
CPU time 478.52 seconds
Started Aug 04 05:25:19 PM PDT 24
Finished Aug 04 05:33:17 PM PDT 24
Peak memory 248800 kb
Host smart-c5101bdd-854e-4b03-9191-9b1e36275fd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558321470 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.2558321470
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.2664221599
Short name T902
Test name
Test status
Simulation time 1116138724 ps
CPU time 6.95 seconds
Started Aug 04 05:25:22 PM PDT 24
Finished Aug 04 05:25:29 PM PDT 24
Peak memory 242048 kb
Host smart-1e41d1eb-6032-4de5-a938-5bcd99caea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664221599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.2664221599
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.869134469
Short name T1047
Test name
Test status
Simulation time 285850344 ps
CPU time 4.54 seconds
Started Aug 04 05:27:12 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 242024 kb
Host smart-859a41cb-5c39-44f9-979f-d206c01df336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869134469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.869134469
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.1064593573
Short name T161
Test name
Test status
Simulation time 4356956151 ps
CPU time 11.47 seconds
Started Aug 04 05:27:11 PM PDT 24
Finished Aug 04 05:27:22 PM PDT 24
Peak memory 241968 kb
Host smart-12c37220-1094-45c7-9cde-a93777472f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064593573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.1064593573
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.2866846210
Short name T116
Test name
Test status
Simulation time 120335624 ps
CPU time 3.21 seconds
Started Aug 04 05:27:12 PM PDT 24
Finished Aug 04 05:27:15 PM PDT 24
Peak memory 241888 kb
Host smart-b7164f83-752b-44d0-a009-ecd472f3bbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866846210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2866846210
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.971346803
Short name T551
Test name
Test status
Simulation time 123425744 ps
CPU time 3.82 seconds
Started Aug 04 05:27:11 PM PDT 24
Finished Aug 04 05:27:15 PM PDT 24
Peak memory 241892 kb
Host smart-6b3c1779-c396-430e-bf84-38085e8d231b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971346803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.971346803
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.1165286401
Short name T914
Test name
Test status
Simulation time 7401584495 ps
CPU time 16.28 seconds
Started Aug 04 05:27:12 PM PDT 24
Finished Aug 04 05:27:28 PM PDT 24
Peak memory 241820 kb
Host smart-047a859c-efff-406b-a591-3d60e4b49d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165286401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1165286401
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.1771534233
Short name T631
Test name
Test status
Simulation time 358805378 ps
CPU time 4.55 seconds
Started Aug 04 05:27:18 PM PDT 24
Finished Aug 04 05:27:22 PM PDT 24
Peak memory 242172 kb
Host smart-628e673a-8548-47b2-a82c-f7d6db8af065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771534233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.1771534233
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.112436709
Short name T719
Test name
Test status
Simulation time 154585077 ps
CPU time 3.99 seconds
Started Aug 04 05:27:19 PM PDT 24
Finished Aug 04 05:27:23 PM PDT 24
Peak memory 242052 kb
Host smart-dba46bc7-f7ce-4018-a45a-486aabed00df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112436709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.112436709
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.419552369
Short name T1190
Test name
Test status
Simulation time 546303738 ps
CPU time 4.44 seconds
Started Aug 04 05:27:27 PM PDT 24
Finished Aug 04 05:27:32 PM PDT 24
Peak memory 242012 kb
Host smart-80dc3a76-7ddc-475f-b43b-13ad437e0b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419552369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.419552369
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.4113031360
Short name T562
Test name
Test status
Simulation time 409295345 ps
CPU time 12.2 seconds
Started Aug 04 05:27:17 PM PDT 24
Finished Aug 04 05:27:30 PM PDT 24
Peak memory 241916 kb
Host smart-94559397-fbe6-405f-a2d4-4899f53a7b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113031360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.4113031360
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.1878405259
Short name T201
Test name
Test status
Simulation time 223824657 ps
CPU time 4.23 seconds
Started Aug 04 05:27:19 PM PDT 24
Finished Aug 04 05:27:24 PM PDT 24
Peak memory 242300 kb
Host smart-ed4d1872-db1e-4ea7-866a-aa895ba4dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878405259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1878405259
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.2555939558
Short name T276
Test name
Test status
Simulation time 1212249967 ps
CPU time 9.79 seconds
Started Aug 04 05:27:13 PM PDT 24
Finished Aug 04 05:27:23 PM PDT 24
Peak memory 241812 kb
Host smart-cd129e8e-4599-4d38-aace-4d0055910e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555939558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2555939558
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.127863513
Short name T279
Test name
Test status
Simulation time 299552325 ps
CPU time 4.44 seconds
Started Aug 04 05:27:17 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 242368 kb
Host smart-ed8cb3e6-b136-4ab0-b0d3-6b3baef68cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127863513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.127863513
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.4125122189
Short name T997
Test name
Test status
Simulation time 246749397 ps
CPU time 3.82 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 241936 kb
Host smart-5b3bab15-51a0-409b-905c-66a86deb1af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125122189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.4125122189
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.1056201087
Short name T814
Test name
Test status
Simulation time 305577952 ps
CPU time 4.12 seconds
Started Aug 04 05:27:15 PM PDT 24
Finished Aug 04 05:27:19 PM PDT 24
Peak memory 242236 kb
Host smart-3ecba847-be6b-4998-93d1-010141b48808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056201087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1056201087
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.162077003
Short name T858
Test name
Test status
Simulation time 973534516 ps
CPU time 7.83 seconds
Started Aug 04 05:27:17 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 241920 kb
Host smart-2b83cb62-8597-4178-8665-565a96c8074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162077003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.162077003
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.2742240467
Short name T1155
Test name
Test status
Simulation time 2737106340 ps
CPU time 7.57 seconds
Started Aug 04 05:27:22 PM PDT 24
Finished Aug 04 05:27:29 PM PDT 24
Peak memory 241864 kb
Host smart-2613020a-0b41-4420-8f0d-92236d66adc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742240467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.2742240467
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.1275256250
Short name T849
Test name
Test status
Simulation time 8161011540 ps
CPU time 19.26 seconds
Started Aug 04 05:27:15 PM PDT 24
Finished Aug 04 05:27:35 PM PDT 24
Peak memory 241948 kb
Host smart-28b42ec8-de34-4fe1-9d76-65cbb5b737d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275256250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.1275256250
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.573192539
Short name T90
Test name
Test status
Simulation time 158468987 ps
CPU time 4.62 seconds
Started Aug 04 05:27:18 PM PDT 24
Finished Aug 04 05:27:22 PM PDT 24
Peak memory 242148 kb
Host smart-60b2f97f-a1f3-4a0a-a468-38a3414d21df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573192539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.573192539
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.1700069004
Short name T524
Test name
Test status
Simulation time 419263663 ps
CPU time 3.74 seconds
Started Aug 04 05:27:22 PM PDT 24
Finished Aug 04 05:27:26 PM PDT 24
Peak memory 242232 kb
Host smart-7f3b5799-becf-437b-b721-e883088e8dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700069004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.1700069004
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.525123813
Short name T190
Test name
Test status
Simulation time 64644266 ps
CPU time 2.09 seconds
Started Aug 04 05:25:20 PM PDT 24
Finished Aug 04 05:25:22 PM PDT 24
Peak memory 240544 kb
Host smart-cde75afb-d89e-4ac8-ae64-8cb96f363958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525123813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.525123813
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.815852456
Short name T399
Test name
Test status
Simulation time 7391707496 ps
CPU time 50.98 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:26:09 PM PDT 24
Peak memory 242544 kb
Host smart-576352ff-e46d-48cd-96bf-9ab5e147d72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815852456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.815852456
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.979748098
Short name T1009
Test name
Test status
Simulation time 1380898860 ps
CPU time 27.54 seconds
Started Aug 04 05:25:21 PM PDT 24
Finished Aug 04 05:25:49 PM PDT 24
Peak memory 242512 kb
Host smart-f5d1be1d-edc1-4308-a20c-a881d951e42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979748098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.979748098
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.623299583
Short name T741
Test name
Test status
Simulation time 189077407 ps
CPU time 4.39 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:25:22 PM PDT 24
Peak memory 242180 kb
Host smart-17386e7a-abb0-46d5-9fe6-5e56376da4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623299583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.623299583
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.3353278102
Short name T1158
Test name
Test status
Simulation time 1140388071 ps
CPU time 37.39 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:26:02 PM PDT 24
Peak memory 246904 kb
Host smart-28627106-757c-4f34-be99-0ecb0141e467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353278102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.3353278102
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.2960997562
Short name T738
Test name
Test status
Simulation time 324149922 ps
CPU time 6.87 seconds
Started Aug 04 05:25:16 PM PDT 24
Finished Aug 04 05:25:23 PM PDT 24
Peak memory 242300 kb
Host smart-3b1a705a-52e7-437f-a0f9-8e9f26dcac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960997562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2960997562
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.3798068062
Short name T978
Test name
Test status
Simulation time 431605664 ps
CPU time 8.25 seconds
Started Aug 04 05:25:17 PM PDT 24
Finished Aug 04 05:25:25 PM PDT 24
Peak memory 242260 kb
Host smart-b7d66084-2c06-45b3-a67e-6a4e1dc82702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798068062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3798068062
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.2442047716
Short name T1016
Test name
Test status
Simulation time 1496336520 ps
CPU time 23.32 seconds
Started Aug 04 05:25:39 PM PDT 24
Finished Aug 04 05:26:03 PM PDT 24
Peak memory 248644 kb
Host smart-f7bfb245-314a-4cef-818d-1082627440b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442047716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2442047716
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.1864523424
Short name T844
Test name
Test status
Simulation time 4005076885 ps
CPU time 12.56 seconds
Started Aug 04 05:25:16 PM PDT 24
Finished Aug 04 05:25:29 PM PDT 24
Peak memory 242108 kb
Host smart-08466e77-d1e6-4c46-a029-c0f7f1fcdbd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864523424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1864523424
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.1739182964
Short name T391
Test name
Test status
Simulation time 204779499 ps
CPU time 4.49 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:29 PM PDT 24
Peak memory 241896 kb
Host smart-29868838-8ba7-4498-aff2-91cf16ec1622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739182964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.1739182964
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.1117574222
Short name T606
Test name
Test status
Simulation time 221672779371 ps
CPU time 484.67 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:33:22 PM PDT 24
Peak memory 258472 kb
Host smart-029eb83c-8d07-4d79-9d7e-39b6561fc443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117574222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.1117574222
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.3422593555
Short name T951
Test name
Test status
Simulation time 126627417417 ps
CPU time 1811.34 seconds
Started Aug 04 05:25:17 PM PDT 24
Finished Aug 04 05:55:29 PM PDT 24
Peak memory 273356 kb
Host smart-731fb099-48d7-4e39-912f-491558162bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422593555 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.3422593555
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.4211520559
Short name T628
Test name
Test status
Simulation time 21023406957 ps
CPU time 60.32 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:26:18 PM PDT 24
Peak memory 243132 kb
Host smart-2c9f95bf-ed03-4d8c-a6fd-b2687ba7ee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211520559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.4211520559
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.2442907665
Short name T509
Test name
Test status
Simulation time 146299696 ps
CPU time 4.2 seconds
Started Aug 04 05:27:17 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 242444 kb
Host smart-fc594fdc-5bab-4816-bfdc-61f6f18ef272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442907665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2442907665
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.3291504194
Short name T667
Test name
Test status
Simulation time 1121254079 ps
CPU time 15.5 seconds
Started Aug 04 05:27:14 PM PDT 24
Finished Aug 04 05:27:29 PM PDT 24
Peak memory 248436 kb
Host smart-a6e34e2e-d812-4138-8009-13b4b458e4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291504194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3291504194
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.1905730605
Short name T449
Test name
Test status
Simulation time 139335826 ps
CPU time 3.58 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 242260 kb
Host smart-a2eae543-6a51-4acc-a083-3d82c1e71244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905730605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.1905730605
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.2225429126
Short name T790
Test name
Test status
Simulation time 460142890 ps
CPU time 5.24 seconds
Started Aug 04 05:27:25 PM PDT 24
Finished Aug 04 05:27:30 PM PDT 24
Peak memory 241840 kb
Host smart-d78fde7d-a2a6-451d-a29b-17c8b6bd52a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225429126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2225429126
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.1095330744
Short name T835
Test name
Test status
Simulation time 259586681 ps
CPU time 3.64 seconds
Started Aug 04 05:27:17 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 241904 kb
Host smart-a57f2443-5bcb-4d58-957d-9e809f38429a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095330744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.1095330744
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.2552714466
Short name T1028
Test name
Test status
Simulation time 415408008 ps
CPU time 5.25 seconds
Started Aug 04 05:27:19 PM PDT 24
Finished Aug 04 05:27:24 PM PDT 24
Peak memory 248512 kb
Host smart-e15d57dd-2ef6-4124-bd53-58f646376578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552714466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.2552714466
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.676721675
Short name T923
Test name
Test status
Simulation time 86077563 ps
CPU time 3.36 seconds
Started Aug 04 05:27:17 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 242292 kb
Host smart-4c368495-3eb8-45e5-821e-69b9471ab72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676721675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.676721675
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.815346993
Short name T144
Test name
Test status
Simulation time 407518675 ps
CPU time 12.71 seconds
Started Aug 04 05:27:17 PM PDT 24
Finished Aug 04 05:27:30 PM PDT 24
Peak memory 242300 kb
Host smart-cc302b0c-0239-49cf-801b-fd1936bc3b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815346993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.815346993
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.476222996
Short name T197
Test name
Test status
Simulation time 182826465 ps
CPU time 3.61 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:24 PM PDT 24
Peak memory 241908 kb
Host smart-daf1a613-45b4-4631-ba92-7079742459c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476222996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.476222996
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.2383875812
Short name T899
Test name
Test status
Simulation time 238180923 ps
CPU time 4.91 seconds
Started Aug 04 05:27:20 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 242020 kb
Host smart-d9cff220-9b3f-4d60-8801-482b7c3505ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383875812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.2383875812
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.759878769
Short name T78
Test name
Test status
Simulation time 303974701 ps
CPU time 3.99 seconds
Started Aug 04 05:27:14 PM PDT 24
Finished Aug 04 05:27:18 PM PDT 24
Peak memory 242084 kb
Host smart-bac23cdb-7e98-40e7-a39b-b2b6a7c92ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759878769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.759878769
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.3418896933
Short name T809
Test name
Test status
Simulation time 220274299 ps
CPU time 4.32 seconds
Started Aug 04 05:27:22 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 241916 kb
Host smart-cfb609d6-db60-4181-8b4e-c36237c50059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418896933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3418896933
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.3033260919
Short name T963
Test name
Test status
Simulation time 184658676 ps
CPU time 4.83 seconds
Started Aug 04 05:27:18 PM PDT 24
Finished Aug 04 05:27:23 PM PDT 24
Peak memory 242020 kb
Host smart-549460f8-c9de-4011-a89b-d60435a38cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033260919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.3033260919
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.1124834379
Short name T1149
Test name
Test status
Simulation time 208915701 ps
CPU time 3 seconds
Started Aug 04 05:27:22 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 241984 kb
Host smart-21de8b9f-8675-4881-a1fa-add34d36dde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124834379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.1124834379
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.3075356234
Short name T422
Test name
Test status
Simulation time 1544204193 ps
CPU time 3.12 seconds
Started Aug 04 05:27:16 PM PDT 24
Finished Aug 04 05:27:19 PM PDT 24
Peak memory 241956 kb
Host smart-3a8ae563-3ff1-47c7-ba54-720d25e1abfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075356234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3075356234
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.3611615747
Short name T1063
Test name
Test status
Simulation time 211924884 ps
CPU time 5.96 seconds
Started Aug 04 05:27:18 PM PDT 24
Finished Aug 04 05:27:24 PM PDT 24
Peak memory 242020 kb
Host smart-ede9f488-a6ca-4a41-a5b8-82cbd35f58af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611615747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.3611615747
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.566349870
Short name T121
Test name
Test status
Simulation time 578368755 ps
CPU time 4.86 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:28 PM PDT 24
Peak memory 241940 kb
Host smart-22da0b36-4118-408c-ab59-2cb8c744d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566349870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.566349870
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.1553190065
Short name T1085
Test name
Test status
Simulation time 754625112 ps
CPU time 9.51 seconds
Started Aug 04 05:27:17 PM PDT 24
Finished Aug 04 05:27:26 PM PDT 24
Peak memory 242160 kb
Host smart-f7accd3f-2405-4691-9bc0-9e8c376c6410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553190065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.1553190065
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.2378394458
Short name T47
Test name
Test status
Simulation time 120827836 ps
CPU time 4.42 seconds
Started Aug 04 05:27:19 PM PDT 24
Finished Aug 04 05:27:23 PM PDT 24
Peak memory 242220 kb
Host smart-df860351-1bcb-4754-a301-9e1b6e89636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378394458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2378394458
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.1800175642
Short name T274
Test name
Test status
Simulation time 410680665 ps
CPU time 3.38 seconds
Started Aug 04 05:27:13 PM PDT 24
Finished Aug 04 05:27:17 PM PDT 24
Peak memory 241992 kb
Host smart-e8d10ce9-2a56-4809-a684-4f64843d4b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800175642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1800175642
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.2291216409
Short name T396
Test name
Test status
Simulation time 65454191 ps
CPU time 1.78 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:24:32 PM PDT 24
Peak memory 240352 kb
Host smart-a1169833-7a70-4a8d-9dec-e7b1fb06859c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291216409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2291216409
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.3204054589
Short name T894
Test name
Test status
Simulation time 1011708825 ps
CPU time 11.63 seconds
Started Aug 04 05:24:32 PM PDT 24
Finished Aug 04 05:24:43 PM PDT 24
Peak memory 242364 kb
Host smart-49c40bb0-6f5a-4a90-85fd-059b91680250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204054589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.3204054589
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.3952798034
Short name T1131
Test name
Test status
Simulation time 2033573565 ps
CPU time 41.1 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:25:11 PM PDT 24
Peak memory 242368 kb
Host smart-cc0811ef-1a14-4ee2-a22e-e1b8084b843c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952798034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3952798034
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.2532695054
Short name T546
Test name
Test status
Simulation time 17192536768 ps
CPU time 56.79 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:25:27 PM PDT 24
Peak memory 250796 kb
Host smart-6b603a64-5beb-4a61-8a1c-6f9a6e78664e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532695054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.2532695054
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.2725861821
Short name T1026
Test name
Test status
Simulation time 1675976287 ps
CPU time 37.37 seconds
Started Aug 04 05:24:31 PM PDT 24
Finished Aug 04 05:25:09 PM PDT 24
Peak memory 242380 kb
Host smart-26d5e61a-5ffd-4d0a-8ff2-ac885984b69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725861821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.2725861821
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.3045926200
Short name T1
Test name
Test status
Simulation time 430054154 ps
CPU time 4.93 seconds
Started Aug 04 05:24:32 PM PDT 24
Finished Aug 04 05:24:37 PM PDT 24
Peak memory 241904 kb
Host smart-82824dc6-951d-4b75-a448-465ac64cf16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045926200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.3045926200
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.2839772778
Short name T1183
Test name
Test status
Simulation time 1284695855 ps
CPU time 25.5 seconds
Started Aug 04 05:24:29 PM PDT 24
Finished Aug 04 05:24:55 PM PDT 24
Peak memory 248592 kb
Host smart-f91ceaf8-1dfa-4d0c-85d3-f35525619673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839772778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.2839772778
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.2358138948
Short name T919
Test name
Test status
Simulation time 3007440359 ps
CPU time 37.85 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:25:08 PM PDT 24
Peak memory 242232 kb
Host smart-a51d8553-a0a5-49ac-8bd0-23be06868bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358138948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2358138948
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.3545380328
Short name T275
Test name
Test status
Simulation time 339103348 ps
CPU time 5.58 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:24:36 PM PDT 24
Peak memory 241828 kb
Host smart-786211d8-4201-415f-957c-4c047db3325b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545380328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.3545380328
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.1150476909
Short name T255
Test name
Test status
Simulation time 1669992500 ps
CPU time 25.09 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:24:55 PM PDT 24
Peak memory 248604 kb
Host smart-1e2fc1da-6cd2-4a07-81fa-ad4a0f5a897c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150476909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.1150476909
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.3144189264
Short name T1051
Test name
Test status
Simulation time 2128271781 ps
CPU time 5.75 seconds
Started Aug 04 05:24:32 PM PDT 24
Finished Aug 04 05:24:38 PM PDT 24
Peak memory 242040 kb
Host smart-ccbebbe9-fd69-4f65-b4d6-d04c318a1740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3144189264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.3144189264
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.1892023708
Short name T618
Test name
Test status
Simulation time 3236672023 ps
CPU time 9.16 seconds
Started Aug 04 05:24:33 PM PDT 24
Finished Aug 04 05:24:42 PM PDT 24
Peak memory 241932 kb
Host smart-16c814d4-242b-4edb-b34b-0c92d955d94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892023708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1892023708
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.3093762390
Short name T243
Test name
Test status
Simulation time 819436258571 ps
CPU time 2485.01 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 06:05:56 PM PDT 24
Peak memory 358536 kb
Host smart-4d33e911-a0b4-466f-9d0a-17eca006820a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093762390 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.3093762390
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.1091392290
Short name T159
Test name
Test status
Simulation time 2041831687 ps
CPU time 13.58 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:24:43 PM PDT 24
Peak memory 242416 kb
Host smart-208f464d-46bd-48ac-983d-0773b1b9ca70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091392290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.1091392290
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.2793018124
Short name T716
Test name
Test status
Simulation time 185522344 ps
CPU time 1.93 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:26 PM PDT 24
Peak memory 240728 kb
Host smart-ddd9b99d-081b-4735-a773-3a8cde19176e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793018124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.2793018124
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.1111196157
Short name T42
Test name
Test status
Simulation time 530388203 ps
CPU time 12.82 seconds
Started Aug 04 05:25:29 PM PDT 24
Finished Aug 04 05:25:42 PM PDT 24
Peak memory 242272 kb
Host smart-22c57f16-451e-4dc1-9c31-d2514f581ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111196157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1111196157
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.1696498308
Short name T594
Test name
Test status
Simulation time 838556662 ps
CPU time 9.54 seconds
Started Aug 04 05:25:17 PM PDT 24
Finished Aug 04 05:25:26 PM PDT 24
Peak memory 241904 kb
Host smart-6b0bcdd9-ea9d-43ff-afab-532b9ea125ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696498308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.1696498308
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.2401382334
Short name T1180
Test name
Test status
Simulation time 1460828432 ps
CPU time 12.35 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:25:30 PM PDT 24
Peak memory 241808 kb
Host smart-455a9a3e-cf48-48ce-b56e-266cfb5d88e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401382334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.2401382334
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.1005778665
Short name T62
Test name
Test status
Simulation time 214239294 ps
CPU time 5.29 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:25:24 PM PDT 24
Peak memory 242368 kb
Host smart-94a71bb1-6e1d-4583-9dbf-3354c027f795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005778665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.1005778665
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.3002126184
Short name T528
Test name
Test status
Simulation time 1617186533 ps
CPU time 33.18 seconds
Started Aug 04 05:25:20 PM PDT 24
Finished Aug 04 05:25:53 PM PDT 24
Peak memory 248596 kb
Host smart-5d1415b8-f3b5-4653-a915-5eb24b49cc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002126184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3002126184
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.1014181272
Short name T462
Test name
Test status
Simulation time 849827278 ps
CPU time 7.8 seconds
Started Aug 04 05:25:20 PM PDT 24
Finished Aug 04 05:25:28 PM PDT 24
Peak memory 248528 kb
Host smart-a2e99d22-d930-4ebb-a083-1fec8115ba50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014181272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.1014181272
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.430889536
Short name T630
Test name
Test status
Simulation time 1167339642 ps
CPU time 27.88 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:25:46 PM PDT 24
Peak memory 241936 kb
Host smart-64b2efdd-c0dc-4d8b-8dd5-ae26d0a5d2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430889536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.430889536
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.860341527
Short name T789
Test name
Test status
Simulation time 7598947183 ps
CPU time 20.27 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:45 PM PDT 24
Peak memory 241904 kb
Host smart-3fc54460-2227-4691-9e87-0d588cdb93f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860341527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.860341527
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.644020141
Short name T845
Test name
Test status
Simulation time 130575792 ps
CPU time 5.69 seconds
Started Aug 04 05:25:22 PM PDT 24
Finished Aug 04 05:25:28 PM PDT 24
Peak memory 241896 kb
Host smart-5269ad59-a26d-47e1-a6aa-98bbf0b68fe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=644020141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.644020141
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.428685148
Short name T368
Test name
Test status
Simulation time 472275566 ps
CPU time 4.26 seconds
Started Aug 04 05:25:18 PM PDT 24
Finished Aug 04 05:25:22 PM PDT 24
Peak memory 242440 kb
Host smart-4a3f9062-e551-4990-8838-2b76d20998d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428685148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.428685148
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.521841870
Short name T833
Test name
Test status
Simulation time 48201678670 ps
CPU time 909.81 seconds
Started Aug 04 05:25:29 PM PDT 24
Finished Aug 04 05:40:39 PM PDT 24
Peak memory 287412 kb
Host smart-dfb727dc-23c4-4b99-81c5-1051678a7b2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521841870 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.521841870
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.624829584
Short name T783
Test name
Test status
Simulation time 2306639820 ps
CPU time 5.93 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:30 PM PDT 24
Peak memory 242424 kb
Host smart-fb912734-7a6b-4911-8856-ef8a182bc5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624829584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.624829584
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.980656797
Short name T1042
Test name
Test status
Simulation time 513747879 ps
CPU time 3.77 seconds
Started Aug 04 05:27:18 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 242160 kb
Host smart-8173f601-5496-496e-8ca2-66c9be930183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980656797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.980656797
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.1289789807
Short name T417
Test name
Test status
Simulation time 136618571 ps
CPU time 3.49 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:24 PM PDT 24
Peak memory 242348 kb
Host smart-3beeec97-f0cb-4f54-b7d6-b227715bc4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289789807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.1289789807
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.838601772
Short name T1137
Test name
Test status
Simulation time 111506896 ps
CPU time 3.61 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 242264 kb
Host smart-eca7e82f-e117-4220-91b3-935d0a611c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838601772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.838601772
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.3851697353
Short name T31
Test name
Test status
Simulation time 161715654 ps
CPU time 4.02 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 242216 kb
Host smart-e5926396-2688-4b10-ab02-e20385826429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851697353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.3851697353
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.2938535516
Short name T1099
Test name
Test status
Simulation time 344642409 ps
CPU time 3.84 seconds
Started Aug 04 05:27:18 PM PDT 24
Finished Aug 04 05:27:22 PM PDT 24
Peak memory 241972 kb
Host smart-b4e2e5bd-42d6-4ccb-ad3b-669dad6beedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938535516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2938535516
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.2233737603
Short name T166
Test name
Test status
Simulation time 249056862 ps
CPU time 3.81 seconds
Started Aug 04 05:27:22 PM PDT 24
Finished Aug 04 05:27:26 PM PDT 24
Peak memory 242436 kb
Host smart-7ee2cb1a-64f3-48ee-a4f4-c6cecd0b2daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233737603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2233737603
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.4081901596
Short name T472
Test name
Test status
Simulation time 557536546 ps
CPU time 4.73 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:26 PM PDT 24
Peak memory 241888 kb
Host smart-b66a6952-39e4-48d6-b551-d7a8de0127bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081901596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.4081901596
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.113226333
Short name T692
Test name
Test status
Simulation time 592725839 ps
CPU time 4.52 seconds
Started Aug 04 05:27:20 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 241944 kb
Host smart-e9a0d476-d398-4008-a855-a38e5d691299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113226333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.113226333
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.2138391698
Short name T173
Test name
Test status
Simulation time 119652277 ps
CPU time 3.41 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 241904 kb
Host smart-ee575f16-8901-44b5-8ce9-c36ec464df6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138391698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2138391698
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.2004200721
Short name T636
Test name
Test status
Simulation time 131628803 ps
CPU time 2.21 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:26 PM PDT 24
Peak memory 240604 kb
Host smart-0a6d7665-87b8-41d5-b3b7-63e120239823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004200721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.2004200721
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.3508272446
Short name T1039
Test name
Test status
Simulation time 4332987148 ps
CPU time 14.65 seconds
Started Aug 04 05:25:20 PM PDT 24
Finished Aug 04 05:25:35 PM PDT 24
Peak memory 242116 kb
Host smart-f153648d-aa15-4286-9b69-eb98267fac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508272446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.3508272446
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3773420579
Short name T504
Test name
Test status
Simulation time 645264428 ps
CPU time 9.3 seconds
Started Aug 04 05:25:29 PM PDT 24
Finished Aug 04 05:25:39 PM PDT 24
Peak memory 242352 kb
Host smart-e2f41816-eeb2-4a46-a24c-252ac9b2c34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773420579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3773420579
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.228805321
Short name T354
Test name
Test status
Simulation time 572340285 ps
CPU time 12.73 seconds
Started Aug 04 05:25:22 PM PDT 24
Finished Aug 04 05:25:34 PM PDT 24
Peak memory 242232 kb
Host smart-124ed9ab-bdeb-4bc2-a57e-a01c32c5bc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228805321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.228805321
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.3248148954
Short name T1175
Test name
Test status
Simulation time 566215968 ps
CPU time 4.51 seconds
Started Aug 04 05:25:21 PM PDT 24
Finished Aug 04 05:25:25 PM PDT 24
Peak memory 242280 kb
Host smart-14c8b5b9-446d-4ae6-bd7a-618ced0839af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248148954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.3248148954
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.909614752
Short name T624
Test name
Test status
Simulation time 640779427 ps
CPU time 11.63 seconds
Started Aug 04 05:25:21 PM PDT 24
Finished Aug 04 05:25:32 PM PDT 24
Peak memory 242340 kb
Host smart-9ac26944-860e-406c-8af7-49c3b2d67cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909614752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.909614752
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.1910714411
Short name T1031
Test name
Test status
Simulation time 4307785034 ps
CPU time 44.96 seconds
Started Aug 04 05:25:21 PM PDT 24
Finished Aug 04 05:26:06 PM PDT 24
Peak memory 242088 kb
Host smart-0aa1d65d-ae5e-47e2-af35-4da01b640989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910714411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1910714411
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.1499669482
Short name T402
Test name
Test status
Simulation time 1443962717 ps
CPU time 6.45 seconds
Started Aug 04 05:25:29 PM PDT 24
Finished Aug 04 05:25:36 PM PDT 24
Peak memory 242348 kb
Host smart-aefd6070-9b56-4497-812a-4dc1115f4399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499669482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.1499669482
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.2033037112
Short name T742
Test name
Test status
Simulation time 559235354 ps
CPU time 8.15 seconds
Started Aug 04 05:25:19 PM PDT 24
Finished Aug 04 05:25:28 PM PDT 24
Peak memory 242152 kb
Host smart-60574725-c5b9-456e-8054-09076c955dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033037112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2033037112
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.3685402241
Short name T766
Test name
Test status
Simulation time 620317661 ps
CPU time 6.64 seconds
Started Aug 04 05:25:20 PM PDT 24
Finished Aug 04 05:25:27 PM PDT 24
Peak memory 241948 kb
Host smart-e45d7ffd-9424-4a53-b4e8-ea5fff0c0489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685402241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.3685402241
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.2904442775
Short name T93
Test name
Test status
Simulation time 1284472816 ps
CPU time 7.41 seconds
Started Aug 04 05:25:21 PM PDT 24
Finished Aug 04 05:25:28 PM PDT 24
Peak memory 248156 kb
Host smart-5556e881-a901-418f-ab4f-f12b0e48f47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904442775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2904442775
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.2392980826
Short name T1182
Test name
Test status
Simulation time 63598889961 ps
CPU time 107.02 seconds
Started Aug 04 05:25:27 PM PDT 24
Finished Aug 04 05:27:14 PM PDT 24
Peak memory 263968 kb
Host smart-b9254668-d1c4-4531-8299-e3d7e4c39854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392980826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.2392980826
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2051842037
Short name T302
Test name
Test status
Simulation time 130715961431 ps
CPU time 2088.28 seconds
Started Aug 04 05:25:29 PM PDT 24
Finished Aug 04 06:00:18 PM PDT 24
Peak memory 367736 kb
Host smart-e57b5960-c0b7-4537-9efb-60d1be4c68f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051842037 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.2051842037
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.2882707569
Short name T970
Test name
Test status
Simulation time 693537304 ps
CPU time 16.14 seconds
Started Aug 04 05:25:20 PM PDT 24
Finished Aug 04 05:25:36 PM PDT 24
Peak memory 241900 kb
Host smart-87fe4f66-d5f7-473b-82be-d80788a6b5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882707569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.2882707569
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.1007719294
Short name T545
Test name
Test status
Simulation time 143240534 ps
CPU time 3.51 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 241932 kb
Host smart-b08b2548-449d-4841-9c20-d54d6c7fef02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007719294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1007719294
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.2287346078
Short name T437
Test name
Test status
Simulation time 336022584 ps
CPU time 4.83 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:26 PM PDT 24
Peak memory 241836 kb
Host smart-5642dc12-a64b-429d-ba90-96817322243d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287346078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2287346078
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.122632095
Short name T582
Test name
Test status
Simulation time 131082538 ps
CPU time 3.64 seconds
Started Aug 04 05:27:19 PM PDT 24
Finished Aug 04 05:27:23 PM PDT 24
Peak memory 242172 kb
Host smart-b166f093-fb30-4b8c-b9df-07b3c9331b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122632095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.122632095
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.1321249314
Short name T977
Test name
Test status
Simulation time 1576664518 ps
CPU time 5.67 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 241924 kb
Host smart-89f0b88b-cff6-4ce1-9082-b74ce7ec8b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321249314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1321249314
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.338393607
Short name T985
Test name
Test status
Simulation time 2035756817 ps
CPU time 5.56 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:28 PM PDT 24
Peak memory 242072 kb
Host smart-0918e78d-740a-4482-9a6f-721848ced54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338393607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.338393607
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.3096453031
Short name T782
Test name
Test status
Simulation time 390334010 ps
CPU time 3.95 seconds
Started Aug 04 05:27:25 PM PDT 24
Finished Aug 04 05:27:29 PM PDT 24
Peak memory 241948 kb
Host smart-a4ec5f40-8d38-48e3-9d0e-379d3677c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096453031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3096453031
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.2880471662
Short name T419
Test name
Test status
Simulation time 227783794 ps
CPU time 4.7 seconds
Started Aug 04 05:27:20 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 241884 kb
Host smart-87411ead-7fc4-4cf0-89e5-689443000f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880471662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.2880471662
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2542660947
Short name T831
Test name
Test status
Simulation time 707063090 ps
CPU time 4.53 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 241832 kb
Host smart-08b87d3d-3894-4415-9731-18d52158493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542660947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2542660947
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.3428151895
Short name T74
Test name
Test status
Simulation time 320022893 ps
CPU time 3.86 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 242412 kb
Host smart-43cdbaa6-18cf-4166-b223-a1e4ee216985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428151895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3428151895
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.2753943419
Short name T969
Test name
Test status
Simulation time 146969345 ps
CPU time 4.25 seconds
Started Aug 04 05:27:18 PM PDT 24
Finished Aug 04 05:27:23 PM PDT 24
Peak memory 241948 kb
Host smart-b1eee513-202c-42de-8221-0f0f356a80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753943419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2753943419
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.4165983358
Short name T429
Test name
Test status
Simulation time 95860777 ps
CPU time 2.04 seconds
Started Aug 04 05:25:27 PM PDT 24
Finished Aug 04 05:25:29 PM PDT 24
Peak memory 240480 kb
Host smart-8bed02a5-00a7-4ea4-9fa9-9f948e46663a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165983358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.4165983358
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.3902457864
Short name T482
Test name
Test status
Simulation time 758036696 ps
CPU time 23.57 seconds
Started Aug 04 05:25:27 PM PDT 24
Finished Aug 04 05:25:50 PM PDT 24
Peak memory 241796 kb
Host smart-b02ccff9-45df-4fa7-8fbe-15443536307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902457864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.3902457864
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.1719447272
Short name T860
Test name
Test status
Simulation time 2043720066 ps
CPU time 23.5 seconds
Started Aug 04 05:25:25 PM PDT 24
Finished Aug 04 05:25:49 PM PDT 24
Peak memory 242112 kb
Host smart-167051c9-fa83-41f8-bec5-b7d8de0b418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719447272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.1719447272
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.1168465808
Short name T641
Test name
Test status
Simulation time 405433148 ps
CPU time 5.02 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:29 PM PDT 24
Peak memory 242124 kb
Host smart-1a1025cd-99cc-4b88-bfab-269d515d0de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168465808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1168465808
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.62276805
Short name T147
Test name
Test status
Simulation time 1208600774 ps
CPU time 8.96 seconds
Started Aug 04 05:25:26 PM PDT 24
Finished Aug 04 05:25:35 PM PDT 24
Peak memory 242080 kb
Host smart-f14fc346-5bd2-429e-8968-38a6a412b856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62276805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.62276805
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.291857953
Short name T632
Test name
Test status
Simulation time 1459662105 ps
CPU time 25.5 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:50 PM PDT 24
Peak memory 242344 kb
Host smart-1606fb29-53f4-4c4d-9b36-5e8c109d7a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291857953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.291857953
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.3300747054
Short name T413
Test name
Test status
Simulation time 11110811354 ps
CPU time 28.82 seconds
Started Aug 04 05:25:25 PM PDT 24
Finished Aug 04 05:25:54 PM PDT 24
Peak memory 242008 kb
Host smart-10be3171-f6d0-42fb-bcbe-852635fed7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300747054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.3300747054
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.3856437983
Short name T225
Test name
Test status
Simulation time 480315874 ps
CPU time 12.9 seconds
Started Aug 04 05:25:28 PM PDT 24
Finished Aug 04 05:25:41 PM PDT 24
Peak memory 242032 kb
Host smart-79118686-7f7c-41bb-b9b7-f3de185cbaef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856437983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.3856437983
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.3558876234
Short name T673
Test name
Test status
Simulation time 889156109 ps
CPU time 9.35 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:34 PM PDT 24
Peak memory 248508 kb
Host smart-397818b9-3b5d-4a4d-8bdf-489254eb24b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3558876234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.3558876234
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.3462849372
Short name T1001
Test name
Test status
Simulation time 1616970927 ps
CPU time 11.42 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:36 PM PDT 24
Peak memory 241992 kb
Host smart-2018a1d4-ab1d-43dc-b660-b1d9a13256dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462849372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.3462849372
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.4247901229
Short name T635
Test name
Test status
Simulation time 13408769113 ps
CPU time 121.52 seconds
Started Aug 04 05:25:26 PM PDT 24
Finished Aug 04 05:27:28 PM PDT 24
Peak memory 248548 kb
Host smart-d89c5ac1-cc3e-49bc-b01d-9e84d6dfd9a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247901229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.4247901229
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.2318227878
Short name T1077
Test name
Test status
Simulation time 3995526483 ps
CPU time 6.59 seconds
Started Aug 04 05:25:25 PM PDT 24
Finished Aug 04 05:25:32 PM PDT 24
Peak memory 242136 kb
Host smart-1f7e1160-5dde-475c-b249-05a0dfe55e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318227878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.2318227878
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.3750052260
Short name T494
Test name
Test status
Simulation time 2063157416 ps
CPU time 5.63 seconds
Started Aug 04 05:27:25 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 241880 kb
Host smart-3738da8b-d3ea-4379-ab10-e52c9e17d86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750052260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.3750052260
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.1027559400
Short name T392
Test name
Test status
Simulation time 103216268 ps
CPU time 3.96 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 241992 kb
Host smart-682268ca-e95f-43c0-841d-3ed0db085074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027559400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.1027559400
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.3184844294
Short name T415
Test name
Test status
Simulation time 148115457 ps
CPU time 4.19 seconds
Started Aug 04 05:27:18 PM PDT 24
Finished Aug 04 05:27:22 PM PDT 24
Peak memory 242320 kb
Host smart-dc4d6ab7-5f06-4032-9075-6d9a5cc9a30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184844294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3184844294
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.2625524660
Short name T192
Test name
Test status
Simulation time 350106427 ps
CPU time 4.28 seconds
Started Aug 04 05:27:20 PM PDT 24
Finished Aug 04 05:27:24 PM PDT 24
Peak memory 242172 kb
Host smart-3365798d-b3df-4535-bff5-87a907d2898a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625524660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.2625524660
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.414834487
Short name T414
Test name
Test status
Simulation time 2861355148 ps
CPU time 6.38 seconds
Started Aug 04 05:27:27 PM PDT 24
Finished Aug 04 05:27:33 PM PDT 24
Peak memory 242012 kb
Host smart-44a83e12-0287-4f08-8d1a-5516cd2d8e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414834487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.414834487
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.792923782
Short name T605
Test name
Test status
Simulation time 237938106 ps
CPU time 3.38 seconds
Started Aug 04 05:27:16 PM PDT 24
Finished Aug 04 05:27:19 PM PDT 24
Peak memory 242332 kb
Host smart-9f020b42-848e-4438-bffb-30e50b572dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792923782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.792923782
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.4008819328
Short name T712
Test name
Test status
Simulation time 454774319 ps
CPU time 3.38 seconds
Started Aug 04 05:27:19 PM PDT 24
Finished Aug 04 05:27:23 PM PDT 24
Peak memory 242328 kb
Host smart-d3333a38-be3a-4487-aeab-ad943de4f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008819328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.4008819328
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.3955480028
Short name T646
Test name
Test status
Simulation time 187755908 ps
CPU time 3.67 seconds
Started Aug 04 05:27:18 PM PDT 24
Finished Aug 04 05:27:21 PM PDT 24
Peak memory 242168 kb
Host smart-cf111a88-d9f8-4112-8908-307beca03ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955480028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3955480028
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.1837226439
Short name T779
Test name
Test status
Simulation time 2767770727 ps
CPU time 8.45 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:29 PM PDT 24
Peak memory 242248 kb
Host smart-daa091ef-dde8-4d20-9c76-22e137406741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837226439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1837226439
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.390873634
Short name T73
Test name
Test status
Simulation time 324836413 ps
CPU time 4.2 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:32 PM PDT 24
Peak memory 242380 kb
Host smart-624088d0-9c6e-4713-8e8d-bb33f0c46bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390873634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.390873634
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.2312169620
Short name T678
Test name
Test status
Simulation time 188350134 ps
CPU time 1.85 seconds
Started Aug 04 05:25:30 PM PDT 24
Finished Aug 04 05:25:32 PM PDT 24
Peak memory 240424 kb
Host smart-c648da21-c9eb-4583-abe6-e92b645b27d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312169620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.2312169620
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.4245989805
Short name T76
Test name
Test status
Simulation time 1913795104 ps
CPU time 21.55 seconds
Started Aug 04 05:25:28 PM PDT 24
Finished Aug 04 05:25:50 PM PDT 24
Peak memory 241928 kb
Host smart-8f07fad4-bd66-40b7-8a2d-ec85a14f7267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245989805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.4245989805
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.1665040331
Short name T728
Test name
Test status
Simulation time 809248834 ps
CPU time 17.3 seconds
Started Aug 04 05:25:26 PM PDT 24
Finished Aug 04 05:25:43 PM PDT 24
Peak memory 241976 kb
Host smart-ac20be26-30d2-4f91-864a-c84a5cb799a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665040331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1665040331
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.3283953393
Short name T871
Test name
Test status
Simulation time 3696354210 ps
CPU time 10.09 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:35 PM PDT 24
Peak memory 243164 kb
Host smart-d45130d9-21a9-4af5-8ea4-00656cacbba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283953393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.3283953393
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.2547499662
Short name T10
Test name
Test status
Simulation time 144610278 ps
CPU time 4.52 seconds
Started Aug 04 05:25:30 PM PDT 24
Finished Aug 04 05:25:34 PM PDT 24
Peak memory 241960 kb
Host smart-10c12694-5454-4266-813c-7060c03b4bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547499662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2547499662
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.313357145
Short name T697
Test name
Test status
Simulation time 635088102 ps
CPU time 23.32 seconds
Started Aug 04 05:25:31 PM PDT 24
Finished Aug 04 05:25:55 PM PDT 24
Peak memory 242360 kb
Host smart-618d4a9d-6dc0-41d4-afc3-2b88b433a3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313357145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.313357145
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.208250731
Short name T1030
Test name
Test status
Simulation time 382434450 ps
CPU time 3.48 seconds
Started Aug 04 05:25:24 PM PDT 24
Finished Aug 04 05:25:28 PM PDT 24
Peak memory 242360 kb
Host smart-1eb9888b-fda4-4773-968d-0141d2e416cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208250731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.208250731
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.1878881394
Short name T764
Test name
Test status
Simulation time 2819925304 ps
CPU time 31.2 seconds
Started Aug 04 05:25:28 PM PDT 24
Finished Aug 04 05:25:59 PM PDT 24
Peak memory 241944 kb
Host smart-294dd7f2-c2d1-46d9-9343-b5bd26c287ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878881394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.1878881394
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.3622057636
Short name T1160
Test name
Test status
Simulation time 141210796 ps
CPU time 5.72 seconds
Started Aug 04 05:25:29 PM PDT 24
Finished Aug 04 05:25:35 PM PDT 24
Peak memory 241892 kb
Host smart-d4eff73e-dd78-448d-ad23-b14a865c59e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622057636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3622057636
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.3073157219
Short name T827
Test name
Test status
Simulation time 309748195 ps
CPU time 3.43 seconds
Started Aug 04 05:25:27 PM PDT 24
Finished Aug 04 05:25:31 PM PDT 24
Peak memory 241960 kb
Host smart-9c328c32-a5dc-406c-b917-16fcf870a5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073157219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3073157219
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.3872170602
Short name T296
Test name
Test status
Simulation time 1379589598982 ps
CPU time 2971.82 seconds
Started Aug 04 05:25:30 PM PDT 24
Finished Aug 04 06:15:02 PM PDT 24
Peak memory 441784 kb
Host smart-37a1e40c-a0c6-4154-8fe6-df9d71c672a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872170602 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.3872170602
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.3244501985
Short name T1100
Test name
Test status
Simulation time 963913791 ps
CPU time 20.9 seconds
Started Aug 04 05:25:30 PM PDT 24
Finished Aug 04 05:25:51 PM PDT 24
Peak memory 242500 kb
Host smart-6025f94a-2b07-4c4b-b5db-3b3b75572c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244501985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3244501985
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.3618161799
Short name T194
Test name
Test status
Simulation time 376468719 ps
CPU time 3.99 seconds
Started Aug 04 05:27:22 PM PDT 24
Finished Aug 04 05:27:26 PM PDT 24
Peak memory 241888 kb
Host smart-f20bef22-4a8e-489d-a930-192721b1c3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618161799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3618161799
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.152400750
Short name T739
Test name
Test status
Simulation time 315153855 ps
CPU time 3.88 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 242088 kb
Host smart-438d550e-271d-4237-b5e7-28de42268235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152400750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.152400750
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.658824621
Short name T796
Test name
Test status
Simulation time 300085826 ps
CPU time 4.39 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 242072 kb
Host smart-e623dceb-5e43-4442-a257-89f507b1fddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658824621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.658824621
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.276533533
Short name T793
Test name
Test status
Simulation time 313368030 ps
CPU time 3.54 seconds
Started Aug 04 05:27:20 PM PDT 24
Finished Aug 04 05:27:24 PM PDT 24
Peak memory 241900 kb
Host smart-687d882f-a49a-4a88-bcee-f6f81886216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276533533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.276533533
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.3683697488
Short name T652
Test name
Test status
Simulation time 295530674 ps
CPU time 3.77 seconds
Started Aug 04 05:27:27 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 242244 kb
Host smart-33eccc7d-f805-4540-a483-df76b683e9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683697488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3683697488
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.2013170723
Short name T77
Test name
Test status
Simulation time 762043303 ps
CPU time 4.78 seconds
Started Aug 04 05:27:22 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 241852 kb
Host smart-2064c066-b7e9-4a7d-88e8-807932c9001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013170723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2013170723
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.3628237501
Short name T518
Test name
Test status
Simulation time 448405015 ps
CPU time 3.75 seconds
Started Aug 04 05:27:24 PM PDT 24
Finished Aug 04 05:27:28 PM PDT 24
Peak memory 241860 kb
Host smart-8d95d221-152b-47ba-a556-27d2776d94de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628237501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.3628237501
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.3443479719
Short name T1013
Test name
Test status
Simulation time 207999075 ps
CPU time 3.99 seconds
Started Aug 04 05:27:25 PM PDT 24
Finished Aug 04 05:27:29 PM PDT 24
Peak memory 242220 kb
Host smart-4605ce24-6a64-4e7f-8b7c-18544037f687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443479719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.3443479719
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.2115743766
Short name T699
Test name
Test status
Simulation time 135721988 ps
CPU time 3.81 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:33 PM PDT 24
Peak memory 242224 kb
Host smart-5bfc9ab0-51a6-4e2a-ae0c-0d64fe1c4903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115743766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2115743766
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.1879354493
Short name T856
Test name
Test status
Simulation time 2082357370 ps
CPU time 4.42 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:28 PM PDT 24
Peak memory 241952 kb
Host smart-0eabee5b-f6e8-4238-8ca8-c3a92503b608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879354493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.1879354493
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.1298145156
Short name T750
Test name
Test status
Simulation time 979725869 ps
CPU time 2.29 seconds
Started Aug 04 05:25:29 PM PDT 24
Finished Aug 04 05:25:31 PM PDT 24
Peak memory 240492 kb
Host smart-58d6bb81-b8c2-482c-9967-6351a1ffbaf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298145156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1298145156
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.447313121
Short name T79
Test name
Test status
Simulation time 1125340968 ps
CPU time 10.9 seconds
Started Aug 04 05:25:28 PM PDT 24
Finished Aug 04 05:25:39 PM PDT 24
Peak memory 248484 kb
Host smart-0404e04a-af0b-4404-9ba9-8276e79ef0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447313121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.447313121
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.873422461
Short name T379
Test name
Test status
Simulation time 1187021536 ps
CPU time 19.03 seconds
Started Aug 04 05:25:31 PM PDT 24
Finished Aug 04 05:25:51 PM PDT 24
Peak memory 248464 kb
Host smart-18ccba83-eca6-456f-a06f-9a3c31cd91c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873422461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.873422461
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.4022251111
Short name T803
Test name
Test status
Simulation time 149966623 ps
CPU time 3.8 seconds
Started Aug 04 05:25:28 PM PDT 24
Finished Aug 04 05:25:32 PM PDT 24
Peak memory 242112 kb
Host smart-dc25f53c-5075-4e1c-b7a9-28df86c1be76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022251111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.4022251111
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.1948539469
Short name T187
Test name
Test status
Simulation time 5339756437 ps
CPU time 60.12 seconds
Started Aug 04 05:25:29 PM PDT 24
Finished Aug 04 05:26:29 PM PDT 24
Peak memory 248936 kb
Host smart-a8d28e0b-3f56-4ca3-a85a-a43562547f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948539469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1948539469
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.452303604
Short name T369
Test name
Test status
Simulation time 2033112879 ps
CPU time 7.54 seconds
Started Aug 04 05:25:29 PM PDT 24
Finished Aug 04 05:25:36 PM PDT 24
Peak memory 248416 kb
Host smart-b15c36f5-17e7-4d04-84d4-e914b0d4dbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452303604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.452303604
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1727011671
Short name T805
Test name
Test status
Simulation time 596386818 ps
CPU time 16.5 seconds
Started Aug 04 05:25:30 PM PDT 24
Finished Aug 04 05:25:46 PM PDT 24
Peak memory 241844 kb
Host smart-80e65943-27d8-4b39-85f4-910a112ccfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727011671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1727011671
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.3715026888
Short name T1000
Test name
Test status
Simulation time 724549574 ps
CPU time 24.45 seconds
Started Aug 04 05:25:30 PM PDT 24
Finished Aug 04 05:25:55 PM PDT 24
Peak memory 242116 kb
Host smart-51237634-b8d6-4066-afa4-19a38cf7913b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3715026888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.3715026888
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.932952351
Short name T330
Test name
Test status
Simulation time 192641872 ps
CPU time 4.82 seconds
Started Aug 04 05:25:31 PM PDT 24
Finished Aug 04 05:25:35 PM PDT 24
Peak memory 241984 kb
Host smart-4d69c3f9-c7ba-40e3-87dd-537a54c3f0e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932952351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.932952351
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.1132702461
Short name T445
Test name
Test status
Simulation time 905020907 ps
CPU time 5.25 seconds
Started Aug 04 05:25:28 PM PDT 24
Finished Aug 04 05:25:33 PM PDT 24
Peak memory 241972 kb
Host smart-257651d2-759a-4e4a-8713-d46a853e921f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132702461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1132702461
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.434092468
Short name T945
Test name
Test status
Simulation time 15247658769 ps
CPU time 98.67 seconds
Started Aug 04 05:25:28 PM PDT 24
Finished Aug 04 05:27:06 PM PDT 24
Peak memory 248648 kb
Host smart-5a35b437-265b-4e18-8fdb-05460831c939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434092468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.
434092468
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.2686288170
Short name T1119
Test name
Test status
Simulation time 432686674296 ps
CPU time 1848.46 seconds
Started Aug 04 05:25:30 PM PDT 24
Finished Aug 04 05:56:19 PM PDT 24
Peak memory 409528 kb
Host smart-36e215ae-b8bf-4bae-a038-c21f9e20927d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686288170 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.2686288170
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.3513946755
Short name T519
Test name
Test status
Simulation time 2204775468 ps
CPU time 21.25 seconds
Started Aug 04 05:25:30 PM PDT 24
Finished Aug 04 05:25:51 PM PDT 24
Peak memory 242296 kb
Host smart-e125ef92-8d1a-4cec-8a36-f3025c3b7d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513946755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3513946755
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.327192558
Short name T874
Test name
Test status
Simulation time 229771963 ps
CPU time 4.18 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:33 PM PDT 24
Peak memory 242020 kb
Host smart-f32b3edd-7e4d-4731-9dc7-05555070a71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327192558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.327192558
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.721396068
Short name T974
Test name
Test status
Simulation time 579684914 ps
CPU time 5.37 seconds
Started Aug 04 05:27:24 PM PDT 24
Finished Aug 04 05:27:30 PM PDT 24
Peak memory 241876 kb
Host smart-0e2318e5-505c-4fc7-836a-c933184f01ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721396068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.721396068
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.603352108
Short name T882
Test name
Test status
Simulation time 441482501 ps
CPU time 4.97 seconds
Started Aug 04 05:27:27 PM PDT 24
Finished Aug 04 05:27:33 PM PDT 24
Peak memory 241848 kb
Host smart-98f95c30-67b4-47fc-9f7a-38be0922489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603352108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.603352108
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.3130776788
Short name T502
Test name
Test status
Simulation time 1587865579 ps
CPU time 5.82 seconds
Started Aug 04 05:27:21 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 242168 kb
Host smart-12620eaf-cf15-434d-aff9-afc920a0b48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130776788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.3130776788
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.1074237189
Short name T808
Test name
Test status
Simulation time 130662701 ps
CPU time 4.54 seconds
Started Aug 04 05:27:25 PM PDT 24
Finished Aug 04 05:27:29 PM PDT 24
Peak memory 241840 kb
Host smart-3d94a082-55d9-4453-a7c8-6f8b4003e7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074237189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.1074237189
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.2861661404
Short name T202
Test name
Test status
Simulation time 191027810 ps
CPU time 3.28 seconds
Started Aug 04 05:27:31 PM PDT 24
Finished Aug 04 05:27:34 PM PDT 24
Peak memory 242096 kb
Host smart-fe7aadc8-d25a-4570-8a6b-5bd191bc6c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861661404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2861661404
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.397157087
Short name T442
Test name
Test status
Simulation time 505982262 ps
CPU time 4.17 seconds
Started Aug 04 05:27:22 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 241964 kb
Host smart-d968dbb1-1ca0-4330-9af6-f6541191fc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397157087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.397157087
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.2994030265
Short name T1045
Test name
Test status
Simulation time 183639329 ps
CPU time 4.8 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:28 PM PDT 24
Peak memory 241988 kb
Host smart-b544053c-470f-46c7-9ebb-7fc5f335a614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994030265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2994030265
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.3526124176
Short name T867
Test name
Test status
Simulation time 120933623 ps
CPU time 4.2 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:33 PM PDT 24
Peak memory 242008 kb
Host smart-2d4cfd22-8fb2-4ab4-b5ae-0bdc3fb9661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526124176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3526124176
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.3713463356
Short name T647
Test name
Test status
Simulation time 56590071 ps
CPU time 1.89 seconds
Started Aug 04 05:25:33 PM PDT 24
Finished Aug 04 05:25:35 PM PDT 24
Peak memory 240828 kb
Host smart-96d20aca-da63-4073-9507-c5b42fb3ddc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713463356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.3713463356
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.913706936
Short name T114
Test name
Test status
Simulation time 1302911919 ps
CPU time 11.26 seconds
Started Aug 04 05:25:34 PM PDT 24
Finished Aug 04 05:25:45 PM PDT 24
Peak memory 248516 kb
Host smart-82b52332-34e9-47c6-8e76-94a6beaa4eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913706936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.913706936
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.2247316584
Short name T412
Test name
Test status
Simulation time 1429039766 ps
CPU time 26.91 seconds
Started Aug 04 05:25:31 PM PDT 24
Finished Aug 04 05:25:58 PM PDT 24
Peak memory 241956 kb
Host smart-65ec379b-2f92-41ce-bfc4-25dd466aa825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247316584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2247316584
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.4096772908
Short name T1027
Test name
Test status
Simulation time 835510198 ps
CPU time 14.21 seconds
Started Aug 04 05:25:32 PM PDT 24
Finished Aug 04 05:25:46 PM PDT 24
Peak memory 242372 kb
Host smart-46f27681-0194-4472-be90-b8ca243ab666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096772908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.4096772908
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.3489933080
Short name T1061
Test name
Test status
Simulation time 332908723 ps
CPU time 4.56 seconds
Started Aug 04 05:25:31 PM PDT 24
Finished Aug 04 05:25:36 PM PDT 24
Peak memory 242064 kb
Host smart-a18d8322-e88d-4b73-a94e-d3f9881c0755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489933080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3489933080
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.1519852697
Short name T720
Test name
Test status
Simulation time 436328785 ps
CPU time 12.56 seconds
Started Aug 04 05:25:31 PM PDT 24
Finished Aug 04 05:25:43 PM PDT 24
Peak memory 242304 kb
Host smart-fb28423b-7672-4638-9d79-3b3d72369b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519852697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.1519852697
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.4089804007
Short name T559
Test name
Test status
Simulation time 1283988870 ps
CPU time 10.76 seconds
Started Aug 04 05:25:32 PM PDT 24
Finished Aug 04 05:25:43 PM PDT 24
Peak memory 248500 kb
Host smart-e352e0d2-a075-4d8a-8fc3-2c96d7164acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089804007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.4089804007
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2634981572
Short name T800
Test name
Test status
Simulation time 2157037537 ps
CPU time 6.77 seconds
Started Aug 04 05:25:33 PM PDT 24
Finished Aug 04 05:25:40 PM PDT 24
Peak memory 242140 kb
Host smart-3b2b3309-4b23-46ee-a6c1-1a7b56f39f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634981572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2634981572
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.661338235
Short name T916
Test name
Test status
Simulation time 151737326 ps
CPU time 3.97 seconds
Started Aug 04 05:25:34 PM PDT 24
Finished Aug 04 05:25:38 PM PDT 24
Peak memory 248156 kb
Host smart-b2ba8698-260c-47be-a394-dcc5aeaf9360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661338235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.661338235
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.2823567237
Short name T725
Test name
Test status
Simulation time 320612797 ps
CPU time 3.81 seconds
Started Aug 04 05:25:32 PM PDT 24
Finished Aug 04 05:25:36 PM PDT 24
Peak memory 248392 kb
Host smart-399d4bd8-1cb2-4708-8a8a-3763919afb9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823567237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2823567237
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.1971888567
Short name T1038
Test name
Test status
Simulation time 1612377599 ps
CPU time 8.51 seconds
Started Aug 04 05:25:32 PM PDT 24
Finished Aug 04 05:25:41 PM PDT 24
Peak memory 242104 kb
Host smart-df80c376-5d94-4233-88cd-779d0c50d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971888567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1971888567
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.4082897953
Short name T362
Test name
Test status
Simulation time 135710161997 ps
CPU time 1008.92 seconds
Started Aug 04 05:25:31 PM PDT 24
Finished Aug 04 05:42:20 PM PDT 24
Peak memory 346608 kb
Host smart-716a5501-b505-4ddf-8c99-58033c3d1a52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082897953 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.4082897953
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.3860992327
Short name T895
Test name
Test status
Simulation time 9908524699 ps
CPU time 26.49 seconds
Started Aug 04 05:25:35 PM PDT 24
Finished Aug 04 05:26:01 PM PDT 24
Peak memory 248716 kb
Host smart-eceba942-cbdd-4696-afed-2c9778b43779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860992327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.3860992327
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.1878460411
Short name T1109
Test name
Test status
Simulation time 2026971454 ps
CPU time 3.79 seconds
Started Aug 04 05:27:22 PM PDT 24
Finished Aug 04 05:27:26 PM PDT 24
Peak memory 241896 kb
Host smart-251b544c-903c-42a5-b7f8-0828964acefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878460411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1878460411
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.3437112618
Short name T976
Test name
Test status
Simulation time 173589536 ps
CPU time 3.29 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:26 PM PDT 24
Peak memory 242204 kb
Host smart-2f356d04-8669-4939-9bb4-02fe419af777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437112618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.3437112618
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.1241050518
Short name T819
Test name
Test status
Simulation time 115920993 ps
CPU time 3.14 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:32 PM PDT 24
Peak memory 241976 kb
Host smart-ad957eed-dc48-4e9b-8cef-c01cc6fd1448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241050518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.1241050518
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.1944874423
Short name T1128
Test name
Test status
Simulation time 120747182 ps
CPU time 4.35 seconds
Started Aug 04 05:27:24 PM PDT 24
Finished Aug 04 05:27:29 PM PDT 24
Peak memory 241984 kb
Host smart-05fd7299-4404-46b7-8688-f4cc2454dbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944874423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1944874423
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.2417492178
Short name T615
Test name
Test status
Simulation time 103511709 ps
CPU time 4.29 seconds
Started Aug 04 05:27:27 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 242100 kb
Host smart-ba984259-6736-4481-a9e7-18b6f2441058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417492178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2417492178
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.2001574330
Short name T840
Test name
Test status
Simulation time 171237357 ps
CPU time 3.64 seconds
Started Aug 04 05:27:26 PM PDT 24
Finished Aug 04 05:27:29 PM PDT 24
Peak memory 241900 kb
Host smart-66644cbf-23d6-40a5-97fa-32fba59985e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001574330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.2001574330
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.1934373344
Short name T205
Test name
Test status
Simulation time 309971505 ps
CPU time 3.6 seconds
Started Aug 04 05:27:27 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 241988 kb
Host smart-ed98ebec-a325-4a7b-b535-3ebbf85b9864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934373344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.1934373344
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.2227722832
Short name T1033
Test name
Test status
Simulation time 2022121053 ps
CPU time 5.24 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:28 PM PDT 24
Peak memory 242128 kb
Host smart-d2ad0278-c0a9-4568-867d-c37310f08858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227722832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.2227722832
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.2208525198
Short name T931
Test name
Test status
Simulation time 154058499 ps
CPU time 1.73 seconds
Started Aug 04 05:25:41 PM PDT 24
Finished Aug 04 05:25:43 PM PDT 24
Peak memory 240424 kb
Host smart-b2d614e7-34cb-4a2d-9381-c5f259372ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208525198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2208525198
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.321022255
Short name T27
Test name
Test status
Simulation time 2286071715 ps
CPU time 23.96 seconds
Started Aug 04 05:25:33 PM PDT 24
Finished Aug 04 05:25:57 PM PDT 24
Peak memory 242616 kb
Host smart-c2dc0e5a-8c7b-4a90-b5af-fac2e36d1a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321022255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.321022255
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.329034102
Short name T501
Test name
Test status
Simulation time 2856529663 ps
CPU time 22.08 seconds
Started Aug 04 05:25:32 PM PDT 24
Finished Aug 04 05:25:54 PM PDT 24
Peak memory 242428 kb
Host smart-a0edc4c9-bb6d-4750-9fde-31b2ec20f301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329034102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.329034102
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.3248670898
Short name T658
Test name
Test status
Simulation time 664946185 ps
CPU time 25.85 seconds
Started Aug 04 05:25:32 PM PDT 24
Finished Aug 04 05:25:58 PM PDT 24
Peak memory 242284 kb
Host smart-1339d3e2-b24e-46fc-a7b1-b8af4d5eea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248670898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.3248670898
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.4217909638
Short name T614
Test name
Test status
Simulation time 637862325 ps
CPU time 4.84 seconds
Started Aug 04 05:25:32 PM PDT 24
Finished Aug 04 05:25:37 PM PDT 24
Peak memory 242244 kb
Host smart-795be954-d4f1-4b05-9deb-0d7e0f4e6ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217909638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.4217909638
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.3555671077
Short name T971
Test name
Test status
Simulation time 1206300524 ps
CPU time 12.63 seconds
Started Aug 04 05:25:37 PM PDT 24
Finished Aug 04 05:25:50 PM PDT 24
Peak memory 243696 kb
Host smart-09ef161e-1f7f-4ad5-9a88-73ffae5afedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555671077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.3555671077
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.1160660429
Short name T966
Test name
Test status
Simulation time 444263711 ps
CPU time 6.48 seconds
Started Aug 04 05:25:37 PM PDT 24
Finished Aug 04 05:25:43 PM PDT 24
Peak memory 247540 kb
Host smart-744a288d-ad64-4943-8796-0fb03a666a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160660429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1160660429
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.1526526295
Short name T748
Test name
Test status
Simulation time 844012884 ps
CPU time 15.35 seconds
Started Aug 04 05:25:34 PM PDT 24
Finished Aug 04 05:25:49 PM PDT 24
Peak memory 241828 kb
Host smart-fad0d442-a84a-4899-934e-f8442342353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526526295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.1526526295
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.3174480089
Short name T650
Test name
Test status
Simulation time 328990427 ps
CPU time 8.84 seconds
Started Aug 04 05:25:32 PM PDT 24
Finished Aug 04 05:25:41 PM PDT 24
Peak memory 248628 kb
Host smart-bcd43d0c-cfa6-48c2-a14d-48500c5ce785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3174480089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3174480089
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.167326258
Short name T322
Test name
Test status
Simulation time 263383783 ps
CPU time 4.57 seconds
Started Aug 04 05:25:42 PM PDT 24
Finished Aug 04 05:25:46 PM PDT 24
Peak memory 242068 kb
Host smart-8344e465-575d-4f2d-adfb-c843e8d240e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167326258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.167326258
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.1621186593
Short name T661
Test name
Test status
Simulation time 443850666 ps
CPU time 7.93 seconds
Started Aug 04 05:25:33 PM PDT 24
Finished Aug 04 05:25:41 PM PDT 24
Peak memory 242100 kb
Host smart-8c574fd6-6b24-4def-a69c-0e2c1a82f8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621186593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.1621186593
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.149007071
Short name T961
Test name
Test status
Simulation time 500852572 ps
CPU time 5.24 seconds
Started Aug 04 05:25:42 PM PDT 24
Finished Aug 04 05:25:47 PM PDT 24
Peak memory 242312 kb
Host smart-df602e3d-b354-4366-a2ed-30d78ad128ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149007071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.149007071
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2041836592
Short name T84
Test name
Test status
Simulation time 382852779 ps
CPU time 4.4 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 241980 kb
Host smart-853e0f1e-6f0e-4e7a-b89f-20876a73e6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041836592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2041836592
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.189228796
Short name T839
Test name
Test status
Simulation time 534765172 ps
CPU time 4.47 seconds
Started Aug 04 05:27:26 PM PDT 24
Finished Aug 04 05:27:30 PM PDT 24
Peak memory 242020 kb
Host smart-22436e67-ce04-49a8-ab84-20235c7dc8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189228796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.189228796
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.355177300
Short name T686
Test name
Test status
Simulation time 370690365 ps
CPU time 4.34 seconds
Started Aug 04 05:27:36 PM PDT 24
Finished Aug 04 05:27:41 PM PDT 24
Peak memory 242208 kb
Host smart-075efdb6-d5e0-440b-9474-12e52486f76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355177300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.355177300
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2378241073
Short name T171
Test name
Test status
Simulation time 370008928 ps
CPU time 4.6 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:32 PM PDT 24
Peak memory 242260 kb
Host smart-e83acc8d-efd9-460d-bcae-f19b207ef656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378241073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2378241073
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.721840216
Short name T1037
Test name
Test status
Simulation time 113514583 ps
CPU time 3.29 seconds
Started Aug 04 05:27:40 PM PDT 24
Finished Aug 04 05:27:44 PM PDT 24
Peak memory 242180 kb
Host smart-37d9704d-c3b9-4e28-b33a-33a0cd5902c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721840216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.721840216
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.3306254019
Short name T1157
Test name
Test status
Simulation time 246541040 ps
CPU time 4 seconds
Started Aug 04 05:27:23 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 242356 kb
Host smart-bd0b8234-899a-4400-977d-83f59167c51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306254019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.3306254019
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.1086241279
Short name T120
Test name
Test status
Simulation time 462441061 ps
CPU time 4.73 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:33 PM PDT 24
Peak memory 242396 kb
Host smart-815c4232-999a-4521-8806-0f436d561ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086241279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1086241279
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.2596249049
Short name T46
Test name
Test status
Simulation time 149802288 ps
CPU time 4.04 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:32 PM PDT 24
Peak memory 242180 kb
Host smart-203a5704-ac15-44af-b50b-ca41c2d9d89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596249049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.2596249049
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.832693433
Short name T470
Test name
Test status
Simulation time 1920083161 ps
CPU time 5.74 seconds
Started Aug 04 05:27:35 PM PDT 24
Finished Aug 04 05:27:41 PM PDT 24
Peak memory 241952 kb
Host smart-22be3e75-8dd2-4eac-b239-a63da17b3241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832693433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.832693433
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.2578409628
Short name T954
Test name
Test status
Simulation time 120235327 ps
CPU time 2.06 seconds
Started Aug 04 05:25:53 PM PDT 24
Finished Aug 04 05:25:55 PM PDT 24
Peak memory 240480 kb
Host smart-d164def5-f6a1-4de2-9f87-44126e953bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578409628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2578409628
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.4106069330
Short name T89
Test name
Test status
Simulation time 5945921674 ps
CPU time 12.41 seconds
Started Aug 04 05:25:37 PM PDT 24
Finished Aug 04 05:25:50 PM PDT 24
Peak memory 243172 kb
Host smart-17936f45-6e2a-4a7c-bbbd-866aae7be458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106069330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.4106069330
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.3551817442
Short name T421
Test name
Test status
Simulation time 642640300 ps
CPU time 16.31 seconds
Started Aug 04 05:25:44 PM PDT 24
Finished Aug 04 05:26:00 PM PDT 24
Peak memory 241824 kb
Host smart-9d742122-50e6-43a5-a9f8-bf4700150c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551817442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.3551817442
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.4108456944
Short name T576
Test name
Test status
Simulation time 11653864605 ps
CPU time 26.09 seconds
Started Aug 04 05:25:37 PM PDT 24
Finished Aug 04 05:26:03 PM PDT 24
Peak memory 242240 kb
Host smart-afe193e7-d488-488b-a3ce-62ec864100ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108456944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.4108456944
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.1890520046
Short name T815
Test name
Test status
Simulation time 107208803 ps
CPU time 3.98 seconds
Started Aug 04 05:25:37 PM PDT 24
Finished Aug 04 05:25:41 PM PDT 24
Peak memory 242256 kb
Host smart-6d73aaf6-9bfd-43ac-8434-e48a991d6daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890520046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1890520046
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.3219353256
Short name T1167
Test name
Test status
Simulation time 1215843141 ps
CPU time 25.04 seconds
Started Aug 04 05:25:42 PM PDT 24
Finished Aug 04 05:26:07 PM PDT 24
Peak memory 242716 kb
Host smart-9b73764a-f475-4787-b67e-f3c51bb803fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219353256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.3219353256
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.3212007986
Short name T488
Test name
Test status
Simulation time 12497354865 ps
CPU time 22.36 seconds
Started Aug 04 05:25:37 PM PDT 24
Finished Aug 04 05:26:00 PM PDT 24
Peak memory 243108 kb
Host smart-6275ea7c-0026-4be8-95aa-399d8a223c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212007986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.3212007986
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.1799372326
Short name T298
Test name
Test status
Simulation time 262824189 ps
CPU time 2.97 seconds
Started Aug 04 05:25:36 PM PDT 24
Finished Aug 04 05:25:39 PM PDT 24
Peak memory 242432 kb
Host smart-2fc6616e-a89f-473b-9180-38e1e3d8c7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799372326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.1799372326
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.3052858514
Short name T987
Test name
Test status
Simulation time 5888579661 ps
CPU time 14.8 seconds
Started Aug 04 05:25:39 PM PDT 24
Finished Aug 04 05:25:54 PM PDT 24
Peak memory 242248 kb
Host smart-2827ab50-d9db-4a15-a225-8179d26d03fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052858514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.3052858514
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.530344564
Short name T327
Test name
Test status
Simulation time 255351669 ps
CPU time 8.19 seconds
Started Aug 04 05:25:37 PM PDT 24
Finished Aug 04 05:25:45 PM PDT 24
Peak memory 242292 kb
Host smart-6d2d3ade-7fcc-4b43-b0fd-568005ce1996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530344564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.530344564
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.1603966446
Short name T443
Test name
Test status
Simulation time 3245921909 ps
CPU time 7.21 seconds
Started Aug 04 05:25:40 PM PDT 24
Finished Aug 04 05:25:48 PM PDT 24
Peak memory 248644 kb
Host smart-3a9e8139-d62b-49c5-b5ee-6af89812e835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603966446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.1603966446
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.3569754508
Short name T1017
Test name
Test status
Simulation time 225086441693 ps
CPU time 272.78 seconds
Started Aug 04 05:25:39 PM PDT 24
Finished Aug 04 05:30:12 PM PDT 24
Peak memory 294088 kb
Host smart-aa1035fd-06cc-4dbf-b471-8778b2fec70a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569754508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.3569754508
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.4158915773
Short name T347
Test name
Test status
Simulation time 14058071830 ps
CPU time 32.42 seconds
Started Aug 04 05:25:39 PM PDT 24
Finished Aug 04 05:26:11 PM PDT 24
Peak memory 243228 kb
Host smart-6102963c-37dd-466e-83e8-92b55e3b9fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158915773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.4158915773
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.3415047386
Short name T824
Test name
Test status
Simulation time 223221754 ps
CPU time 3.5 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:33 PM PDT 24
Peak memory 242144 kb
Host smart-bb1538af-888b-4688-8e06-41a24c9f5b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415047386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.3415047386
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.1119216708
Short name T674
Test name
Test status
Simulation time 140991969 ps
CPU time 3.3 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:32 PM PDT 24
Peak memory 242340 kb
Host smart-89e8ce03-273e-4d81-be17-407a58ddd523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119216708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1119216708
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.789331558
Short name T735
Test name
Test status
Simulation time 2273162101 ps
CPU time 6.4 seconds
Started Aug 04 05:27:40 PM PDT 24
Finished Aug 04 05:27:47 PM PDT 24
Peak memory 241996 kb
Host smart-7b715898-8b74-4696-9879-5db79e94190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789331558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.789331558
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.999027694
Short name T561
Test name
Test status
Simulation time 148932530 ps
CPU time 5.02 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:33 PM PDT 24
Peak memory 242168 kb
Host smart-ac451cc8-6585-4d5c-bf8a-842ca06cc27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999027694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.999027694
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.1365260029
Short name T698
Test name
Test status
Simulation time 537241907 ps
CPU time 4.51 seconds
Started Aug 04 05:27:27 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 241972 kb
Host smart-d1a53b3f-b3ca-4768-b63e-eb9f6df2350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365260029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1365260029
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.2743076938
Short name T1118
Test name
Test status
Simulation time 114240706 ps
CPU time 3.31 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 242360 kb
Host smart-6428493d-aaa0-4dab-b560-8a0b121bde1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743076938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2743076938
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.433665713
Short name T58
Test name
Test status
Simulation time 2526192640 ps
CPU time 4.56 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 242412 kb
Host smart-fd560689-e331-4cb1-9da3-e0b4f01c4185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433665713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.433665713
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.3733807469
Short name T855
Test name
Test status
Simulation time 412625647 ps
CPU time 4.13 seconds
Started Aug 04 05:27:38 PM PDT 24
Finished Aug 04 05:27:42 PM PDT 24
Peak memory 242228 kb
Host smart-fe649b4a-0f59-4699-ba8f-cae2a75682cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733807469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3733807469
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.4274926440
Short name T403
Test name
Test status
Simulation time 60710943 ps
CPU time 1.9 seconds
Started Aug 04 05:25:42 PM PDT 24
Finished Aug 04 05:25:43 PM PDT 24
Peak memory 240592 kb
Host smart-959e3688-ae88-48dd-bdc3-143551d42fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274926440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.4274926440
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.798629903
Short name T115
Test name
Test status
Simulation time 152670729 ps
CPU time 4.29 seconds
Started Aug 04 05:25:42 PM PDT 24
Finished Aug 04 05:25:46 PM PDT 24
Peak memory 248536 kb
Host smart-56192aee-06bc-42f3-8d75-01456bfd7210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798629903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.798629903
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.1372420311
Short name T622
Test name
Test status
Simulation time 730813835 ps
CPU time 23.96 seconds
Started Aug 04 05:25:40 PM PDT 24
Finished Aug 04 05:26:04 PM PDT 24
Peak memory 241952 kb
Host smart-d5e16747-495a-4011-b0e2-471a13285ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372420311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1372420311
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.3096521354
Short name T487
Test name
Test status
Simulation time 748591192 ps
CPU time 14.55 seconds
Started Aug 04 05:25:37 PM PDT 24
Finished Aug 04 05:25:52 PM PDT 24
Peak memory 241924 kb
Host smart-39bb2a85-7eb1-4d76-be15-952958217989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096521354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.3096521354
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.1343486854
Short name T1052
Test name
Test status
Simulation time 1357572857 ps
CPU time 3.98 seconds
Started Aug 04 05:25:38 PM PDT 24
Finished Aug 04 05:25:42 PM PDT 24
Peak memory 241996 kb
Host smart-6979ee84-d09b-4fdc-a512-6832b36d798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343486854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.1343486854
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.2367370889
Short name T186
Test name
Test status
Simulation time 3514394834 ps
CPU time 18.84 seconds
Started Aug 04 05:25:50 PM PDT 24
Finished Aug 04 05:26:09 PM PDT 24
Peak memory 242432 kb
Host smart-12426127-b126-40fb-a880-ad193759e0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367370889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.2367370889
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.607813395
Short name T939
Test name
Test status
Simulation time 1944326092 ps
CPU time 22.07 seconds
Started Aug 04 05:25:41 PM PDT 24
Finished Aug 04 05:26:03 PM PDT 24
Peak memory 242492 kb
Host smart-3139cbc4-ae93-464f-bbd5-e8e6ba0276e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607813395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.607813395
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.1036193763
Short name T1007
Test name
Test status
Simulation time 636141477 ps
CPU time 5.36 seconds
Started Aug 04 05:25:38 PM PDT 24
Finished Aug 04 05:25:43 PM PDT 24
Peak memory 241860 kb
Host smart-0b4cd41f-0036-4b0b-aea4-a70eb4a2f1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036193763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1036193763
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.1838950763
Short name T549
Test name
Test status
Simulation time 4144121824 ps
CPU time 7.82 seconds
Started Aug 04 05:25:38 PM PDT 24
Finished Aug 04 05:25:46 PM PDT 24
Peak memory 242232 kb
Host smart-ba3e7132-5d8e-407c-bf7e-b83df4fe87ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838950763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.1838950763
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.1499094374
Short name T1152
Test name
Test status
Simulation time 143873744 ps
CPU time 4.41 seconds
Started Aug 04 05:25:44 PM PDT 24
Finished Aug 04 05:25:48 PM PDT 24
Peak memory 242068 kb
Host smart-87267982-a9a6-4497-ba9a-e9d1539cefa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499094374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.1499094374
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.2594742605
Short name T996
Test name
Test status
Simulation time 399800567 ps
CPU time 5.1 seconds
Started Aug 04 05:25:38 PM PDT 24
Finished Aug 04 05:25:43 PM PDT 24
Peak memory 241896 kb
Host smart-721c07e3-93b0-4acb-b641-61606e17e2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594742605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.2594742605
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.2147653798
Short name T1097
Test name
Test status
Simulation time 9058815415 ps
CPU time 132.26 seconds
Started Aug 04 05:25:46 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 250008 kb
Host smart-b3518a03-dbeb-4625-a9f1-282de976c5d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147653798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.2147653798
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.3138431889
Short name T547
Test name
Test status
Simulation time 63610354813 ps
CPU time 280.06 seconds
Started Aug 04 05:25:40 PM PDT 24
Finished Aug 04 05:30:20 PM PDT 24
Peak memory 265584 kb
Host smart-7a08e2d6-7f1f-47ca-a5ee-6562f4fa2ed0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138431889 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.3138431889
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.432504007
Short name T880
Test name
Test status
Simulation time 2532681430 ps
CPU time 29.24 seconds
Started Aug 04 05:25:45 PM PDT 24
Finished Aug 04 05:26:14 PM PDT 24
Peak memory 241972 kb
Host smart-7e297c80-95ee-41a5-841a-dfe763f11af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432504007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.432504007
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.2409002769
Short name T1068
Test name
Test status
Simulation time 199276969 ps
CPU time 4.69 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:32 PM PDT 24
Peak memory 242052 kb
Host smart-3cf5d1c1-207a-4035-931b-0a4702ef5793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409002769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.2409002769
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.4158782630
Short name T1021
Test name
Test status
Simulation time 127129554 ps
CPU time 3.61 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:32 PM PDT 24
Peak memory 242236 kb
Host smart-5173864d-79ba-4876-a56c-9089efd000eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158782630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.4158782630
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.811203787
Short name T28
Test name
Test status
Simulation time 1664710607 ps
CPU time 4.3 seconds
Started Aug 04 05:27:26 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 242156 kb
Host smart-765029dc-5798-4d8a-9054-2dfb2b34535c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811203787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.811203787
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.2642827849
Short name T1004
Test name
Test status
Simulation time 137168656 ps
CPU time 3.81 seconds
Started Aug 04 05:27:26 PM PDT 24
Finished Aug 04 05:27:30 PM PDT 24
Peak memory 242248 kb
Host smart-057d0c1e-9d65-4d0d-a9e4-1082e95ef895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642827849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.2642827849
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.1351980395
Short name T469
Test name
Test status
Simulation time 561456648 ps
CPU time 4.43 seconds
Started Aug 04 05:27:27 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 241844 kb
Host smart-69414635-2323-40ef-bb18-57c4517228a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351980395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1351980395
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.617652759
Short name T757
Test name
Test status
Simulation time 103241558 ps
CPU time 2.97 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:49 PM PDT 24
Peak memory 242136 kb
Host smart-1629c595-49b2-4b9f-9858-c19b9f12ce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617652759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.617652759
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.2131753840
Short name T752
Test name
Test status
Simulation time 208064312 ps
CPU time 3.69 seconds
Started Aug 04 05:27:32 PM PDT 24
Finished Aug 04 05:27:35 PM PDT 24
Peak memory 242380 kb
Host smart-22c25df1-2d56-4547-aa26-9b78de2f3971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131753840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.2131753840
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.1598381198
Short name T1003
Test name
Test status
Simulation time 204487968 ps
CPU time 3.28 seconds
Started Aug 04 05:27:41 PM PDT 24
Finished Aug 04 05:27:44 PM PDT 24
Peak memory 242032 kb
Host smart-ced38841-98c1-48eb-ac9b-8cf5de76b533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598381198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1598381198
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.2221295865
Short name T57
Test name
Test status
Simulation time 342211401 ps
CPU time 4.27 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:34 PM PDT 24
Peak memory 242188 kb
Host smart-1c49ee17-fac4-4d33-aade-46209fe14b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221295865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2221295865
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.909057272
Short name T731
Test name
Test status
Simulation time 472620610 ps
CPU time 4.06 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:32 PM PDT 24
Peak memory 242156 kb
Host smart-45f6b7d7-a867-435c-8b1b-e51a8bc3eab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909057272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.909057272
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.4287587538
Short name T380
Test name
Test status
Simulation time 168342966 ps
CPU time 1.69 seconds
Started Aug 04 05:25:42 PM PDT 24
Finished Aug 04 05:25:43 PM PDT 24
Peak memory 240864 kb
Host smart-eef2f770-c4f4-4477-88f0-420ff37f1936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287587538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.4287587538
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.2362051013
Short name T663
Test name
Test status
Simulation time 19186167602 ps
CPU time 41.63 seconds
Started Aug 04 05:25:39 PM PDT 24
Finished Aug 04 05:26:21 PM PDT 24
Peak memory 245716 kb
Host smart-2a5f119e-d7b3-4652-b621-55d182d6441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362051013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.2362051013
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.3271188865
Short name T812
Test name
Test status
Simulation time 1411123449 ps
CPU time 24.78 seconds
Started Aug 04 05:25:42 PM PDT 24
Finished Aug 04 05:26:07 PM PDT 24
Peak memory 242796 kb
Host smart-11506442-af7f-4709-b5aa-f9296394224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271188865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3271188865
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.3977245950
Short name T670
Test name
Test status
Simulation time 3705005698 ps
CPU time 32.62 seconds
Started Aug 04 05:25:44 PM PDT 24
Finished Aug 04 05:26:16 PM PDT 24
Peak memory 242076 kb
Host smart-a9d46cb4-81a6-4bb8-a385-414c0ad4a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977245950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3977245950
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.3964072514
Short name T952
Test name
Test status
Simulation time 555750951 ps
CPU time 5.93 seconds
Started Aug 04 05:25:39 PM PDT 24
Finished Aug 04 05:25:45 PM PDT 24
Peak memory 242180 kb
Host smart-6bf12d00-8f5b-4dde-8208-434c7f09e1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964072514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3964072514
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.2288526243
Short name T536
Test name
Test status
Simulation time 8672833403 ps
CPU time 15.6 seconds
Started Aug 04 05:25:50 PM PDT 24
Finished Aug 04 05:26:06 PM PDT 24
Peak memory 243048 kb
Host smart-bdf94b9a-3dcc-4ee1-9d3e-125c51d87e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288526243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.2288526243
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.1232386310
Short name T929
Test name
Test status
Simulation time 382739458 ps
CPU time 14.41 seconds
Started Aug 04 05:25:41 PM PDT 24
Finished Aug 04 05:25:55 PM PDT 24
Peak memory 241952 kb
Host smart-5da4b58d-def9-4099-9b92-ec0792b923e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232386310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.1232386310
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.2931577005
Short name T564
Test name
Test status
Simulation time 160964646 ps
CPU time 4.58 seconds
Started Aug 04 05:25:50 PM PDT 24
Finished Aug 04 05:25:55 PM PDT 24
Peak memory 242384 kb
Host smart-aaa45c9b-e823-4e02-963d-17c529ecf4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931577005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2931577005
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.1446205583
Short name T522
Test name
Test status
Simulation time 1122366729 ps
CPU time 16.34 seconds
Started Aug 04 05:25:45 PM PDT 24
Finished Aug 04 05:26:02 PM PDT 24
Peak memory 242004 kb
Host smart-b218aa41-283a-44dd-b4bf-54c88b6b494d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446205583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1446205583
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.575038595
Short name T1172
Test name
Test status
Simulation time 568608571 ps
CPU time 7.92 seconds
Started Aug 04 05:25:44 PM PDT 24
Finished Aug 04 05:25:52 PM PDT 24
Peak memory 248432 kb
Host smart-ea80e381-5681-44a3-b09f-be0afa444208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575038595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.575038595
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.2729317834
Short name T210
Test name
Test status
Simulation time 607002729 ps
CPU time 5.62 seconds
Started Aug 04 05:25:39 PM PDT 24
Finished Aug 04 05:25:45 PM PDT 24
Peak memory 242396 kb
Host smart-028dcfbd-d83b-4835-85b6-932c20f0e652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729317834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2729317834
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.2525470897
Short name T787
Test name
Test status
Simulation time 15922546879 ps
CPU time 144.23 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:28:14 PM PDT 24
Peak memory 248696 kb
Host smart-8fd8b222-9a46-45be-82b6-ba5d7c1d4285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525470897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.2525470897
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.1810943989
Short name T660
Test name
Test status
Simulation time 20562125556 ps
CPU time 525.24 seconds
Started Aug 04 05:25:40 PM PDT 24
Finished Aug 04 05:34:25 PM PDT 24
Peak memory 257712 kb
Host smart-5c97a254-23e5-4243-a8a0-b798dc20381e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810943989 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.1810943989
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.883841439
Short name T604
Test name
Test status
Simulation time 2622541417 ps
CPU time 19.57 seconds
Started Aug 04 05:25:40 PM PDT 24
Finished Aug 04 05:25:59 PM PDT 24
Peak memory 242244 kb
Host smart-279c7510-6ba9-4cd2-9f65-1dd3d76b07f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883841439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.883841439
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.166339458
Short name T113
Test name
Test status
Simulation time 2501143378 ps
CPU time 6.03 seconds
Started Aug 04 05:27:25 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 242040 kb
Host smart-36e56676-c579-4fd1-824d-9f43d2091390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166339458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.166339458
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.3097600376
Short name T53
Test name
Test status
Simulation time 120930160 ps
CPU time 4.21 seconds
Started Aug 04 05:27:25 PM PDT 24
Finished Aug 04 05:27:30 PM PDT 24
Peak memory 242292 kb
Host smart-4b897841-ad4e-4525-a8e6-33aed591c5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097600376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3097600376
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.1666450927
Short name T785
Test name
Test status
Simulation time 399129890 ps
CPU time 3.7 seconds
Started Aug 04 05:27:28 PM PDT 24
Finished Aug 04 05:27:31 PM PDT 24
Peak memory 242000 kb
Host smart-bfbdbf8a-ce64-4a9a-9f54-c77a3b178ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666450927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1666450927
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.3962589179
Short name T806
Test name
Test status
Simulation time 540145843 ps
CPU time 5.31 seconds
Started Aug 04 05:27:30 PM PDT 24
Finished Aug 04 05:27:36 PM PDT 24
Peak memory 242180 kb
Host smart-bd36e356-6eb3-498c-b518-185b4019370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962589179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.3962589179
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.2185700377
Short name T1189
Test name
Test status
Simulation time 1849098554 ps
CPU time 4.45 seconds
Started Aug 04 05:27:46 PM PDT 24
Finished Aug 04 05:27:51 PM PDT 24
Peak memory 242032 kb
Host smart-d5c86b31-84cb-416e-97bc-59daea85cf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185700377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.2185700377
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.2974409261
Short name T1187
Test name
Test status
Simulation time 320477771 ps
CPU time 3.65 seconds
Started Aug 04 05:27:33 PM PDT 24
Finished Aug 04 05:27:37 PM PDT 24
Peak memory 242180 kb
Host smart-bcc271ff-9766-4f0b-9e2e-3405c87d027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974409261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2974409261
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.1258793445
Short name T980
Test name
Test status
Simulation time 527021812 ps
CPU time 4.2 seconds
Started Aug 04 05:27:32 PM PDT 24
Finished Aug 04 05:27:36 PM PDT 24
Peak memory 242176 kb
Host smart-fcd51fab-281d-450f-896f-774e979fc8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258793445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1258793445
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.2959059342
Short name T539
Test name
Test status
Simulation time 133455835 ps
CPU time 3.41 seconds
Started Aug 04 05:27:29 PM PDT 24
Finished Aug 04 05:27:33 PM PDT 24
Peak memory 242152 kb
Host smart-2ebf759d-d307-4114-a9b3-339afa72c9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959059342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.2959059342
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.608334339
Short name T407
Test name
Test status
Simulation time 2759244158 ps
CPU time 7.2 seconds
Started Aug 04 05:27:30 PM PDT 24
Finished Aug 04 05:27:38 PM PDT 24
Peak memory 242204 kb
Host smart-c12ed3bd-ecb7-497f-8fec-ef6cae8ae022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608334339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.608334339
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.2147308627
Short name T621
Test name
Test status
Simulation time 105497265 ps
CPU time 1.87 seconds
Started Aug 04 05:24:34 PM PDT 24
Finished Aug 04 05:24:36 PM PDT 24
Peak memory 240860 kb
Host smart-347a7f33-55fc-475c-9040-e9e525538cdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147308627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.2147308627
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.677767268
Short name T745
Test name
Test status
Simulation time 646508660 ps
CPU time 8.55 seconds
Started Aug 04 05:24:29 PM PDT 24
Finished Aug 04 05:24:38 PM PDT 24
Peak memory 242132 kb
Host smart-5307481d-c8f7-4dfc-bf14-9540535947d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677767268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.677767268
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.2700641735
Short name T947
Test name
Test status
Simulation time 361973913 ps
CPU time 9.52 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:24:40 PM PDT 24
Peak memory 248576 kb
Host smart-291458c5-6155-4a81-ad12-660d5bdd12a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700641735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.2700641735
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.1612674176
Short name T293
Test name
Test status
Simulation time 4285894959 ps
CPU time 29.67 seconds
Started Aug 04 05:24:29 PM PDT 24
Finished Aug 04 05:24:59 PM PDT 24
Peak memory 244016 kb
Host smart-a0a2f8d6-45e4-4e15-b223-faebe4f09de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612674176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.1612674176
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.2279483624
Short name T349
Test name
Test status
Simulation time 1399515768 ps
CPU time 15.02 seconds
Started Aug 04 05:24:31 PM PDT 24
Finished Aug 04 05:24:46 PM PDT 24
Peak memory 242048 kb
Host smart-f9b9dfe8-d298-49fb-9e65-3b0dfebae342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279483624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.2279483624
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.1999520363
Short name T912
Test name
Test status
Simulation time 166266172 ps
CPU time 4.45 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:24:35 PM PDT 24
Peak memory 242236 kb
Host smart-72309a26-f5c8-49cc-ad84-1ec598757f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999520363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.1999520363
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.2378624077
Short name T200
Test name
Test status
Simulation time 3486940119 ps
CPU time 40.98 seconds
Started Aug 04 05:24:36 PM PDT 24
Finished Aug 04 05:25:17 PM PDT 24
Peak memory 248688 kb
Host smart-795c8cb0-76e8-4e5e-9439-a80872684aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378624077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.2378624077
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.1704343733
Short name T668
Test name
Test status
Simulation time 489556415 ps
CPU time 10.88 seconds
Started Aug 04 05:24:36 PM PDT 24
Finished Aug 04 05:24:47 PM PDT 24
Peak memory 241952 kb
Host smart-3260af92-1c3f-42fa-b810-06a67d69a17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704343733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1704343733
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.2860032225
Short name T642
Test name
Test status
Simulation time 2941877547 ps
CPU time 7.53 seconds
Started Aug 04 05:24:32 PM PDT 24
Finished Aug 04 05:24:40 PM PDT 24
Peak memory 242304 kb
Host smart-06d686ae-f45d-4ebd-be72-ca5d1c5e4e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860032225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2860032225
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.3748625643
Short name T730
Test name
Test status
Simulation time 341508295 ps
CPU time 11.78 seconds
Started Aug 04 05:24:30 PM PDT 24
Finished Aug 04 05:24:42 PM PDT 24
Peak memory 241984 kb
Host smart-815c546b-649b-45e1-843c-69b9831c6373
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748625643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.3748625643
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.252589497
Short name T20
Test name
Test status
Simulation time 155298038575 ps
CPU time 311.65 seconds
Started Aug 04 05:24:37 PM PDT 24
Finished Aug 04 05:29:48 PM PDT 24
Peak memory 266472 kb
Host smart-184a4524-a5c1-4cca-acb8-a99252b54130
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252589497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.252589497
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.2577493424
Short name T456
Test name
Test status
Simulation time 249479009 ps
CPU time 4.17 seconds
Started Aug 04 05:24:31 PM PDT 24
Finished Aug 04 05:24:36 PM PDT 24
Peak memory 242016 kb
Host smart-b50ceda0-fd88-4bfc-ba0d-180c1e34935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577493424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2577493424
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.341892643
Short name T865
Test name
Test status
Simulation time 6241087150 ps
CPU time 71.75 seconds
Started Aug 04 05:24:35 PM PDT 24
Finished Aug 04 05:25:47 PM PDT 24
Peak memory 258804 kb
Host smart-2455c750-adf0-4e4e-b98f-a04f874077d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341892643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.341892643
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.2381023334
Short name T495
Test name
Test status
Simulation time 1094326446 ps
CPU time 9.08 seconds
Started Aug 04 05:24:36 PM PDT 24
Finished Aug 04 05:24:45 PM PDT 24
Peak memory 242016 kb
Host smart-22f5707e-3380-4314-9363-230ca5763398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381023334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2381023334
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.1815511741
Short name T590
Test name
Test status
Simulation time 161547709 ps
CPU time 1.78 seconds
Started Aug 04 05:25:44 PM PDT 24
Finished Aug 04 05:25:46 PM PDT 24
Peak memory 240656 kb
Host smart-f8cbe0f4-7788-4842-a9cb-a02ffd641b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815511741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.1815511741
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.733149182
Short name T485
Test name
Test status
Simulation time 207423892 ps
CPU time 5.37 seconds
Started Aug 04 05:25:47 PM PDT 24
Finished Aug 04 05:25:53 PM PDT 24
Peak memory 248572 kb
Host smart-8b313650-d16d-4b05-be51-fd362118a6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733149182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.733149182
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.2712267770
Short name T722
Test name
Test status
Simulation time 988249829 ps
CPU time 32.75 seconds
Started Aug 04 05:25:45 PM PDT 24
Finished Aug 04 05:26:17 PM PDT 24
Peak memory 244640 kb
Host smart-4b614a18-db86-4b90-a0c9-e83e039463d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712267770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.2712267770
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.3812361768
Short name T829
Test name
Test status
Simulation time 3977818869 ps
CPU time 16.95 seconds
Started Aug 04 05:25:47 PM PDT 24
Finished Aug 04 05:26:04 PM PDT 24
Peak memory 241920 kb
Host smart-a4df8bdd-77dc-4447-8c58-a3cf915b9226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812361768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.3812361768
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.3473652067
Short name T592
Test name
Test status
Simulation time 279557608 ps
CPU time 4.45 seconds
Started Aug 04 05:25:41 PM PDT 24
Finished Aug 04 05:25:45 PM PDT 24
Peak memory 242080 kb
Host smart-92c1b493-a348-4f10-a956-71cb93eb9ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473652067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.3473652067
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.3503498059
Short name T589
Test name
Test status
Simulation time 1393805616 ps
CPU time 27.67 seconds
Started Aug 04 05:25:43 PM PDT 24
Finished Aug 04 05:26:11 PM PDT 24
Peak memory 248564 kb
Host smart-baf381bf-8399-444a-a85f-a47756fb98a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503498059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.3503498059
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.2530922464
Short name T759
Test name
Test status
Simulation time 16288785666 ps
CPU time 35.73 seconds
Started Aug 04 05:25:46 PM PDT 24
Finished Aug 04 05:26:21 PM PDT 24
Peak memory 242880 kb
Host smart-8b19a60f-57f9-44aa-8d0b-dc33e8f68f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530922464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.2530922464
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.2558387897
Short name T560
Test name
Test status
Simulation time 145843581 ps
CPU time 6.56 seconds
Started Aug 04 05:25:42 PM PDT 24
Finished Aug 04 05:25:48 PM PDT 24
Peak memory 241984 kb
Host smart-99a6e855-ba3e-410d-bc61-bec226e2baaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558387897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2558387897
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.2295606018
Short name T1070
Test name
Test status
Simulation time 417624812 ps
CPU time 9.43 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:25:59 PM PDT 24
Peak memory 241944 kb
Host smart-bb559185-7cbd-4d16-804f-f0f1c1ff2f1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295606018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.2295606018
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.4036675235
Short name T320
Test name
Test status
Simulation time 829023105 ps
CPU time 5.46 seconds
Started Aug 04 05:25:45 PM PDT 24
Finished Aug 04 05:25:50 PM PDT 24
Peak memory 242052 kb
Host smart-e6a1a8f8-1241-483a-a9d1-bbf94e36e3f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036675235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.4036675235
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.2946792540
Short name T376
Test name
Test status
Simulation time 293226966 ps
CPU time 9.79 seconds
Started Aug 04 05:25:45 PM PDT 24
Finished Aug 04 05:25:55 PM PDT 24
Peak memory 242192 kb
Host smart-af42b9fe-6590-42ad-bd9f-9baf29266bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946792540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2946792540
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.2716221240
Short name T625
Test name
Test status
Simulation time 32468832354 ps
CPU time 184.46 seconds
Started Aug 04 05:25:48 PM PDT 24
Finished Aug 04 05:28:53 PM PDT 24
Peak memory 253000 kb
Host smart-c239a3b7-ce3f-429f-ba1d-09c8dc791db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716221240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.2716221240
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.3423309594
Short name T239
Test name
Test status
Simulation time 22791290607 ps
CPU time 258.31 seconds
Started Aug 04 05:25:47 PM PDT 24
Finished Aug 04 05:30:06 PM PDT 24
Peak memory 265104 kb
Host smart-9cea724d-fa6d-4464-b10d-c4eddfb17aaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423309594 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.3423309594
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.3174239910
Short name T982
Test name
Test status
Simulation time 2065564581 ps
CPU time 23.52 seconds
Started Aug 04 05:25:48 PM PDT 24
Finished Aug 04 05:26:11 PM PDT 24
Peak memory 242484 kb
Host smart-6231d3c1-15c0-4b33-996a-479328220129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174239910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3174239910
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.1597962561
Short name T529
Test name
Test status
Simulation time 583502715 ps
CPU time 2.01 seconds
Started Aug 04 05:25:51 PM PDT 24
Finished Aug 04 05:25:53 PM PDT 24
Peak memory 240468 kb
Host smart-755536e4-34e4-4690-9726-b93fa24bcf55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597962561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1597962561
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.915362487
Short name T701
Test name
Test status
Simulation time 792375201 ps
CPU time 13.2 seconds
Started Aug 04 05:25:45 PM PDT 24
Finished Aug 04 05:25:59 PM PDT 24
Peak memory 241960 kb
Host smart-3a9cbf55-ca73-49bd-8af5-27d373882bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915362487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.915362487
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.256676267
Short name T371
Test name
Test status
Simulation time 1041874345 ps
CPU time 32.65 seconds
Started Aug 04 05:25:45 PM PDT 24
Finished Aug 04 05:26:17 PM PDT 24
Peak memory 242216 kb
Host smart-ac1311b8-89ef-4a44-85f1-80b44e0ebc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256676267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.256676267
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.1532662592
Short name T98
Test name
Test status
Simulation time 262747026 ps
CPU time 6.01 seconds
Started Aug 04 05:25:47 PM PDT 24
Finished Aug 04 05:25:53 PM PDT 24
Peak memory 248468 kb
Host smart-5975f793-6e9d-4b09-aa0e-a7ec96521f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532662592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.1532662592
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.1112951440
Short name T1177
Test name
Test status
Simulation time 360432550 ps
CPU time 4.71 seconds
Started Aug 04 05:25:47 PM PDT 24
Finished Aug 04 05:25:51 PM PDT 24
Peak memory 242012 kb
Host smart-a6f3f781-db7a-4a1c-a14c-70531674b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112951440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.1112951440
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.1185630533
Short name T1170
Test name
Test status
Simulation time 419039111 ps
CPU time 8.39 seconds
Started Aug 04 05:25:48 PM PDT 24
Finished Aug 04 05:25:57 PM PDT 24
Peak memory 241936 kb
Host smart-d4ef48bc-bd78-4f94-98aa-67e4308ee022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185630533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.1185630533
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.3174228245
Short name T1083
Test name
Test status
Simulation time 839855104 ps
CPU time 12.83 seconds
Started Aug 04 05:25:45 PM PDT 24
Finished Aug 04 05:25:58 PM PDT 24
Peak memory 242008 kb
Host smart-ec1b84ac-234d-4ffe-9cbf-8079e52356a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174228245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.3174228245
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.441656486
Short name T881
Test name
Test status
Simulation time 1693898459 ps
CPU time 17.62 seconds
Started Aug 04 05:25:46 PM PDT 24
Finished Aug 04 05:26:03 PM PDT 24
Peak memory 242136 kb
Host smart-03e8bfe3-c2ea-4e2e-a1be-ba32d3415927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441656486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.441656486
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.1678601753
Short name T511
Test name
Test status
Simulation time 387905927 ps
CPU time 4.41 seconds
Started Aug 04 05:25:50 PM PDT 24
Finished Aug 04 05:25:55 PM PDT 24
Peak memory 241892 kb
Host smart-2f67d36e-f0e0-4ec3-8ecb-1fc174ec0202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678601753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1678601753
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.865377201
Short name T1148
Test name
Test status
Simulation time 1040322110 ps
CPU time 7.61 seconds
Started Aug 04 05:25:45 PM PDT 24
Finished Aug 04 05:25:52 PM PDT 24
Peak memory 242012 kb
Host smart-a92210b9-3861-447b-91ae-8e98389a2378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865377201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.865377201
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.1850088829
Short name T994
Test name
Test status
Simulation time 10705104188 ps
CPU time 107.58 seconds
Started Aug 04 05:25:48 PM PDT 24
Finished Aug 04 05:27:36 PM PDT 24
Peak memory 256864 kb
Host smart-92e12078-4dcd-4aa5-9a9f-0edd499236e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850088829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.1850088829
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.2382966632
Short name T480
Test name
Test status
Simulation time 66656183646 ps
CPU time 1250.09 seconds
Started Aug 04 05:25:43 PM PDT 24
Finished Aug 04 05:46:33 PM PDT 24
Peak memory 385960 kb
Host smart-4a436f58-65a0-40dc-811b-d45ab82f065a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382966632 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.2382966632
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.74921723
Short name T836
Test name
Test status
Simulation time 365442018 ps
CPU time 6.32 seconds
Started Aug 04 05:25:46 PM PDT 24
Finished Aug 04 05:25:53 PM PDT 24
Peak memory 242156 kb
Host smart-c9255811-06e4-4ead-a963-f6a7fd6de8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74921723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.74921723
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.292154796
Short name T981
Test name
Test status
Simulation time 44571805 ps
CPU time 1.58 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:25:51 PM PDT 24
Peak memory 240464 kb
Host smart-9528a1c5-2d35-486e-b330-5f3c2043d28a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292154796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.292154796
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.1428748223
Short name T665
Test name
Test status
Simulation time 151470847 ps
CPU time 4.17 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:25:53 PM PDT 24
Peak memory 241968 kb
Host smart-122ece8c-c268-42e8-963a-8e3613ead8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428748223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1428748223
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.3566338396
Short name T1136
Test name
Test status
Simulation time 300216439 ps
CPU time 8.96 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:25:58 PM PDT 24
Peak memory 242360 kb
Host smart-5a992608-4062-4597-8724-26784b117dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566338396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.3566338396
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.32028458
Short name T104
Test name
Test status
Simulation time 1328923956 ps
CPU time 25.24 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:26:14 PM PDT 24
Peak memory 242544 kb
Host smart-ad038ab6-c116-4256-9717-e6eb694dbceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32028458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.32028458
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.2562396987
Short name T850
Test name
Test status
Simulation time 320847643 ps
CPU time 4.97 seconds
Started Aug 04 05:25:44 PM PDT 24
Finished Aug 04 05:25:49 PM PDT 24
Peak memory 242228 kb
Host smart-951eb4cc-d0ea-40c1-9508-17abde2b4e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562396987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.2562396987
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.493283106
Short name T999
Test name
Test status
Simulation time 1147098891 ps
CPU time 27.94 seconds
Started Aug 04 05:25:51 PM PDT 24
Finished Aug 04 05:26:19 PM PDT 24
Peak memory 248584 kb
Host smart-ffea76ae-17bf-48cc-9d2f-4529f1433257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493283106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.493283106
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.890596336
Short name T1124
Test name
Test status
Simulation time 417670171 ps
CPU time 10.76 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:26:00 PM PDT 24
Peak memory 242072 kb
Host smart-7575a725-2d43-4133-94d0-b0f65712403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890596336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.890596336
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.964480456
Short name T307
Test name
Test status
Simulation time 1647688253 ps
CPU time 11.68 seconds
Started Aug 04 05:25:45 PM PDT 24
Finished Aug 04 05:25:57 PM PDT 24
Peak memory 241948 kb
Host smart-6e3669db-18c8-4afb-b76e-d62f2defe9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964480456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.964480456
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.630248590
Short name T623
Test name
Test status
Simulation time 147751506 ps
CPU time 4.36 seconds
Started Aug 04 05:25:47 PM PDT 24
Finished Aug 04 05:25:51 PM PDT 24
Peak memory 242008 kb
Host smart-bcd3eeb7-ac4a-4b13-b578-2f527989a9af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=630248590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.630248590
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.3512381885
Short name T1105
Test name
Test status
Simulation time 186882968 ps
CPU time 5.71 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:25:54 PM PDT 24
Peak memory 242344 kb
Host smart-3310ab91-4cd1-448e-8349-e3464f4b9d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3512381885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.3512381885
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.625517516
Short name T799
Test name
Test status
Simulation time 236984631 ps
CPU time 5.45 seconds
Started Aug 04 05:25:47 PM PDT 24
Finished Aug 04 05:25:52 PM PDT 24
Peak memory 241916 kb
Host smart-5c5ecdea-71ae-4cd5-8596-236cd3b9cdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625517516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.625517516
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.1671830537
Short name T355
Test name
Test status
Simulation time 36253862268 ps
CPU time 180.6 seconds
Started Aug 04 05:25:50 PM PDT 24
Finished Aug 04 05:28:51 PM PDT 24
Peak memory 250032 kb
Host smart-0b66bb03-8b20-44d0-b6c4-7aab6a11c0b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671830537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.1671830537
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.999318727
Short name T707
Test name
Test status
Simulation time 53439212868 ps
CPU time 960.81 seconds
Started Aug 04 05:25:48 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 295700 kb
Host smart-45dcd3ce-b8bc-4989-ba52-444bc86007b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999318727 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.999318727
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.800513454
Short name T563
Test name
Test status
Simulation time 1242880454 ps
CPU time 11.93 seconds
Started Aug 04 05:25:52 PM PDT 24
Finished Aug 04 05:26:04 PM PDT 24
Peak memory 242244 kb
Host smart-83bbfa63-0094-4694-9acd-61510a304252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800513454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.800513454
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.3912808869
Short name T530
Test name
Test status
Simulation time 43761327 ps
CPU time 1.56 seconds
Started Aug 04 05:25:53 PM PDT 24
Finished Aug 04 05:25:54 PM PDT 24
Peak memory 240320 kb
Host smart-4200f962-0082-49e3-a277-5053eddce474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912808869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3912808869
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.2554930835
Short name T744
Test name
Test status
Simulation time 1311283993 ps
CPU time 10.79 seconds
Started Aug 04 05:25:47 PM PDT 24
Finished Aug 04 05:25:58 PM PDT 24
Peak memory 241932 kb
Host smart-fd2d380c-e509-49ee-adba-ee3e00621210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554930835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2554930835
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.944760559
Short name T1174
Test name
Test status
Simulation time 25246090164 ps
CPU time 79.16 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:27:09 PM PDT 24
Peak memory 256900 kb
Host smart-5b3a4d8b-1db1-4d0c-a223-ec651755cdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944760559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.944760559
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.3076478244
Short name T157
Test name
Test status
Simulation time 522591692 ps
CPU time 10.41 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:26:00 PM PDT 24
Peak memory 241924 kb
Host smart-1b490924-0824-47fe-8d29-fea880dd187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076478244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3076478244
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.803428831
Short name T1081
Test name
Test status
Simulation time 202841089 ps
CPU time 4.02 seconds
Started Aug 04 05:25:50 PM PDT 24
Finished Aug 04 05:25:55 PM PDT 24
Peak memory 242200 kb
Host smart-eeb82a91-546d-4512-a939-b49c0ae86a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803428831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.803428831
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.714805661
Short name T150
Test name
Test status
Simulation time 1403346607 ps
CPU time 25.74 seconds
Started Aug 04 05:25:51 PM PDT 24
Finished Aug 04 05:26:17 PM PDT 24
Peak memory 243968 kb
Host smart-dc177041-4e65-444b-9ad7-9cc5b952890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714805661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.714805661
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.2934007981
Short name T365
Test name
Test status
Simulation time 273580824 ps
CPU time 6.43 seconds
Started Aug 04 05:25:48 PM PDT 24
Finished Aug 04 05:25:54 PM PDT 24
Peak memory 248528 kb
Host smart-3fb77953-bf33-4c2d-96bb-14f1e1e804bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934007981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2934007981
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.2673698003
Short name T400
Test name
Test status
Simulation time 886381908 ps
CPU time 8.22 seconds
Started Aug 04 05:25:50 PM PDT 24
Finished Aug 04 05:25:58 PM PDT 24
Peak memory 242240 kb
Host smart-95312f8e-092f-4968-86b5-f253c6672b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673698003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2673698003
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.547576740
Short name T100
Test name
Test status
Simulation time 2532064160 ps
CPU time 27.63 seconds
Started Aug 04 05:25:49 PM PDT 24
Finished Aug 04 05:26:17 PM PDT 24
Peak memory 242004 kb
Host smart-3e0e64e7-87e2-4e3d-9a8c-ba2ce0940a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547576740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.547576740
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.305352568
Short name T756
Test name
Test status
Simulation time 212067852 ps
CPU time 6.31 seconds
Started Aug 04 05:25:48 PM PDT 24
Finished Aug 04 05:25:55 PM PDT 24
Peak memory 242176 kb
Host smart-9cb168de-8a00-4416-8eab-42f52865332d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305352568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.305352568
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.3697614749
Short name T441
Test name
Test status
Simulation time 543472521 ps
CPU time 6.61 seconds
Started Aug 04 05:25:48 PM PDT 24
Finished Aug 04 05:25:54 PM PDT 24
Peak memory 242020 kb
Host smart-56ffdf85-17f4-4420-94b0-8c414713684c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697614749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.3697614749
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.2436550906
Short name T992
Test name
Test status
Simulation time 7462794218 ps
CPU time 69.47 seconds
Started Aug 04 05:25:52 PM PDT 24
Finished Aug 04 05:27:02 PM PDT 24
Peak memory 248640 kb
Host smart-7a729078-cf3d-4516-a1c8-aad761dfca48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436550906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.2436550906
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.3417722268
Short name T277
Test name
Test status
Simulation time 2677289640 ps
CPU time 26.93 seconds
Started Aug 04 05:25:50 PM PDT 24
Finished Aug 04 05:26:17 PM PDT 24
Peak memory 242236 kb
Host smart-caf7638b-f736-4f30-9edd-fbe44bf5302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417722268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.3417722268
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.3480811176
Short name T934
Test name
Test status
Simulation time 627135816 ps
CPU time 2.49 seconds
Started Aug 04 05:25:54 PM PDT 24
Finished Aug 04 05:25:56 PM PDT 24
Peak memory 240612 kb
Host smart-6606ab42-2f84-4884-9686-fe65b65adfed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480811176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3480811176
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.41885098
Short name T1064
Test name
Test status
Simulation time 364432706 ps
CPU time 4.28 seconds
Started Aug 04 05:25:58 PM PDT 24
Finished Aug 04 05:26:02 PM PDT 24
Peak memory 241924 kb
Host smart-473e9141-344a-41f3-bf82-702a61520ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41885098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.41885098
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.722974748
Short name T1071
Test name
Test status
Simulation time 908938351 ps
CPU time 26.01 seconds
Started Aug 04 05:25:52 PM PDT 24
Finished Aug 04 05:26:19 PM PDT 24
Peak memory 241952 kb
Host smart-564d09ae-3d1f-4bb2-a89c-f070a5fcace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722974748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.722974748
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.1475888992
Short name T338
Test name
Test status
Simulation time 1841740314 ps
CPU time 33.54 seconds
Started Aug 04 05:25:58 PM PDT 24
Finished Aug 04 05:26:31 PM PDT 24
Peak memory 242340 kb
Host smart-9ed1db72-1cbe-43e3-a781-9002ca568509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475888992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.1475888992
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.755990213
Short name T612
Test name
Test status
Simulation time 179434086 ps
CPU time 4.95 seconds
Started Aug 04 05:25:52 PM PDT 24
Finished Aug 04 05:25:58 PM PDT 24
Peak memory 242000 kb
Host smart-28fbc0e4-8868-4d83-8ec4-f3aa3853ab43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755990213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.755990213
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.2332867577
Short name T765
Test name
Test status
Simulation time 2686322116 ps
CPU time 22.8 seconds
Started Aug 04 05:25:53 PM PDT 24
Finished Aug 04 05:26:16 PM PDT 24
Peak memory 244792 kb
Host smart-0354cf8c-3930-487b-8c7a-8d23b686d6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332867577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.2332867577
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.2376986856
Short name T773
Test name
Test status
Simulation time 1793286690 ps
CPU time 37.11 seconds
Started Aug 04 05:25:52 PM PDT 24
Finished Aug 04 05:26:29 PM PDT 24
Peak memory 242284 kb
Host smart-e2bedf53-50b9-466c-8828-afd4d3b025e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376986856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.2376986856
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.2584305261
Short name T770
Test name
Test status
Simulation time 1166272115 ps
CPU time 16.25 seconds
Started Aug 04 05:25:54 PM PDT 24
Finished Aug 04 05:26:10 PM PDT 24
Peak memory 242040 kb
Host smart-45dfd342-07a1-4757-a7ce-113d5ff4ead4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584305261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.2584305261
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.1921467504
Short name T348
Test name
Test status
Simulation time 1211868702 ps
CPU time 8.03 seconds
Started Aug 04 05:25:53 PM PDT 24
Finished Aug 04 05:26:01 PM PDT 24
Peak memory 248512 kb
Host smart-4601666a-8d6d-4e44-8ace-979b26179841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921467504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.1921467504
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2915703099
Short name T732
Test name
Test status
Simulation time 596605417 ps
CPU time 6.42 seconds
Started Aug 04 05:25:52 PM PDT 24
Finished Aug 04 05:25:58 PM PDT 24
Peak memory 241928 kb
Host smart-4862bce9-9542-46de-be13-6eda61e3ee83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2915703099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2915703099
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.1025446830
Short name T506
Test name
Test status
Simulation time 420855263 ps
CPU time 7.53 seconds
Started Aug 04 05:25:52 PM PDT 24
Finished Aug 04 05:26:00 PM PDT 24
Peak memory 242192 kb
Host smart-e9b63720-3d13-480e-bd2a-8bce298370ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025446830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1025446830
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.2839420140
Short name T763
Test name
Test status
Simulation time 22702338156 ps
CPU time 240.85 seconds
Started Aug 04 05:25:54 PM PDT 24
Finished Aug 04 05:29:55 PM PDT 24
Peak memory 270444 kb
Host smart-38efa920-4b52-4661-8bfe-f3bbac034ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839420140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.2839420140
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.228029195
Short name T1185
Test name
Test status
Simulation time 104778572526 ps
CPU time 2431.3 seconds
Started Aug 04 05:25:53 PM PDT 24
Finished Aug 04 06:06:24 PM PDT 24
Peak memory 357576 kb
Host smart-42f42b2c-f797-43d1-957f-a2a6f6697b1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228029195 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.228029195
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.1171242140
Short name T1058
Test name
Test status
Simulation time 1163848106 ps
CPU time 22.5 seconds
Started Aug 04 05:25:53 PM PDT 24
Finished Aug 04 05:26:15 PM PDT 24
Peak memory 242340 kb
Host smart-a998d1bd-75f6-4ae5-9b2d-0ade7de50beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171242140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.1171242140
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.547836234
Short name T828
Test name
Test status
Simulation time 689652325 ps
CPU time 2.1 seconds
Started Aug 04 05:25:55 PM PDT 24
Finished Aug 04 05:25:57 PM PDT 24
Peak memory 240428 kb
Host smart-a822dedc-4f44-4200-8f5e-33cf4637d292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547836234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.547836234
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.2757771289
Short name T879
Test name
Test status
Simulation time 1992957237 ps
CPU time 6.25 seconds
Started Aug 04 05:25:54 PM PDT 24
Finished Aug 04 05:26:01 PM PDT 24
Peak memory 241784 kb
Host smart-86061028-6fcd-4bdb-8c11-911e369e83bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757771289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.2757771289
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.3187100581
Short name T693
Test name
Test status
Simulation time 652798580 ps
CPU time 19.5 seconds
Started Aug 04 05:25:53 PM PDT 24
Finished Aug 04 05:26:13 PM PDT 24
Peak memory 242020 kb
Host smart-137e9435-c1a6-4db6-bcdc-19d1fe2d8c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187100581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.3187100581
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.1329084418
Short name T843
Test name
Test status
Simulation time 1012154963 ps
CPU time 14.44 seconds
Started Aug 04 05:25:53 PM PDT 24
Finished Aug 04 05:26:08 PM PDT 24
Peak memory 242356 kb
Host smart-2bc5289f-ba30-48be-b3f3-0ca267053908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329084418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1329084418
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1303643024
Short name T1041
Test name
Test status
Simulation time 110725771 ps
CPU time 4.28 seconds
Started Aug 04 05:25:52 PM PDT 24
Finished Aug 04 05:25:57 PM PDT 24
Peak memory 241848 kb
Host smart-d82e8866-6fad-43a1-abbe-108ff7d32461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303643024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1303643024
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.1397710393
Short name T1113
Test name
Test status
Simulation time 1367155675 ps
CPU time 17.69 seconds
Started Aug 04 05:25:58 PM PDT 24
Finished Aug 04 05:26:16 PM PDT 24
Peak memory 248516 kb
Host smart-7bfa0113-e877-48d2-9a2f-7c48d940e736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397710393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.1397710393
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1285459120
Short name T94
Test name
Test status
Simulation time 469629262 ps
CPU time 18.82 seconds
Started Aug 04 05:25:55 PM PDT 24
Finished Aug 04 05:26:14 PM PDT 24
Peak memory 242080 kb
Host smart-4720067b-9458-45dd-8635-6f9f75e3f037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285459120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1285459120
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.611038082
Short name T837
Test name
Test status
Simulation time 526588461 ps
CPU time 6.78 seconds
Started Aug 04 05:25:53 PM PDT 24
Finished Aug 04 05:25:59 PM PDT 24
Peak memory 241960 kb
Host smart-b6884f33-7191-486c-b382-93217e621a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611038082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.611038082
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.1688057623
Short name T444
Test name
Test status
Simulation time 964847650 ps
CPU time 24.36 seconds
Started Aug 04 05:25:55 PM PDT 24
Finished Aug 04 05:26:19 PM PDT 24
Peak memory 242072 kb
Host smart-6c5d57c7-223b-4e7c-bd8e-22902cbe3855
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688057623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1688057623
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.3127125328
Short name T328
Test name
Test status
Simulation time 126358625 ps
CPU time 3.16 seconds
Started Aug 04 05:25:55 PM PDT 24
Finished Aug 04 05:25:59 PM PDT 24
Peak memory 248324 kb
Host smart-65155fda-d406-4f33-a29f-d79658c9782f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3127125328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3127125328
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1588850486
Short name T198
Test name
Test status
Simulation time 150359297 ps
CPU time 5.23 seconds
Started Aug 04 05:25:52 PM PDT 24
Finished Aug 04 05:25:57 PM PDT 24
Peak memory 242016 kb
Host smart-1188e99f-0c8a-4c1f-a7b4-f014c2212b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588850486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1588850486
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.686292682
Short name T1176
Test name
Test status
Simulation time 20561772465 ps
CPU time 188.89 seconds
Started Aug 04 05:25:55 PM PDT 24
Finished Aug 04 05:29:04 PM PDT 24
Peak memory 256832 kb
Host smart-b25dc116-3390-4072-bcb2-a67a4948632f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686292682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.
686292682
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.120598513
Short name T677
Test name
Test status
Simulation time 123370198186 ps
CPU time 1446.26 seconds
Started Aug 04 05:25:55 PM PDT 24
Finished Aug 04 05:50:01 PM PDT 24
Peak memory 392800 kb
Host smart-d3e2541a-bcb0-4aa3-8594-84d41fe7e6b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120598513 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.120598513
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.1903131455
Short name T595
Test name
Test status
Simulation time 2533392276 ps
CPU time 25.3 seconds
Started Aug 04 05:25:56 PM PDT 24
Finished Aug 04 05:26:21 PM PDT 24
Peak memory 242516 kb
Host smart-c929c2dd-272a-4278-96ed-9389255e1052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903131455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.1903131455
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.1629919846
Short name T832
Test name
Test status
Simulation time 182811759 ps
CPU time 1.86 seconds
Started Aug 04 05:25:57 PM PDT 24
Finished Aug 04 05:25:59 PM PDT 24
Peak memory 240728 kb
Host smart-baf1c64f-3086-4348-9d82-13c955392a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629919846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1629919846
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.2552581186
Short name T591
Test name
Test status
Simulation time 4906973765 ps
CPU time 21.45 seconds
Started Aug 04 05:25:55 PM PDT 24
Finished Aug 04 05:26:17 PM PDT 24
Peak memory 241940 kb
Host smart-d85aa944-58f8-4407-b034-da74ba3aff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552581186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.2552581186
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.2319772296
Short name T777
Test name
Test status
Simulation time 1890012832 ps
CPU time 19.55 seconds
Started Aug 04 05:25:59 PM PDT 24
Finished Aug 04 05:26:18 PM PDT 24
Peak memory 242192 kb
Host smart-792c2915-de8f-476c-a12c-61de3e36b483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319772296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2319772296
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.2483353652
Short name T29
Test name
Test status
Simulation time 536134638 ps
CPU time 5.02 seconds
Started Aug 04 05:25:56 PM PDT 24
Finished Aug 04 05:26:01 PM PDT 24
Peak memory 242224 kb
Host smart-0bb93416-f15e-4e2c-82c5-cf5d338ff0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483353652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.2483353652
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.521218030
Short name T491
Test name
Test status
Simulation time 1337932599 ps
CPU time 19.56 seconds
Started Aug 04 05:25:58 PM PDT 24
Finished Aug 04 05:26:17 PM PDT 24
Peak memory 243136 kb
Host smart-3bf2b37f-527d-4d28-a63f-5070458c38e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521218030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.521218030
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.2403830994
Short name T1048
Test name
Test status
Simulation time 769979633 ps
CPU time 9.56 seconds
Started Aug 04 05:25:58 PM PDT 24
Finished Aug 04 05:26:07 PM PDT 24
Peak memory 242120 kb
Host smart-d6bc6b14-ed0d-4826-aa0e-9af2aec06b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403830994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.2403830994
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.3304011325
Short name T571
Test name
Test status
Simulation time 298543901 ps
CPU time 4.47 seconds
Started Aug 04 05:25:54 PM PDT 24
Finished Aug 04 05:25:59 PM PDT 24
Peak memory 241936 kb
Host smart-5d870b28-86ed-49ef-98f6-21d8fa81114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304011325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3304011325
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.3415166697
Short name T797
Test name
Test status
Simulation time 3155481993 ps
CPU time 8.7 seconds
Started Aug 04 05:25:58 PM PDT 24
Finished Aug 04 05:26:07 PM PDT 24
Peak memory 248620 kb
Host smart-8f069ddc-26a5-4a8c-b8aa-1b8e38b90c55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3415166697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.3415166697
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.829063741
Short name T103
Test name
Test status
Simulation time 1757748595 ps
CPU time 5.46 seconds
Started Aug 04 05:26:00 PM PDT 24
Finished Aug 04 05:26:06 PM PDT 24
Peak memory 242324 kb
Host smart-ab7f61b7-8b1e-434e-86f5-62f397cc4ed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829063741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.829063741
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.987221336
Short name T513
Test name
Test status
Simulation time 647432287 ps
CPU time 3.95 seconds
Started Aug 04 05:25:56 PM PDT 24
Finished Aug 04 05:26:00 PM PDT 24
Peak memory 241948 kb
Host smart-a1a65a6e-e1e2-4617-b1d9-a8bf0803b40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987221336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.987221336
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.3439505538
Short name T1133
Test name
Test status
Simulation time 23200755279 ps
CPU time 190.02 seconds
Started Aug 04 05:25:56 PM PDT 24
Finished Aug 04 05:29:06 PM PDT 24
Peak memory 258364 kb
Host smart-7afa8136-e8c4-4ab8-8b92-e846250771b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439505538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.3439505538
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.3323216269
Short name T1147
Test name
Test status
Simulation time 2477356378 ps
CPU time 47.38 seconds
Started Aug 04 05:25:59 PM PDT 24
Finished Aug 04 05:26:46 PM PDT 24
Peak memory 248528 kb
Host smart-b944824a-631d-40ee-bb6d-c3d503a54b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323216269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.3323216269
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.1378612803
Short name T381
Test name
Test status
Simulation time 143255696 ps
CPU time 1.69 seconds
Started Aug 04 05:26:00 PM PDT 24
Finished Aug 04 05:26:02 PM PDT 24
Peak memory 240416 kb
Host smart-e55218b9-74cf-4b59-b132-d3aa71381074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378612803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.1378612803
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.1439553925
Short name T1108
Test name
Test status
Simulation time 981118930 ps
CPU time 14.56 seconds
Started Aug 04 05:26:02 PM PDT 24
Finished Aug 04 05:26:16 PM PDT 24
Peak memory 242208 kb
Host smart-a96daac4-0d42-4c77-9eac-a43400e60c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439553925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.1439553925
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.1747605680
Short name T1094
Test name
Test status
Simulation time 17268486946 ps
CPU time 51.15 seconds
Started Aug 04 05:26:03 PM PDT 24
Finished Aug 04 05:26:54 PM PDT 24
Peak memory 248984 kb
Host smart-1e40ecca-d60e-4008-9e40-8d43f0c31307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747605680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.1747605680
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.2379674096
Short name T944
Test name
Test status
Simulation time 549853129 ps
CPU time 13.27 seconds
Started Aug 04 05:26:01 PM PDT 24
Finished Aug 04 05:26:14 PM PDT 24
Peak memory 242280 kb
Host smart-1c0cdc77-4bd3-4f3b-9e15-14337d71216e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379674096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.2379674096
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.3450619373
Short name T203
Test name
Test status
Simulation time 324314999 ps
CPU time 4.25 seconds
Started Aug 04 05:25:59 PM PDT 24
Finished Aug 04 05:26:04 PM PDT 24
Peak memory 242220 kb
Host smart-4b287db1-772c-4ab9-ad7c-51c8845cdda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450619373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3450619373
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.3635066131
Short name T151
Test name
Test status
Simulation time 1766040942 ps
CPU time 21.71 seconds
Started Aug 04 05:25:58 PM PDT 24
Finished Aug 04 05:26:20 PM PDT 24
Peak memory 248580 kb
Host smart-6292c702-ec31-46c0-af98-06da8a7d34dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635066131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.3635066131
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.322596028
Short name T617
Test name
Test status
Simulation time 410602481 ps
CPU time 16.22 seconds
Started Aug 04 05:26:01 PM PDT 24
Finished Aug 04 05:26:18 PM PDT 24
Peak memory 242024 kb
Host smart-d3f3a1d0-18fa-4485-90c8-7af9265fd587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322596028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.322596028
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.1836831756
Short name T897
Test name
Test status
Simulation time 284595290 ps
CPU time 7.73 seconds
Started Aug 04 05:26:00 PM PDT 24
Finished Aug 04 05:26:08 PM PDT 24
Peak memory 242000 kb
Host smart-d032557e-6d0f-4770-812c-32ceeb7abccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836831756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1836831756
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.818108228
Short name T331
Test name
Test status
Simulation time 291045411 ps
CPU time 9.48 seconds
Started Aug 04 05:26:01 PM PDT 24
Finished Aug 04 05:26:11 PM PDT 24
Peak memory 241940 kb
Host smart-b886191f-a7c1-49a3-bf95-4112e78407c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818108228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.818108228
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.2065008953
Short name T497
Test name
Test status
Simulation time 4285086108 ps
CPU time 7.94 seconds
Started Aug 04 05:25:55 PM PDT 24
Finished Aug 04 05:26:03 PM PDT 24
Peak memory 242416 kb
Host smart-57d3d1d8-3f07-48f6-84d0-72ec8e0f1fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065008953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2065008953
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.576504262
Short name T212
Test name
Test status
Simulation time 3075179081 ps
CPU time 73.02 seconds
Started Aug 04 05:26:00 PM PDT 24
Finished Aug 04 05:27:13 PM PDT 24
Peak memory 257448 kb
Host smart-3f638cb2-7f9e-4a97-bc5d-d85a67940815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576504262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.
576504262
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.524197335
Short name T957
Test name
Test status
Simulation time 154415620373 ps
CPU time 1195.64 seconds
Started Aug 04 05:25:59 PM PDT 24
Finished Aug 04 05:45:55 PM PDT 24
Peak memory 383052 kb
Host smart-20af1c4d-53e4-4b71-91cd-c5ccc051dbbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524197335 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.524197335
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.2972182482
Short name T682
Test name
Test status
Simulation time 533049283 ps
CPU time 10.69 seconds
Started Aug 04 05:25:59 PM PDT 24
Finished Aug 04 05:26:10 PM PDT 24
Peak memory 248604 kb
Host smart-f56e56a9-5faa-4fc8-afc2-ecf4b571b8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972182482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.2972182482
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.939310925
Short name T883
Test name
Test status
Simulation time 1054693399 ps
CPU time 1.95 seconds
Started Aug 04 05:26:04 PM PDT 24
Finished Aug 04 05:26:06 PM PDT 24
Peak memory 240768 kb
Host smart-08383af3-5c23-4368-ba16-b011104d7399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939310925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.939310925
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3372391300
Short name T26
Test name
Test status
Simulation time 619828629 ps
CPU time 10.72 seconds
Started Aug 04 05:25:59 PM PDT 24
Finished Aug 04 05:26:10 PM PDT 24
Peak memory 242756 kb
Host smart-7ac41fa3-31d2-49f7-8845-1da1a89136e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372391300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3372391300
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.3431470827
Short name T724
Test name
Test status
Simulation time 612244682 ps
CPU time 7.73 seconds
Started Aug 04 05:26:00 PM PDT 24
Finished Aug 04 05:26:08 PM PDT 24
Peak memory 241920 kb
Host smart-5cd00b99-c836-4562-bb25-19dc7fa95a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431470827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3431470827
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.2447943036
Short name T550
Test name
Test status
Simulation time 18354827026 ps
CPU time 21.3 seconds
Started Aug 04 05:26:03 PM PDT 24
Finished Aug 04 05:26:24 PM PDT 24
Peak memory 241848 kb
Host smart-8a82bd7f-9427-419e-ad03-1b32bf87d2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447943036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.2447943036
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.4186483259
Short name T118
Test name
Test status
Simulation time 535639314 ps
CPU time 4.22 seconds
Started Aug 04 05:26:00 PM PDT 24
Finished Aug 04 05:26:04 PM PDT 24
Peak memory 242412 kb
Host smart-23edbc6c-7848-41a3-a5d6-a76b4d1acead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186483259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.4186483259
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.319476590
Short name T375
Test name
Test status
Simulation time 556316372 ps
CPU time 6.23 seconds
Started Aug 04 05:25:59 PM PDT 24
Finished Aug 04 05:26:05 PM PDT 24
Peak memory 241932 kb
Host smart-bc176a72-0baa-41f7-bcb1-952a867cc188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319476590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.319476590
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.142016267
Short name T360
Test name
Test status
Simulation time 4690337264 ps
CPU time 35.72 seconds
Started Aug 04 05:26:01 PM PDT 24
Finished Aug 04 05:26:37 PM PDT 24
Peak memory 243164 kb
Host smart-50a34cf5-2372-4058-9407-9e470f5cbfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142016267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.142016267
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.1557512540
Short name T920
Test name
Test status
Simulation time 575763478 ps
CPU time 8.37 seconds
Started Aug 04 05:25:59 PM PDT 24
Finished Aug 04 05:26:07 PM PDT 24
Peak memory 242028 kb
Host smart-cd07d502-17b2-4b32-bcda-01e271b21826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557512540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.1557512540
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.3036242526
Short name T325
Test name
Test status
Simulation time 385566027 ps
CPU time 7.27 seconds
Started Aug 04 05:25:59 PM PDT 24
Finished Aug 04 05:26:07 PM PDT 24
Peak memory 242048 kb
Host smart-c73651e8-a2a7-4ac2-b4a3-920bff699fbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3036242526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3036242526
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1612445811
Short name T500
Test name
Test status
Simulation time 757012492 ps
CPU time 5.88 seconds
Started Aug 04 05:26:00 PM PDT 24
Finished Aug 04 05:26:06 PM PDT 24
Peak memory 248496 kb
Host smart-0f2cd3fd-be8a-42a1-9276-20f86a07e51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612445811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1612445811
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.2386537209
Short name T776
Test name
Test status
Simulation time 37605078306 ps
CPU time 163.89 seconds
Started Aug 04 05:26:04 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 244928 kb
Host smart-015bd2db-2485-4f72-969c-62279f6b063f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386537209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.2386537209
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.4168851725
Short name T241
Test name
Test status
Simulation time 1073322327768 ps
CPU time 1680.48 seconds
Started Aug 04 05:26:02 PM PDT 24
Finished Aug 04 05:54:03 PM PDT 24
Peak memory 296732 kb
Host smart-0548afc2-0316-452f-aee2-dc8b2b27e08b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168851725 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.4168851725
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.1370099231
Short name T568
Test name
Test status
Simulation time 965386133 ps
CPU time 17.11 seconds
Started Aug 04 05:26:02 PM PDT 24
Finished Aug 04 05:26:19 PM PDT 24
Peak memory 242260 kb
Host smart-dd7cdfa3-ce07-45b3-93af-d17e259b4ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370099231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.1370099231
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.4290765886
Short name T181
Test name
Test status
Simulation time 90552739 ps
CPU time 2.28 seconds
Started Aug 04 05:26:03 PM PDT 24
Finished Aug 04 05:26:05 PM PDT 24
Peak memory 240708 kb
Host smart-b1f7baaf-e5ba-49ec-a34d-7ca1d2c1f5b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290765886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.4290765886
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.3152550627
Short name T83
Test name
Test status
Simulation time 1583080329 ps
CPU time 21.64 seconds
Started Aug 04 05:26:06 PM PDT 24
Finished Aug 04 05:26:29 PM PDT 24
Peak memory 242076 kb
Host smart-9d91b3d0-8496-4620-a6d1-10e5c4aeaa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152550627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.3152550627
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.1521531702
Short name T394
Test name
Test status
Simulation time 290337969 ps
CPU time 14.53 seconds
Started Aug 04 05:26:06 PM PDT 24
Finished Aug 04 05:26:21 PM PDT 24
Peak memory 242100 kb
Host smart-bc852759-d1b0-4d3b-a1b9-cacaea364c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521531702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1521531702
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.867114338
Short name T252
Test name
Test status
Simulation time 638177796 ps
CPU time 22.97 seconds
Started Aug 04 05:26:04 PM PDT 24
Finished Aug 04 05:26:27 PM PDT 24
Peak memory 242680 kb
Host smart-515a3152-490b-4748-87b2-611ca7cffe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867114338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.867114338
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.1913167914
Short name T689
Test name
Test status
Simulation time 2455277375 ps
CPU time 4.55 seconds
Started Aug 04 05:26:04 PM PDT 24
Finished Aug 04 05:26:09 PM PDT 24
Peak memory 242288 kb
Host smart-c1dd19c4-989b-4fad-b45c-e9783c3c03a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913167914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1913167914
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.1863486956
Short name T189
Test name
Test status
Simulation time 1660243053 ps
CPU time 23.44 seconds
Started Aug 04 05:26:03 PM PDT 24
Finished Aug 04 05:26:27 PM PDT 24
Peak memory 248564 kb
Host smart-f5935508-37ce-44cb-a1c3-c4afcaf46c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863486956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.1863486956
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.2444352775
Short name T760
Test name
Test status
Simulation time 851765006 ps
CPU time 38.89 seconds
Started Aug 04 05:26:05 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 242032 kb
Host smart-e16e2d65-9142-4a3e-b97d-fcfabc118fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444352775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2444352775
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.1035660218
Short name T305
Test name
Test status
Simulation time 1056238393 ps
CPU time 28.48 seconds
Started Aug 04 05:26:06 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 242016 kb
Host smart-742c1436-4ffa-4180-87b5-e5a2ec8c74d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035660218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1035660218
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1817377429
Short name T666
Test name
Test status
Simulation time 13462304621 ps
CPU time 33.61 seconds
Started Aug 04 05:26:05 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 242032 kb
Host smart-fc35b4f7-6e22-4e47-9319-3de9276eba36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817377429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1817377429
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.167656409
Short name T199
Test name
Test status
Simulation time 137137634 ps
CPU time 4.77 seconds
Started Aug 04 05:26:06 PM PDT 24
Finished Aug 04 05:26:11 PM PDT 24
Peak memory 241992 kb
Host smart-6ae7a98e-98ad-471c-90f0-57e0f02c1088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167656409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.167656409
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.2186743120
Short name T1153
Test name
Test status
Simulation time 551507506 ps
CPU time 8.79 seconds
Started Aug 04 05:26:03 PM PDT 24
Finished Aug 04 05:26:11 PM PDT 24
Peak memory 241988 kb
Host smart-4ce62335-f830-4bae-9644-c5948828f155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186743120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2186743120
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.2140757693
Short name T249
Test name
Test status
Simulation time 19274057422 ps
CPU time 156.23 seconds
Started Aug 04 05:26:04 PM PDT 24
Finished Aug 04 05:28:40 PM PDT 24
Peak memory 249644 kb
Host smart-8e6fa8ad-05a8-48c3-9b27-dd124799cb81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140757693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.2140757693
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.2548647389
Short name T251
Test name
Test status
Simulation time 9789177767 ps
CPU time 19.16 seconds
Started Aug 04 05:26:04 PM PDT 24
Finished Aug 04 05:26:23 PM PDT 24
Peak memory 242076 kb
Host smart-263f7e8e-7bb8-4533-9c40-92f6d4ab4a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548647389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.2548647389
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.2765339929
Short name T294
Test name
Test status
Simulation time 222749113 ps
CPU time 1.85 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:24:49 PM PDT 24
Peak memory 240680 kb
Host smart-8eaeeee6-5222-44d4-9c54-62f39d69fcaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765339929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2765339929
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.3584186496
Short name T638
Test name
Test status
Simulation time 2115702188 ps
CPU time 26.27 seconds
Started Aug 04 05:24:35 PM PDT 24
Finished Aug 04 05:25:02 PM PDT 24
Peak memory 242260 kb
Host smart-7edaa080-66f7-4eb6-a52b-09e1e2950f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584186496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.3584186496
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.3439846914
Short name T49
Test name
Test status
Simulation time 401183941 ps
CPU time 11.26 seconds
Started Aug 04 05:24:36 PM PDT 24
Finished Aug 04 05:24:48 PM PDT 24
Peak memory 248576 kb
Host smart-69904fee-cd4e-44af-a71b-0e2bf2dbf5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439846914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.3439846914
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.416415895
Short name T857
Test name
Test status
Simulation time 360878113 ps
CPU time 17.48 seconds
Started Aug 04 05:24:36 PM PDT 24
Finished Aug 04 05:24:54 PM PDT 24
Peak memory 242176 kb
Host smart-6b73486e-22af-4486-ad36-01e34486e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416415895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.416415895
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.1210467
Short name T356
Test name
Test status
Simulation time 2011457012 ps
CPU time 18.94 seconds
Started Aug 04 05:24:37 PM PDT 24
Finished Aug 04 05:24:56 PM PDT 24
Peak memory 242432 kb
Host smart-c92064bc-e1d5-4354-99a5-98d4ad2430b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1210467
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.2555296972
Short name T700
Test name
Test status
Simulation time 287482842 ps
CPU time 4.98 seconds
Started Aug 04 05:24:35 PM PDT 24
Finished Aug 04 05:24:40 PM PDT 24
Peak memory 242084 kb
Host smart-fba5bb22-7973-4054-928c-95aa9746b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555296972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.2555296972
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.1408350962
Short name T886
Test name
Test status
Simulation time 14058535230 ps
CPU time 30.65 seconds
Started Aug 04 05:24:35 PM PDT 24
Finished Aug 04 05:25:06 PM PDT 24
Peak memory 242572 kb
Host smart-df53278e-de05-4e18-8df4-ddf5af1f884b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408350962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1408350962
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.484437906
Short name T603
Test name
Test status
Simulation time 2598060174 ps
CPU time 19.2 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:25:06 PM PDT 24
Peak memory 241904 kb
Host smart-d246dc9e-74fe-4242-a06a-b4ef19cf980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484437906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.484437906
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.3967336203
Short name T454
Test name
Test status
Simulation time 146403721 ps
CPU time 4.07 seconds
Started Aug 04 05:24:35 PM PDT 24
Finished Aug 04 05:24:39 PM PDT 24
Peak memory 241916 kb
Host smart-d8472706-2762-46c6-b5ea-d4f10d73a216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967336203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.3967336203
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.490019367
Short name T514
Test name
Test status
Simulation time 769079388 ps
CPU time 11.52 seconds
Started Aug 04 05:24:36 PM PDT 24
Finished Aug 04 05:24:47 PM PDT 24
Peak memory 241976 kb
Host smart-4febe35d-e8d7-4119-89ae-61a4d9528c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=490019367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.490019367
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.2990012405
Short name T933
Test name
Test status
Simulation time 525356724 ps
CPU time 5.71 seconds
Started Aug 04 05:24:39 PM PDT 24
Finished Aug 04 05:24:44 PM PDT 24
Peak memory 242428 kb
Host smart-6c4a2016-cd37-43ec-bbdd-9abaa1abfc56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990012405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.2990012405
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.2368590703
Short name T218
Test name
Test status
Simulation time 169906823964 ps
CPU time 272.36 seconds
Started Aug 04 05:24:39 PM PDT 24
Finished Aug 04 05:29:11 PM PDT 24
Peak memory 270824 kb
Host smart-8405ab3d-fd0b-4d06-8003-ad835651b417
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368590703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.2368590703
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.2092979637
Short name T1095
Test name
Test status
Simulation time 443847403 ps
CPU time 7.88 seconds
Started Aug 04 05:24:37 PM PDT 24
Finished Aug 04 05:24:44 PM PDT 24
Peak memory 241928 kb
Host smart-abb002fa-b43a-4ab4-b6e5-2b1be7a72426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092979637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.2092979637
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.490374087
Short name T1163
Test name
Test status
Simulation time 305629553 ps
CPU time 9.81 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:24:57 PM PDT 24
Peak memory 242068 kb
Host smart-73598865-6076-4c71-9fe2-fddcf7763915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490374087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.490374087
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.249013037
Short name T579
Test name
Test status
Simulation time 188861712 ps
CPU time 1.99 seconds
Started Aug 04 05:26:06 PM PDT 24
Finished Aug 04 05:26:09 PM PDT 24
Peak memory 240248 kb
Host smart-a419c35b-d901-410a-93a5-159751fc574f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249013037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.249013037
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.379383131
Short name T56
Test name
Test status
Simulation time 984373094 ps
CPU time 23.12 seconds
Started Aug 04 05:26:02 PM PDT 24
Finished Aug 04 05:26:25 PM PDT 24
Peak memory 243496 kb
Host smart-3b242c31-9bc7-4845-8474-d05d37e7df83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379383131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.379383131
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.1925504378
Short name T158
Test name
Test status
Simulation time 1488785616 ps
CPU time 35.7 seconds
Started Aug 04 05:26:04 PM PDT 24
Finished Aug 04 05:26:40 PM PDT 24
Peak memory 242596 kb
Host smart-61795d08-0063-4a6b-81f4-1e2a29551d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925504378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.1925504378
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.1156408306
Short name T1065
Test name
Test status
Simulation time 16349329802 ps
CPU time 29.46 seconds
Started Aug 04 05:26:06 PM PDT 24
Finished Aug 04 05:26:35 PM PDT 24
Peak memory 243128 kb
Host smart-8592a171-f756-42c7-bb6e-a3fb868d69d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156408306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1156408306
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.2206705550
Short name T973
Test name
Test status
Simulation time 122051927 ps
CPU time 3.55 seconds
Started Aug 04 05:26:04 PM PDT 24
Finished Aug 04 05:26:08 PM PDT 24
Peak memory 242200 kb
Host smart-dec21b8e-580f-4c4e-b52e-9bf0b746c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206705550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.2206705550
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.387598564
Short name T946
Test name
Test status
Simulation time 4032084061 ps
CPU time 14 seconds
Started Aug 04 05:26:06 PM PDT 24
Finished Aug 04 05:26:21 PM PDT 24
Peak memory 242084 kb
Host smart-fa4f3863-2927-4deb-9607-cfdc1e42e8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387598564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.387598564
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.2115427804
Short name T464
Test name
Test status
Simulation time 143219347 ps
CPU time 3.84 seconds
Started Aug 04 05:26:03 PM PDT 24
Finished Aug 04 05:26:07 PM PDT 24
Peak memory 242292 kb
Host smart-89998b62-8472-49ae-b508-fa3ca9a46661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115427804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.2115427804
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.2889089841
Short name T918
Test name
Test status
Simulation time 4440620257 ps
CPU time 11.54 seconds
Started Aug 04 05:26:07 PM PDT 24
Finished Aug 04 05:26:19 PM PDT 24
Peak memory 241900 kb
Host smart-807c1b68-3157-4225-8434-8bb5dbff03ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889089841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.2889089841
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1540043769
Short name T165
Test name
Test status
Simulation time 827639088 ps
CPU time 23.01 seconds
Started Aug 04 05:26:05 PM PDT 24
Finished Aug 04 05:26:28 PM PDT 24
Peak memory 241844 kb
Host smart-9ee5b35d-da29-4797-9e68-4dbc59d42244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540043769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1540043769
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.1746141260
Short name T109
Test name
Test status
Simulation time 624905112 ps
CPU time 7.73 seconds
Started Aug 04 05:26:05 PM PDT 24
Finished Aug 04 05:26:14 PM PDT 24
Peak memory 242128 kb
Host smart-c8249dcc-d1ce-422b-b568-fc9d8cfcec1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746141260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1746141260
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.416265210
Short name T11
Test name
Test status
Simulation time 762906459 ps
CPU time 5.47 seconds
Started Aug 04 05:26:07 PM PDT 24
Finished Aug 04 05:26:13 PM PDT 24
Peak memory 248436 kb
Host smart-a3df7c01-991d-40a8-8257-5d18715ad45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416265210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.416265210
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.1197757326
Short name T737
Test name
Test status
Simulation time 8855579254 ps
CPU time 201.92 seconds
Started Aug 04 05:26:06 PM PDT 24
Finished Aug 04 05:29:28 PM PDT 24
Peak memory 272188 kb
Host smart-d379caa8-3bf4-45c9-aabe-715f8a7a32e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197757326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.1197757326
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.2843959619
Short name T297
Test name
Test status
Simulation time 112770087241 ps
CPU time 1819.03 seconds
Started Aug 04 05:26:05 PM PDT 24
Finished Aug 04 05:56:24 PM PDT 24
Peak memory 539324 kb
Host smart-57014f78-d7cb-4d6f-a5f0-fe38de87b44a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843959619 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.2843959619
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.2799453040
Short name T802
Test name
Test status
Simulation time 615548455 ps
CPU time 11.04 seconds
Started Aug 04 05:26:04 PM PDT 24
Finished Aug 04 05:26:16 PM PDT 24
Peak memory 241832 kb
Host smart-898b9ecc-3611-499f-82b7-14b58dd1ced9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799453040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2799453040
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.4023510085
Short name T567
Test name
Test status
Simulation time 1037256309 ps
CPU time 2.33 seconds
Started Aug 04 05:26:09 PM PDT 24
Finished Aug 04 05:26:11 PM PDT 24
Peak memory 240500 kb
Host smart-a68259ab-b16a-47e7-84fb-85e445dce0bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023510085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.4023510085
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.3494591302
Short name T1008
Test name
Test status
Simulation time 1789674135 ps
CPU time 18.07 seconds
Started Aug 04 05:26:09 PM PDT 24
Finished Aug 04 05:26:27 PM PDT 24
Peak memory 242096 kb
Host smart-0d61a087-c003-43e3-a06a-65ff5284e436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494591302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.3494591302
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.1708974832
Short name T906
Test name
Test status
Simulation time 1008900702 ps
CPU time 17.14 seconds
Started Aug 04 05:26:07 PM PDT 24
Finished Aug 04 05:26:24 PM PDT 24
Peak memory 242020 kb
Host smart-cfb3a764-e877-449e-8902-e5d8f18256f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708974832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1708974832
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.1763261626
Short name T531
Test name
Test status
Simulation time 16133926403 ps
CPU time 33.38 seconds
Started Aug 04 05:26:08 PM PDT 24
Finished Aug 04 05:26:42 PM PDT 24
Peak memory 242984 kb
Host smart-7f593202-a359-4148-b787-d40733b98561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763261626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.1763261626
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.237846177
Short name T853
Test name
Test status
Simulation time 119149865 ps
CPU time 4.19 seconds
Started Aug 04 05:26:08 PM PDT 24
Finished Aug 04 05:26:13 PM PDT 24
Peak memory 241924 kb
Host smart-894bf8cf-0479-49e4-855a-2dbb3b927162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237846177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.237846177
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.4285356453
Short name T476
Test name
Test status
Simulation time 1472220916 ps
CPU time 14.41 seconds
Started Aug 04 05:26:06 PM PDT 24
Finished Aug 04 05:26:22 PM PDT 24
Peak memory 248408 kb
Host smart-26d0620b-2480-4afe-99c6-4982809865ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285356453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.4285356453
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.2870543198
Short name T1132
Test name
Test status
Simulation time 432225850 ps
CPU time 15.29 seconds
Started Aug 04 05:26:09 PM PDT 24
Finished Aug 04 05:26:25 PM PDT 24
Peak memory 242144 kb
Host smart-f1cbd425-df8c-4779-a293-acaddbe33af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870543198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.2870543198
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.7455525
Short name T938
Test name
Test status
Simulation time 1226116269 ps
CPU time 29.04 seconds
Started Aug 04 05:26:08 PM PDT 24
Finished Aug 04 05:26:38 PM PDT 24
Peak memory 241864 kb
Host smart-87eeb64d-d127-41df-bfcc-f38a3e8cfd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7455525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.7455525
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.3093293619
Short name T34
Test name
Test status
Simulation time 1524942033 ps
CPU time 23.28 seconds
Started Aug 04 05:26:08 PM PDT 24
Finished Aug 04 05:26:32 PM PDT 24
Peak memory 241996 kb
Host smart-f3998967-1583-4446-92db-b90a5ce3d2e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093293619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.3093293619
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.3390807177
Short name T558
Test name
Test status
Simulation time 267271755 ps
CPU time 5.1 seconds
Started Aug 04 05:26:10 PM PDT 24
Finished Aug 04 05:26:15 PM PDT 24
Peak memory 242220 kb
Host smart-3c108be6-9cf5-4780-a29e-eac57728e2e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390807177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3390807177
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.609118884
Short name T1088
Test name
Test status
Simulation time 259567930 ps
CPU time 4.33 seconds
Started Aug 04 05:26:07 PM PDT 24
Finished Aug 04 05:26:12 PM PDT 24
Peak memory 242156 kb
Host smart-db4b8c5b-9ac6-480d-8d4a-7a6c3d44b428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609118884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.609118884
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1591927174
Short name T260
Test name
Test status
Simulation time 40257281159 ps
CPU time 808.73 seconds
Started Aug 04 05:26:08 PM PDT 24
Finished Aug 04 05:39:38 PM PDT 24
Peak memory 298556 kb
Host smart-fac85de6-fabb-4d43-9488-a1bda7c41965
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591927174 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.1591927174
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.1736474738
Short name T99
Test name
Test status
Simulation time 437497554 ps
CPU time 13.36 seconds
Started Aug 04 05:26:07 PM PDT 24
Finished Aug 04 05:26:21 PM PDT 24
Peak memory 242320 kb
Host smart-e99a8209-8e34-4ca4-916b-b11cdff12c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736474738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1736474738
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.1328805464
Short name T626
Test name
Test status
Simulation time 237819769 ps
CPU time 2.01 seconds
Started Aug 04 05:26:15 PM PDT 24
Finished Aug 04 05:26:18 PM PDT 24
Peak memory 240416 kb
Host smart-177c76bc-dbad-4b4d-8b9f-ed1276a09060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328805464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1328805464
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.895594042
Short name T893
Test name
Test status
Simulation time 525782830 ps
CPU time 10.64 seconds
Started Aug 04 05:26:12 PM PDT 24
Finished Aug 04 05:26:22 PM PDT 24
Peak memory 241932 kb
Host smart-fdeff06e-5482-48ea-907f-7ad8b0eaa70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895594042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.895594042
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.473457935
Short name T541
Test name
Test status
Simulation time 510803983 ps
CPU time 13.17 seconds
Started Aug 04 05:26:09 PM PDT 24
Finished Aug 04 05:26:22 PM PDT 24
Peak memory 242300 kb
Host smart-c8c1cef8-5005-4893-8e06-6ab9453d6749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473457935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.473457935
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3389374076
Short name T1069
Test name
Test status
Simulation time 260529116 ps
CPU time 9.21 seconds
Started Aug 04 05:26:07 PM PDT 24
Finished Aug 04 05:26:16 PM PDT 24
Peak memory 242148 kb
Host smart-d1cf57b7-ad3c-46e3-aee3-2f695f57bc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389374076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3389374076
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.4078264902
Short name T160
Test name
Test status
Simulation time 196855998 ps
CPU time 4.27 seconds
Started Aug 04 05:26:07 PM PDT 24
Finished Aug 04 05:26:11 PM PDT 24
Peak memory 242120 kb
Host smart-e29650ab-91b8-452d-83bd-d9c26de84024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078264902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.4078264902
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.994775084
Short name T1060
Test name
Test status
Simulation time 652990544 ps
CPU time 17.86 seconds
Started Aug 04 05:26:18 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 246432 kb
Host smart-ddb44449-1d11-4926-a679-9b742a0a44ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994775084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.994775084
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.502698208
Short name T1082
Test name
Test status
Simulation time 1287844118 ps
CPU time 29.39 seconds
Started Aug 04 05:26:15 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 242228 kb
Host smart-a06899e9-e14b-4305-91af-d36442f6f830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502698208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.502698208
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.1420949922
Short name T427
Test name
Test status
Simulation time 4507514683 ps
CPU time 34.9 seconds
Started Aug 04 05:26:10 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 242892 kb
Host smart-7583f9c5-afcc-4cfc-af72-7e39c00b6ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420949922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1420949922
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.214181073
Short name T4
Test name
Test status
Simulation time 190174721 ps
CPU time 5.47 seconds
Started Aug 04 05:26:07 PM PDT 24
Finished Aug 04 05:26:13 PM PDT 24
Peak memory 242016 kb
Host smart-5b655fab-fbec-4a5b-8da0-cd02f398947c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=214181073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.214181073
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3145586113
Short name T1019
Test name
Test status
Simulation time 290855688 ps
CPU time 3.1 seconds
Started Aug 04 05:26:11 PM PDT 24
Finished Aug 04 05:26:15 PM PDT 24
Peak memory 241996 kb
Host smart-dec36094-f529-46b9-bfa4-0523cd79554b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145586113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3145586113
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.2434338270
Short name T458
Test name
Test status
Simulation time 134983571 ps
CPU time 3.19 seconds
Started Aug 04 05:26:08 PM PDT 24
Finished Aug 04 05:26:12 PM PDT 24
Peak memory 242260 kb
Host smart-71355485-acf1-4f90-b278-d3b4d77f893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434338270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2434338270
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.3333562341
Short name T135
Test name
Test status
Simulation time 11617485417 ps
CPU time 158.86 seconds
Started Aug 04 05:26:15 PM PDT 24
Finished Aug 04 05:28:54 PM PDT 24
Peak memory 247332 kb
Host smart-f2518f5f-91ae-4df6-94e8-e70b40d8d811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333562341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.3333562341
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.2165036500
Short name T573
Test name
Test status
Simulation time 4459289448 ps
CPU time 13.97 seconds
Started Aug 04 05:26:14 PM PDT 24
Finished Aug 04 05:26:28 PM PDT 24
Peak memory 248580 kb
Host smart-9e53c191-6da7-411a-b75d-d517cdc7d9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165036500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2165036500
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.1351964074
Short name T751
Test name
Test status
Simulation time 735434419 ps
CPU time 1.78 seconds
Started Aug 04 05:26:12 PM PDT 24
Finished Aug 04 05:26:14 PM PDT 24
Peak memory 240748 kb
Host smart-1ba74ae7-3725-4e14-bb61-1016c13f1e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351964074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.1351964074
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.1606907874
Short name T453
Test name
Test status
Simulation time 238398562 ps
CPU time 7.86 seconds
Started Aug 04 05:26:11 PM PDT 24
Finished Aug 04 05:26:19 PM PDT 24
Peak memory 242236 kb
Host smart-6c018a35-9823-4431-8784-a8a24550738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606907874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1606907874
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.3704142243
Short name T532
Test name
Test status
Simulation time 393951582 ps
CPU time 10.16 seconds
Started Aug 04 05:26:11 PM PDT 24
Finished Aug 04 05:26:22 PM PDT 24
Peak memory 242312 kb
Host smart-2d2af190-66e4-45d6-a492-b9e89b6fdffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704142243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.3704142243
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.2619893160
Short name T736
Test name
Test status
Simulation time 625711269 ps
CPU time 11.14 seconds
Started Aug 04 05:26:12 PM PDT 24
Finished Aug 04 05:26:23 PM PDT 24
Peak memory 242424 kb
Host smart-bcd21916-6667-4c73-8337-8c1e63e1b237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619893160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.2619893160
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.486384880
Short name T177
Test name
Test status
Simulation time 116907329 ps
CPU time 4.24 seconds
Started Aug 04 05:26:15 PM PDT 24
Finished Aug 04 05:26:20 PM PDT 24
Peak memory 242200 kb
Host smart-73dd366b-62d0-4832-a5da-2052a733d7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486384880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.486384880
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.3909976794
Short name T922
Test name
Test status
Simulation time 2770739679 ps
CPU time 31.26 seconds
Started Aug 04 05:26:11 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 245228 kb
Host smart-476e7005-eaf0-4206-882c-203ae341947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909976794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.3909976794
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.3377723920
Short name T345
Test name
Test status
Simulation time 568475905 ps
CPU time 26 seconds
Started Aug 04 05:26:15 PM PDT 24
Finished Aug 04 05:26:42 PM PDT 24
Peak memory 241976 kb
Host smart-22bcb05f-498a-4da2-b33a-baf2f44de30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377723920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.3377723920
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.3069120870
Short name T336
Test name
Test status
Simulation time 455458886 ps
CPU time 12.65 seconds
Started Aug 04 05:26:11 PM PDT 24
Finished Aug 04 05:26:24 PM PDT 24
Peak memory 242108 kb
Host smart-4bce9569-cff6-4af5-a681-2d06385e9578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069120870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3069120870
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.1718833503
Short name T822
Test name
Test status
Simulation time 377394124 ps
CPU time 13.74 seconds
Started Aug 04 05:26:14 PM PDT 24
Finished Aug 04 05:26:28 PM PDT 24
Peak memory 248580 kb
Host smart-cf4fdb35-17f5-4fb2-83c6-1e6649b830d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1718833503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1718833503
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.2859927134
Short name T326
Test name
Test status
Simulation time 4552868343 ps
CPU time 15.44 seconds
Started Aug 04 05:26:12 PM PDT 24
Finished Aug 04 05:26:27 PM PDT 24
Peak memory 242384 kb
Host smart-d24e1c0e-dff5-40c5-b5df-0954450966d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859927134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2859927134
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.4126593022
Short name T398
Test name
Test status
Simulation time 385838682 ps
CPU time 5.7 seconds
Started Aug 04 05:26:15 PM PDT 24
Finished Aug 04 05:26:21 PM PDT 24
Peak memory 241968 kb
Host smart-4cf7a477-aae6-4335-928e-c2341ad82061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126593022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.4126593022
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.4235003262
Short name T344
Test name
Test status
Simulation time 7937709803 ps
CPU time 71.13 seconds
Started Aug 04 05:26:13 PM PDT 24
Finished Aug 04 05:27:25 PM PDT 24
Peak memory 247164 kb
Host smart-52eebe14-3f53-493a-af20-d3f96cc02fd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235003262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.4235003262
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.190296144
Short name T221
Test name
Test status
Simulation time 1089631988508 ps
CPU time 2336.45 seconds
Started Aug 04 05:26:14 PM PDT 24
Finished Aug 04 06:05:10 PM PDT 24
Peak memory 277672 kb
Host smart-fadafb96-bd06-4ac3-9409-bcc366c261aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190296144 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.190296144
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.2208808008
Short name T1117
Test name
Test status
Simulation time 6952825051 ps
CPU time 38.21 seconds
Started Aug 04 05:26:14 PM PDT 24
Finished Aug 04 05:26:52 PM PDT 24
Peak memory 241828 kb
Host smart-becd3b9e-03db-4820-ba6c-cdee04c64148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208808008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2208808008
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.3012019630
Short name T434
Test name
Test status
Simulation time 88341809 ps
CPU time 1.64 seconds
Started Aug 04 05:26:16 PM PDT 24
Finished Aug 04 05:26:18 PM PDT 24
Peak memory 240844 kb
Host smart-c6642a86-410b-41d3-a963-b77dd1ea8593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012019630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3012019630
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.1499034046
Short name T1162
Test name
Test status
Simulation time 172457861 ps
CPU time 4.86 seconds
Started Aug 04 05:26:16 PM PDT 24
Finished Aug 04 05:26:21 PM PDT 24
Peak memory 241696 kb
Host smart-24dfcb5a-b222-4d17-ba65-5e0cd5a2907a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499034046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1499034046
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.1271343345
Short name T889
Test name
Test status
Simulation time 1938551298 ps
CPU time 30.86 seconds
Started Aug 04 05:26:14 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 245752 kb
Host smart-8d19743a-38c8-42c0-b7ab-907929598706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271343345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1271343345
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.106375567
Short name T1135
Test name
Test status
Simulation time 1097988867 ps
CPU time 22.32 seconds
Started Aug 04 05:26:17 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 242076 kb
Host smart-baeb37d6-6850-47da-a7c6-d4a01f6c2e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106375567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.106375567
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.386707696
Short name T543
Test name
Test status
Simulation time 340778487 ps
CPU time 5.06 seconds
Started Aug 04 05:26:11 PM PDT 24
Finished Aug 04 05:26:16 PM PDT 24
Peak memory 242008 kb
Host smart-238c09ef-f83a-4c13-9154-75412caad036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386707696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.386707696
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.4229282788
Short name T955
Test name
Test status
Simulation time 6432214924 ps
CPU time 41.54 seconds
Started Aug 04 05:26:18 PM PDT 24
Finished Aug 04 05:26:59 PM PDT 24
Peak memory 245600 kb
Host smart-92ea6e6d-cfe1-4230-bcfd-5ae9eb8722ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229282788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.4229282788
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.1661440124
Short name T224
Test name
Test status
Simulation time 2405907563 ps
CPU time 16.92 seconds
Started Aug 04 05:26:18 PM PDT 24
Finished Aug 04 05:26:35 PM PDT 24
Peak memory 242496 kb
Host smart-c2761924-7113-4b07-b242-af1837095888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661440124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1661440124
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.2014965285
Short name T346
Test name
Test status
Simulation time 1586318996 ps
CPU time 25.25 seconds
Started Aug 04 05:26:13 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 242088 kb
Host smart-9a54aa30-4459-4235-982a-5ae9c7ec7292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014965285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2014965285
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.3334791200
Short name T869
Test name
Test status
Simulation time 587700876 ps
CPU time 10.87 seconds
Started Aug 04 05:26:17 PM PDT 24
Finished Aug 04 05:26:28 PM PDT 24
Peak memory 242152 kb
Host smart-60223c93-3ef6-433b-828a-dca3e4620fd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3334791200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3334791200
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.1180060766
Short name T420
Test name
Test status
Simulation time 330859306 ps
CPU time 5.56 seconds
Started Aug 04 05:26:12 PM PDT 24
Finished Aug 04 05:26:18 PM PDT 24
Peak memory 241880 kb
Host smart-e267f0af-15fe-47d7-9c32-0a40f8901983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180060766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1180060766
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.3808916798
Short name T924
Test name
Test status
Simulation time 32057219473 ps
CPU time 185.53 seconds
Started Aug 04 05:26:16 PM PDT 24
Finished Aug 04 05:29:22 PM PDT 24
Peak memory 249168 kb
Host smart-18b22135-b31e-45db-8d31-5e9504ffaddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808916798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.3808916798
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.1721796460
Short name T870
Test name
Test status
Simulation time 237159013889 ps
CPU time 632.99 seconds
Started Aug 04 05:26:17 PM PDT 24
Finished Aug 04 05:36:50 PM PDT 24
Peak memory 256880 kb
Host smart-deec3425-d9f6-4931-aa3a-7371805bbe2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721796460 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.1721796460
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.3182839723
Short name T578
Test name
Test status
Simulation time 9331126151 ps
CPU time 22.07 seconds
Started Aug 04 05:26:15 PM PDT 24
Finished Aug 04 05:26:38 PM PDT 24
Peak memory 242984 kb
Host smart-67164c3a-4add-4b14-b6ba-a48c67224ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182839723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3182839723
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.2760260993
Short name T585
Test name
Test status
Simulation time 217824397 ps
CPU time 1.79 seconds
Started Aug 04 05:26:20 PM PDT 24
Finished Aug 04 05:26:22 PM PDT 24
Peak memory 240360 kb
Host smart-fe68820a-fb51-416b-a998-a013befffefd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760260993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.2760260993
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.3509298477
Short name T569
Test name
Test status
Simulation time 3103317252 ps
CPU time 11.53 seconds
Started Aug 04 05:26:13 PM PDT 24
Finished Aug 04 05:26:25 PM PDT 24
Peak memory 242036 kb
Host smart-99f6071e-25b7-4d89-a625-a398c80a9449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509298477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.3509298477
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.1579274012
Short name T775
Test name
Test status
Simulation time 1127940486 ps
CPU time 33.08 seconds
Started Aug 04 05:26:15 PM PDT 24
Finished Aug 04 05:26:49 PM PDT 24
Peak memory 242496 kb
Host smart-23f49c45-8a09-4dd3-a4d1-4000f3fbaa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579274012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1579274012
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.1508184905
Short name T21
Test name
Test status
Simulation time 199302089 ps
CPU time 4.02 seconds
Started Aug 04 05:26:16 PM PDT 24
Finished Aug 04 05:26:20 PM PDT 24
Peak memory 242408 kb
Host smart-b5a7d007-20e9-4851-b6b5-b00cf5299908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508184905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1508184905
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.4180479168
Short name T655
Test name
Test status
Simulation time 3482416571 ps
CPU time 8.33 seconds
Started Aug 04 05:26:15 PM PDT 24
Finished Aug 04 05:26:23 PM PDT 24
Peak memory 242052 kb
Host smart-f58cd7e8-3101-4e88-9a8a-d3395480fd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180479168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.4180479168
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.3146601733
Short name T366
Test name
Test status
Simulation time 3941544828 ps
CPU time 45.79 seconds
Started Aug 04 05:26:23 PM PDT 24
Finished Aug 04 05:27:09 PM PDT 24
Peak memory 242288 kb
Host smart-7905fe97-6412-449a-82ea-046bd6d0e8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146601733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3146601733
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.112577806
Short name T222
Test name
Test status
Simulation time 1855104602 ps
CPU time 11.63 seconds
Started Aug 04 05:26:16 PM PDT 24
Finished Aug 04 05:26:28 PM PDT 24
Peak memory 241704 kb
Host smart-6b33ffb3-f4de-4ba1-b400-d109e7ad77fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112577806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.112577806
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.2036782151
Short name T1143
Test name
Test status
Simulation time 3005076033 ps
CPU time 7.39 seconds
Started Aug 04 05:26:13 PM PDT 24
Finished Aug 04 05:26:21 PM PDT 24
Peak memory 248712 kb
Host smart-d5298c4b-f057-44d7-9ab9-e0040b51ce14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2036782151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.2036782151
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.434080252
Short name T597
Test name
Test status
Simulation time 246912987 ps
CPU time 7.5 seconds
Started Aug 04 05:26:24 PM PDT 24
Finished Aug 04 05:26:31 PM PDT 24
Peak memory 242260 kb
Host smart-1567ec37-0448-4b65-a82e-91c56b6c1f22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434080252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.434080252
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.3202923740
Short name T253
Test name
Test status
Simulation time 160346256 ps
CPU time 4.52 seconds
Started Aug 04 05:26:17 PM PDT 24
Finished Aug 04 05:26:21 PM PDT 24
Peak memory 241840 kb
Host smart-662be8b8-4f74-4c4c-8ea8-702f37a7e13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202923740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3202923740
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.721298731
Short name T66
Test name
Test status
Simulation time 17298234495 ps
CPU time 170.71 seconds
Started Aug 04 05:26:20 PM PDT 24
Finished Aug 04 05:29:11 PM PDT 24
Peak memory 248708 kb
Host smart-35704529-69d0-4267-98e9-a223c770b9dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721298731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.
721298731
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.19551073
Short name T33
Test name
Test status
Simulation time 152024723240 ps
CPU time 1396.16 seconds
Started Aug 04 05:26:24 PM PDT 24
Finished Aug 04 05:49:40 PM PDT 24
Peak memory 276436 kb
Host smart-fac084c9-6cb5-4a22-a811-4a9bab35c0e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19551073 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.19551073
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.2261821819
Short name T729
Test name
Test status
Simulation time 1785012599 ps
CPU time 21.02 seconds
Started Aug 04 05:26:24 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 241888 kb
Host smart-12afbf83-af7e-4e2e-a0e8-6c8d864a4fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261821819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.2261821819
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.1692058865
Short name T416
Test name
Test status
Simulation time 70517132 ps
CPU time 1.93 seconds
Started Aug 04 05:26:21 PM PDT 24
Finished Aug 04 05:26:23 PM PDT 24
Peak memory 240528 kb
Host smart-891d4fda-8f83-4a99-9aeb-b0633d0d21f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692058865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1692058865
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.3852282863
Short name T1125
Test name
Test status
Simulation time 2603163121 ps
CPU time 32.15 seconds
Started Aug 04 05:26:19 PM PDT 24
Finished Aug 04 05:26:51 PM PDT 24
Peak memory 242376 kb
Host smart-eab93b07-a591-49f3-aa65-f5c43c65e6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852282863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3852282863
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.4008434598
Short name T1122
Test name
Test status
Simulation time 4116650006 ps
CPU time 40.81 seconds
Started Aug 04 05:26:20 PM PDT 24
Finished Aug 04 05:27:01 PM PDT 24
Peak memory 242528 kb
Host smart-b046fdc1-f47a-4356-bed8-0eace2e459b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008434598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.4008434598
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.3740650267
Short name T593
Test name
Test status
Simulation time 254404841 ps
CPU time 3.88 seconds
Started Aug 04 05:26:21 PM PDT 24
Finished Aug 04 05:26:25 PM PDT 24
Peak memory 242392 kb
Host smart-3788c31a-53f7-4df9-b3fd-433a8cac8285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740650267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.3740650267
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.4209712454
Short name T9
Test name
Test status
Simulation time 125845936 ps
CPU time 4.01 seconds
Started Aug 04 05:26:21 PM PDT 24
Finished Aug 04 05:26:25 PM PDT 24
Peak memory 242380 kb
Host smart-1e30bab8-38e2-47a5-a649-16da8ab48285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209712454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.4209712454
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.1209879507
Short name T859
Test name
Test status
Simulation time 1507475642 ps
CPU time 11.31 seconds
Started Aug 04 05:26:20 PM PDT 24
Finished Aug 04 05:26:31 PM PDT 24
Peak memory 241832 kb
Host smart-39dcc1c3-9c8a-4c0f-bd22-79482157a8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209879507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1209879507
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.3681688138
Short name T602
Test name
Test status
Simulation time 557188323 ps
CPU time 4.47 seconds
Started Aug 04 05:26:18 PM PDT 24
Finished Aug 04 05:26:22 PM PDT 24
Peak memory 241884 kb
Host smart-25cf8708-131f-4d72-90d7-0b53ac081a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681688138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3681688138
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.1294362451
Short name T645
Test name
Test status
Simulation time 464721789 ps
CPU time 9.23 seconds
Started Aug 04 05:26:20 PM PDT 24
Finished Aug 04 05:26:30 PM PDT 24
Peak memory 242068 kb
Host smart-955d165e-aed7-46d0-acd2-783030530c2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294362451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1294362451
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.1785590728
Short name T708
Test name
Test status
Simulation time 401603104 ps
CPU time 4.64 seconds
Started Aug 04 05:26:19 PM PDT 24
Finished Aug 04 05:26:24 PM PDT 24
Peak memory 242308 kb
Host smart-ea0c1f09-c46e-4c57-8add-a034448e85aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785590728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.1785590728
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.33011905
Short name T378
Test name
Test status
Simulation time 4209703532 ps
CPU time 10.3 seconds
Started Aug 04 05:26:16 PM PDT 24
Finished Aug 04 05:26:26 PM PDT 24
Peak memory 242492 kb
Host smart-279e63f9-ab38-4ba5-9f54-00a73d363d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33011905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.33011905
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.434634194
Short name T364
Test name
Test status
Simulation time 10606400587 ps
CPU time 120.28 seconds
Started Aug 04 05:26:18 PM PDT 24
Finished Aug 04 05:28:18 PM PDT 24
Peak memory 248632 kb
Host smart-b3647fa6-f6df-496f-941e-039cf46930d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434634194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.
434634194
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3181781194
Short name T949
Test name
Test status
Simulation time 97373434201 ps
CPU time 1006.73 seconds
Started Aug 04 05:26:18 PM PDT 24
Finished Aug 04 05:43:05 PM PDT 24
Peak memory 314624 kb
Host smart-92194afb-18bb-4385-89ea-f051c599aef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181781194 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.3181781194
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.3579705700
Short name T807
Test name
Test status
Simulation time 11430317074 ps
CPU time 32.09 seconds
Started Aug 04 05:26:20 PM PDT 24
Finished Aug 04 05:26:52 PM PDT 24
Peak memory 242120 kb
Host smart-e77b745b-2aae-462c-be57-161cc7004925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579705700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.3579705700
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.3431257188
Short name T1169
Test name
Test status
Simulation time 281583595 ps
CPU time 2.24 seconds
Started Aug 04 05:26:24 PM PDT 24
Finished Aug 04 05:26:27 PM PDT 24
Peak memory 240860 kb
Host smart-b760640a-9d40-4135-9673-5454367f6ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431257188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3431257188
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.2241279069
Short name T69
Test name
Test status
Simulation time 464875488 ps
CPU time 10.43 seconds
Started Aug 04 05:26:19 PM PDT 24
Finished Aug 04 05:26:30 PM PDT 24
Peak memory 242472 kb
Host smart-2248bc1b-fcd9-41c1-ba59-6d7d3c8106d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241279069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.2241279069
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.3030618543
Short name T1178
Test name
Test status
Simulation time 1245184291 ps
CPU time 26.76 seconds
Started Aug 04 05:26:24 PM PDT 24
Finished Aug 04 05:26:51 PM PDT 24
Peak memory 242180 kb
Host smart-8e17fa71-b301-459a-bcf3-54df48c59717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030618543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3030618543
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.3228201964
Short name T358
Test name
Test status
Simulation time 569408760 ps
CPU time 9.34 seconds
Started Aug 04 05:26:19 PM PDT 24
Finished Aug 04 05:26:28 PM PDT 24
Peak memory 241964 kb
Host smart-9df2575b-ab91-4dfa-956c-4e0fd4aa5aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228201964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3228201964
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.2559264993
Short name T418
Test name
Test status
Simulation time 374646412 ps
CPU time 4.01 seconds
Started Aug 04 05:26:18 PM PDT 24
Finished Aug 04 05:26:22 PM PDT 24
Peak memory 242244 kb
Host smart-9acf970a-584d-4169-9f3f-00de8be05ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559264993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2559264993
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.33447126
Short name T851
Test name
Test status
Simulation time 2846087846 ps
CPU time 28.74 seconds
Started Aug 04 05:26:19 PM PDT 24
Finished Aug 04 05:26:48 PM PDT 24
Peak memory 248644 kb
Host smart-9d47f21b-8b10-4a09-ac3a-ea52d97f2202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33447126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.33447126
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.2866696036
Short name T357
Test name
Test status
Simulation time 1323208224 ps
CPU time 32.46 seconds
Started Aug 04 05:26:23 PM PDT 24
Finished Aug 04 05:26:56 PM PDT 24
Peak memory 242412 kb
Host smart-77a4a1f1-3be6-464f-827a-d4c764804a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866696036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2866696036
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.1361552699
Short name T1011
Test name
Test status
Simulation time 2668502996 ps
CPU time 4.71 seconds
Started Aug 04 05:26:18 PM PDT 24
Finished Aug 04 05:26:23 PM PDT 24
Peak memory 241872 kb
Host smart-2bcafa8e-73b1-4752-bfea-acd4c8a79cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361552699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1361552699
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.2260026984
Short name T1171
Test name
Test status
Simulation time 2035996656 ps
CPU time 15.32 seconds
Started Aug 04 05:26:24 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 241944 kb
Host smart-0456fa92-2af3-49e1-9ff5-303e933e2156
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260026984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2260026984
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.3652860938
Short name T507
Test name
Test status
Simulation time 1162293631 ps
CPU time 10.17 seconds
Started Aug 04 05:26:27 PM PDT 24
Finished Aug 04 05:26:38 PM PDT 24
Peak memory 241928 kb
Host smart-a52c0075-fca2-4a75-8025-c0d7d8918077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652860938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.3652860938
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.1882712882
Short name T433
Test name
Test status
Simulation time 2290736077 ps
CPU time 7.26 seconds
Started Aug 04 05:26:24 PM PDT 24
Finished Aug 04 05:26:31 PM PDT 24
Peak memory 242028 kb
Host smart-9fdc9a3d-ee6f-4346-b3dc-4048572fa0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882712882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1882712882
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.310169260
Short name T743
Test name
Test status
Simulation time 25881799503 ps
CPU time 282.07 seconds
Started Aug 04 05:26:27 PM PDT 24
Finished Aug 04 05:31:09 PM PDT 24
Peak memory 256828 kb
Host smart-49c696e7-d563-44af-8dd8-10fd4cbae97a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310169260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.
310169260
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.603038894
Short name T130
Test name
Test status
Simulation time 224226753223 ps
CPU time 2043.39 seconds
Started Aug 04 05:26:25 PM PDT 24
Finished Aug 04 06:00:29 PM PDT 24
Peak memory 609184 kb
Host smart-918b6b93-1682-4184-8e1f-0b155d792997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603038894 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.603038894
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.4156004954
Short name T1126
Test name
Test status
Simulation time 2324630828 ps
CPU time 26.47 seconds
Started Aug 04 05:26:22 PM PDT 24
Finished Aug 04 05:26:48 PM PDT 24
Peak memory 242032 kb
Host smart-30f08a46-8d15-426a-b355-41b5379af57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156004954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.4156004954
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.3682677609
Short name T372
Test name
Test status
Simulation time 75249925 ps
CPU time 1.94 seconds
Started Aug 04 05:26:22 PM PDT 24
Finished Aug 04 05:26:24 PM PDT 24
Peak memory 240376 kb
Host smart-7d1e7d88-e9ab-42ef-98a9-c07030efc13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682677609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.3682677609
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.1210096967
Short name T1080
Test name
Test status
Simulation time 4200197231 ps
CPU time 15.98 seconds
Started Aug 04 05:26:23 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 242056 kb
Host smart-a7fea647-06b3-4087-ab5e-bbd685d74733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210096967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.1210096967
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.1138907677
Short name T1012
Test name
Test status
Simulation time 672854647 ps
CPU time 23.44 seconds
Started Aug 04 05:26:22 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 242496 kb
Host smart-1dcfc099-0c93-4cbd-bc0f-e90bd140f201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138907677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.1138907677
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.2520304730
Short name T868
Test name
Test status
Simulation time 2032739732 ps
CPU time 6.7 seconds
Started Aug 04 05:26:22 PM PDT 24
Finished Aug 04 05:26:29 PM PDT 24
Peak memory 241888 kb
Host smart-678f3425-de5f-4424-a176-525fb5c57267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520304730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2520304730
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.2220037750
Short name T526
Test name
Test status
Simulation time 1012444822 ps
CPU time 11.5 seconds
Started Aug 04 05:26:26 PM PDT 24
Finished Aug 04 05:26:38 PM PDT 24
Peak memory 242052 kb
Host smart-b77ea64e-0a0d-46d9-a9c2-2e430e97ce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220037750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2220037750
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.3509453401
Short name T401
Test name
Test status
Simulation time 1162123146 ps
CPU time 20.35 seconds
Started Aug 04 05:26:22 PM PDT 24
Finished Aug 04 05:26:42 PM PDT 24
Peak memory 241840 kb
Host smart-f500a34a-312e-4658-ad0b-88433bf3460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509453401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.3509453401
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.852202048
Short name T942
Test name
Test status
Simulation time 750598705 ps
CPU time 22.33 seconds
Started Aug 04 05:26:21 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 248564 kb
Host smart-3b43b31b-fbff-430d-969b-fae352821b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852202048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.852202048
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.2157823495
Short name T1005
Test name
Test status
Simulation time 208476937 ps
CPU time 7.01 seconds
Started Aug 04 05:26:24 PM PDT 24
Finished Aug 04 05:26:31 PM PDT 24
Peak memory 242312 kb
Host smart-add87e72-2aa9-4704-87bb-477e5ceb9120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157823495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.2157823495
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.3073900538
Short name T208
Test name
Test status
Simulation time 1150357343 ps
CPU time 10.84 seconds
Started Aug 04 05:26:26 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 242284 kb
Host smart-1f77a44d-2235-4948-b1cf-8d1538bc2118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073900538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.3073900538
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.3136355365
Short name T548
Test name
Test status
Simulation time 25761789068 ps
CPU time 107.24 seconds
Started Aug 04 05:26:24 PM PDT 24
Finished Aug 04 05:28:11 PM PDT 24
Peak memory 248580 kb
Host smart-67c088b9-9acb-45ef-968c-f7d284f76deb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136355365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.3136355365
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.4021405192
Short name T310
Test name
Test status
Simulation time 581017790875 ps
CPU time 1449.26 seconds
Started Aug 04 05:26:24 PM PDT 24
Finished Aug 04 05:50:33 PM PDT 24
Peak memory 451672 kb
Host smart-3d3081cc-b993-4d28-aa16-0a69522bf55f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021405192 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.4021405192
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.2582209976
Short name T928
Test name
Test status
Simulation time 268077980 ps
CPU time 7.09 seconds
Started Aug 04 05:26:22 PM PDT 24
Finished Aug 04 05:26:29 PM PDT 24
Peak memory 242204 kb
Host smart-c430b04b-6be9-4f81-8589-f33f078d9659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582209976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2582209976
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.1588801502
Short name T13
Test name
Test status
Simulation time 776979987 ps
CPU time 1.84 seconds
Started Aug 04 05:26:27 PM PDT 24
Finished Aug 04 05:26:29 PM PDT 24
Peak memory 240352 kb
Host smart-24a122a4-f702-43db-b6d7-90919cca9601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588801502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1588801502
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.3517233716
Short name T620
Test name
Test status
Simulation time 659296303 ps
CPU time 21.22 seconds
Started Aug 04 05:26:27 PM PDT 24
Finished Aug 04 05:26:48 PM PDT 24
Peak memory 241792 kb
Host smart-ed6a331a-c3b0-478a-b54f-978060845d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517233716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.3517233716
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.556935437
Short name T163
Test name
Test status
Simulation time 89854731 ps
CPU time 3.88 seconds
Started Aug 04 05:26:25 PM PDT 24
Finished Aug 04 05:26:29 PM PDT 24
Peak memory 242036 kb
Host smart-ff8925a4-c61b-4661-9d23-e98bb40f10e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556935437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.556935437
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.1382699791
Short name T1179
Test name
Test status
Simulation time 139674014 ps
CPU time 3.6 seconds
Started Aug 04 05:26:22 PM PDT 24
Finished Aug 04 05:26:26 PM PDT 24
Peak memory 241868 kb
Host smart-7b230f0b-d8a6-436a-832d-f963ddafd298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382699791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.1382699791
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.2030034092
Short name T990
Test name
Test status
Simulation time 501921106 ps
CPU time 10.64 seconds
Started Aug 04 05:26:25 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 242212 kb
Host smart-239c69b0-f329-44a3-82d8-f8103c788d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030034092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2030034092
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.2980337029
Short name T361
Test name
Test status
Simulation time 1838534256 ps
CPU time 14.19 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:44 PM PDT 24
Peak memory 241948 kb
Host smart-2e6464b0-4f88-42fa-be94-e66d4db3c785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980337029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2980337029
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.391980037
Short name T780
Test name
Test status
Simulation time 209112902 ps
CPU time 6.41 seconds
Started Aug 04 05:26:22 PM PDT 24
Finished Aug 04 05:26:29 PM PDT 24
Peak memory 242136 kb
Host smart-366153c9-95bf-4826-96b2-09a99326f642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391980037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.391980037
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.1673767988
Short name T1151
Test name
Test status
Simulation time 1047745809 ps
CPU time 15.6 seconds
Started Aug 04 05:26:23 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 242116 kb
Host smart-b9a065a2-fc7f-4d6c-8f02-6afb1c0200ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673767988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.1673767988
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.2493482130
Short name T332
Test name
Test status
Simulation time 228518671 ps
CPU time 4.8 seconds
Started Aug 04 05:26:26 PM PDT 24
Finished Aug 04 05:26:31 PM PDT 24
Peak memory 241956 kb
Host smart-0eb2c39a-1a9c-4c27-909d-cc96648571a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493482130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2493482130
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.4290895900
Short name T991
Test name
Test status
Simulation time 447108347 ps
CPU time 4.93 seconds
Started Aug 04 05:26:22 PM PDT 24
Finished Aug 04 05:26:27 PM PDT 24
Peak memory 242024 kb
Host smart-e4a20ed2-3d82-4d7f-98b4-bbbeebe09b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290895900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.4290895900
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.2518681340
Short name T129
Test name
Test status
Simulation time 50379668672 ps
CPU time 207.21 seconds
Started Aug 04 05:26:29 PM PDT 24
Finished Aug 04 05:29:57 PM PDT 24
Peak memory 257880 kb
Host smart-917e93ef-7b6b-45ae-90b3-fae7173bbe93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518681340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.2518681340
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.3626687511
Short name T1046
Test name
Test status
Simulation time 49863804279 ps
CPU time 810.13 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:40:00 PM PDT 24
Peak memory 276436 kb
Host smart-e4ee18f9-d967-481e-8a2f-e102929c19ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626687511 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.3626687511
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.1873037019
Short name T291
Test name
Test status
Simulation time 10480037462 ps
CPU time 30.02 seconds
Started Aug 04 05:26:28 PM PDT 24
Finished Aug 04 05:26:58 PM PDT 24
Peak memory 241864 kb
Host smart-eabbf038-eb1a-4ec3-b0a7-e190d0fd3379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873037019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1873037019
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.474195772
Short name T1116
Test name
Test status
Simulation time 217447578 ps
CPU time 2.25 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:24:50 PM PDT 24
Peak memory 240396 kb
Host smart-9d698ddc-6d98-4577-8a53-8008f5a00ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474195772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.474195772
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.1518270744
Short name T12
Test name
Test status
Simulation time 667469385 ps
CPU time 5.36 seconds
Started Aug 04 05:24:40 PM PDT 24
Finished Aug 04 05:24:45 PM PDT 24
Peak memory 241976 kb
Host smart-220777b2-9297-44f8-bcec-b8f0d45aa793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518270744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.1518270744
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.3343012938
Short name T958
Test name
Test status
Simulation time 674911512 ps
CPU time 24.58 seconds
Started Aug 04 05:24:39 PM PDT 24
Finished Aug 04 05:25:04 PM PDT 24
Peak memory 243700 kb
Host smart-a3e78c12-762b-495f-be60-ab694d846bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343012938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3343012938
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.4088192341
Short name T705
Test name
Test status
Simulation time 1795380462 ps
CPU time 27.2 seconds
Started Aug 04 05:24:42 PM PDT 24
Finished Aug 04 05:25:10 PM PDT 24
Peak memory 244284 kb
Host smart-66fe9db0-f189-4994-a016-b2029a6d1bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088192341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.4088192341
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.3652813480
Short name T1120
Test name
Test status
Simulation time 914698772 ps
CPU time 14.35 seconds
Started Aug 04 05:24:48 PM PDT 24
Finished Aug 04 05:25:02 PM PDT 24
Peak memory 242000 kb
Host smart-c9019a97-6473-43bf-9d87-2030e225f270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652813480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.3652813480
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.327882685
Short name T373
Test name
Test status
Simulation time 513999317 ps
CPU time 3.97 seconds
Started Aug 04 05:24:48 PM PDT 24
Finished Aug 04 05:24:52 PM PDT 24
Peak memory 241724 kb
Host smart-83f6b6c3-d2f4-431f-837f-269ff1b9f99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327882685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.327882685
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.1192188921
Short name T905
Test name
Test status
Simulation time 4640592991 ps
CPU time 22.95 seconds
Started Aug 04 05:24:40 PM PDT 24
Finished Aug 04 05:25:03 PM PDT 24
Peak memory 248676 kb
Host smart-ae566f0e-a419-4184-84d3-98b57295b649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192188921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.1192188921
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.3224100539
Short name T351
Test name
Test status
Simulation time 13998845132 ps
CPU time 49.74 seconds
Started Aug 04 05:24:39 PM PDT 24
Finished Aug 04 05:25:29 PM PDT 24
Peak memory 242288 kb
Host smart-336b3243-2fa6-4be5-a40b-e47cafb846c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224100539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3224100539
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.884952877
Short name T517
Test name
Test status
Simulation time 252759464 ps
CPU time 8.16 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:24:56 PM PDT 24
Peak memory 242172 kb
Host smart-b93999d7-db50-4573-8b25-02f82d6fc136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884952877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.884952877
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.743866048
Short name T223
Test name
Test status
Simulation time 1793463869 ps
CPU time 14.66 seconds
Started Aug 04 05:24:40 PM PDT 24
Finished Aug 04 05:24:54 PM PDT 24
Peak memory 248540 kb
Host smart-9746c24a-8d25-4d2b-aedd-33655301711d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743866048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.743866048
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.353460937
Short name T334
Test name
Test status
Simulation time 693638319 ps
CPU time 7.7 seconds
Started Aug 04 05:24:42 PM PDT 24
Finished Aug 04 05:24:50 PM PDT 24
Peak memory 241868 kb
Host smart-4dba48a5-2ab9-4f28-896a-9b9af6d826a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353460937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.353460937
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.847435117
Short name T162
Test name
Test status
Simulation time 3354635570 ps
CPU time 8.86 seconds
Started Aug 04 05:24:39 PM PDT 24
Finished Aug 04 05:24:48 PM PDT 24
Peak memory 242380 kb
Host smart-d0f8a8d8-1544-486c-bb23-4a98bfe2a172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847435117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.847435117
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.4037004252
Short name T1184
Test name
Test status
Simulation time 35105821681 ps
CPU time 216.71 seconds
Started Aug 04 05:24:41 PM PDT 24
Finished Aug 04 05:28:18 PM PDT 24
Peak memory 250256 kb
Host smart-5daa0b69-69aa-4a4d-9d8d-e9fc063851b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037004252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
4037004252
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.636502347
Short name T788
Test name
Test status
Simulation time 1862637334014 ps
CPU time 3053.2 seconds
Started Aug 04 05:24:45 PM PDT 24
Finished Aug 04 06:15:39 PM PDT 24
Peak memory 505348 kb
Host smart-d592b0a3-bf25-4832-8524-9f6df5ea7a1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636502347 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.636502347
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.758735917
Short name T1040
Test name
Test status
Simulation time 4665017431 ps
CPU time 25.55 seconds
Started Aug 04 05:24:45 PM PDT 24
Finished Aug 04 05:25:11 PM PDT 24
Peak memory 242508 kb
Host smart-fe02962f-8cdd-4096-b64d-b5f6c632290d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758735917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.758735917
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.1946874319
Short name T72
Test name
Test status
Simulation time 1767086673 ps
CPU time 6.07 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 242228 kb
Host smart-75cb4764-5f6b-42a2-9289-8b236071226d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946874319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1946874319
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.1205825006
Short name T229
Test name
Test status
Simulation time 513298515 ps
CPU time 14.05 seconds
Started Aug 04 05:26:29 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 241932 kb
Host smart-7178ac23-5e29-4429-8e7f-f2bad50eef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205825006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1205825006
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.892551979
Short name T452
Test name
Test status
Simulation time 139973919820 ps
CPU time 1063.15 seconds
Started Aug 04 05:26:27 PM PDT 24
Finished Aug 04 05:44:10 PM PDT 24
Peak memory 265204 kb
Host smart-a76d4d04-c397-4001-8b80-cbabdb4b9c66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892551979 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.892551979
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.4153922535
Short name T710
Test name
Test status
Simulation time 150556309 ps
CPU time 3.29 seconds
Started Aug 04 05:26:29 PM PDT 24
Finished Aug 04 05:26:32 PM PDT 24
Peak memory 242072 kb
Host smart-b90db4c9-926f-431d-813f-698ec077243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153922535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.4153922535
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.2819540959
Short name T702
Test name
Test status
Simulation time 168183900 ps
CPU time 6.83 seconds
Started Aug 04 05:26:26 PM PDT 24
Finished Aug 04 05:26:33 PM PDT 24
Peak memory 242260 kb
Host smart-6af3295f-71c4-4ec8-8d6d-a146ce700084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819540959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2819540959
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.2010066957
Short name T301
Test name
Test status
Simulation time 217310023555 ps
CPU time 1728.93 seconds
Started Aug 04 05:26:29 PM PDT 24
Finished Aug 04 05:55:19 PM PDT 24
Peak memory 289704 kb
Host smart-e9ae82ee-311d-4948-ac43-d3a8c07f6028
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010066957 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.2010066957
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.1881165531
Short name T911
Test name
Test status
Simulation time 1908243282 ps
CPU time 6.51 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 242072 kb
Host smart-0b0f3e7e-a192-4f57-8f44-4b220bd73a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881165531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.1881165531
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.1770055139
Short name T943
Test name
Test status
Simulation time 7967325984 ps
CPU time 19.14 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:49 PM PDT 24
Peak memory 242332 kb
Host smart-a54daf77-d2c4-4f8a-ab04-2b75be94f108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770055139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.1770055139
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.2288199391
Short name T164
Test name
Test status
Simulation time 80627246294 ps
CPU time 486.74 seconds
Started Aug 04 05:26:28 PM PDT 24
Finished Aug 04 05:34:34 PM PDT 24
Peak memory 315588 kb
Host smart-20f7b2d6-cf85-43d3-9779-94b88a0d1000
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288199391 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.2288199391
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.2247369241
Short name T1159
Test name
Test status
Simulation time 465871283 ps
CPU time 4.75 seconds
Started Aug 04 05:26:28 PM PDT 24
Finished Aug 04 05:26:33 PM PDT 24
Peak memory 242276 kb
Host smart-9bfd2cd5-2f99-4058-bb0c-ab7283599d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247369241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.2247369241
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.3523035227
Short name T746
Test name
Test status
Simulation time 9857849035 ps
CPU time 21.45 seconds
Started Aug 04 05:26:28 PM PDT 24
Finished Aug 04 05:26:49 PM PDT 24
Peak memory 241792 kb
Host smart-00067d64-027c-423f-b881-caab62f47a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523035227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3523035227
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.652476044
Short name T972
Test name
Test status
Simulation time 127953208755 ps
CPU time 1001.76 seconds
Started Aug 04 05:26:25 PM PDT 24
Finished Aug 04 05:43:07 PM PDT 24
Peak memory 257336 kb
Host smart-627362c5-96df-482d-acc4-0df26a5b4535
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652476044 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.652476044
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.2523041876
Short name T91
Test name
Test status
Simulation time 1657139121 ps
CPU time 5.86 seconds
Started Aug 04 05:26:27 PM PDT 24
Finished Aug 04 05:26:33 PM PDT 24
Peak memory 242120 kb
Host smart-957253d7-bf39-48f4-bc20-15ca28ac46e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523041876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.2523041876
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.118581776
Short name T534
Test name
Test status
Simulation time 306232778 ps
CPU time 7.68 seconds
Started Aug 04 05:26:28 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 242080 kb
Host smart-bf70f921-3881-4e40-bbe0-c2413fadd583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118581776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.118581776
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.1586184311
Short name T6
Test name
Test status
Simulation time 148058603391 ps
CPU time 746.07 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:38:57 PM PDT 24
Peak memory 265080 kb
Host smart-2651f089-3264-4e51-9b2c-017da7ab906f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586184311 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.1586184311
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.1506018872
Short name T691
Test name
Test status
Simulation time 142747117 ps
CPU time 3.65 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:34 PM PDT 24
Peak memory 242212 kb
Host smart-eff3307e-f4cf-48c3-812b-fbb0cffc7f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506018872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.1506018872
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.3663399767
Short name T308
Test name
Test status
Simulation time 718783254 ps
CPU time 20.22 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 242016 kb
Host smart-a5d87d60-217f-4463-b60b-5bd0b6e31293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663399767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.3663399767
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.1427608744
Short name T303
Test name
Test status
Simulation time 151107859015 ps
CPU time 987.96 seconds
Started Aug 04 05:26:33 PM PDT 24
Finished Aug 04 05:43:01 PM PDT 24
Peak memory 329928 kb
Host smart-1f52b9b1-bb21-4ae1-90b6-2834ee1bfa2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427608744 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.1427608744
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.2744267869
Short name T695
Test name
Test status
Simulation time 237258208 ps
CPU time 3.14 seconds
Started Aug 04 05:26:32 PM PDT 24
Finished Aug 04 05:26:35 PM PDT 24
Peak memory 241920 kb
Host smart-c6ecde8b-cdf9-40c5-873c-432d7dab2788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744267869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.2744267869
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.1555493962
Short name T214
Test name
Test status
Simulation time 348922746 ps
CPU time 6.81 seconds
Started Aug 04 05:26:31 PM PDT 24
Finished Aug 04 05:26:38 PM PDT 24
Peak memory 247396 kb
Host smart-47e35cfa-dc06-4d78-9b7c-ad52646bed4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555493962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1555493962
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2300340776
Short name T915
Test name
Test status
Simulation time 195464608987 ps
CPU time 1402.14 seconds
Started Aug 04 05:26:32 PM PDT 24
Finished Aug 04 05:49:54 PM PDT 24
Peak memory 300440 kb
Host smart-761649f2-c824-4033-869a-0078d9254b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300340776 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.2300340776
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.3066198009
Short name T709
Test name
Test status
Simulation time 236221805 ps
CPU time 3.33 seconds
Started Aug 04 05:26:33 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 241928 kb
Host smart-744b8716-713d-4eb2-b44e-0920fb3829c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066198009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.3066198009
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.945922312
Short name T65
Test name
Test status
Simulation time 1600631255 ps
CPU time 5.15 seconds
Started Aug 04 05:26:33 PM PDT 24
Finished Aug 04 05:26:38 PM PDT 24
Peak memory 241860 kb
Host smart-f9e27cae-f6dd-45d4-9df2-ccfbf2a981b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945922312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.945922312
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.481514560
Short name T174
Test name
Test status
Simulation time 110839998 ps
CPU time 4.26 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:34 PM PDT 24
Peak memory 242316 kb
Host smart-087ba243-f31f-4b3f-b1e0-827e343501c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481514560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.481514560
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.3433675040
Short name T703
Test name
Test status
Simulation time 338334982 ps
CPU time 4.05 seconds
Started Aug 04 05:26:40 PM PDT 24
Finished Aug 04 05:26:44 PM PDT 24
Peak memory 241928 kb
Host smart-87dc7fda-d948-441a-982a-b1bcb290fc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433675040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.3433675040
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.1087495252
Short name T758
Test name
Test status
Simulation time 27372645891 ps
CPU time 311.99 seconds
Started Aug 04 05:26:32 PM PDT 24
Finished Aug 04 05:31:44 PM PDT 24
Peak memory 278428 kb
Host smart-d5fe9831-28a5-42e0-bca9-bdeea6123dc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087495252 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.1087495252
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.102644645
Short name T471
Test name
Test status
Simulation time 380124797 ps
CPU time 10.81 seconds
Started Aug 04 05:26:31 PM PDT 24
Finished Aug 04 05:26:42 PM PDT 24
Peak memory 242128 kb
Host smart-3b7be1c6-3b05-4a3b-a143-71afb90b4cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102644645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.102644645
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.1722802034
Short name T778
Test name
Test status
Simulation time 942875823 ps
CPU time 2.44 seconds
Started Aug 04 05:24:42 PM PDT 24
Finished Aug 04 05:24:45 PM PDT 24
Peak memory 240260 kb
Host smart-9923cf9f-efbc-43fb-bfc9-643dc0d4840f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722802034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1722802034
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.1355539485
Short name T753
Test name
Test status
Simulation time 2639018209 ps
CPU time 31.51 seconds
Started Aug 04 05:24:40 PM PDT 24
Finished Aug 04 05:25:11 PM PDT 24
Peak memory 242360 kb
Host smart-f95c9e69-c272-4e2e-bdda-1162fda32d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355539485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.1355539485
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.1697703261
Short name T50
Test name
Test status
Simulation time 375093210 ps
CPU time 10.55 seconds
Started Aug 04 05:24:46 PM PDT 24
Finished Aug 04 05:24:57 PM PDT 24
Peak memory 241976 kb
Host smart-3be0fe76-ec2e-432f-b775-d885e0e06e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697703261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.1697703261
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.1201710920
Short name T107
Test name
Test status
Simulation time 2564859067 ps
CPU time 18.27 seconds
Started Aug 04 05:24:45 PM PDT 24
Finished Aug 04 05:25:03 PM PDT 24
Peak memory 242404 kb
Host smart-a913203c-ce52-453f-9b00-d543e58555e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201710920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1201710920
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.70174819
Short name T457
Test name
Test status
Simulation time 246613878 ps
CPU time 5.32 seconds
Started Aug 04 05:24:40 PM PDT 24
Finished Aug 04 05:24:45 PM PDT 24
Peak memory 241912 kb
Host smart-da5e4ceb-4e33-49e8-891f-a76b84fb38bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70174819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.70174819
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.920973827
Short name T155
Test name
Test status
Simulation time 142609893 ps
CPU time 3.93 seconds
Started Aug 04 05:24:46 PM PDT 24
Finished Aug 04 05:24:50 PM PDT 24
Peak memory 242068 kb
Host smart-9217dff4-8e19-4e98-a7e0-ccdd1a988cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920973827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.920973827
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.3567342660
Short name T1050
Test name
Test status
Simulation time 7024748399 ps
CPU time 38.7 seconds
Started Aug 04 05:24:46 PM PDT 24
Finished Aug 04 05:25:25 PM PDT 24
Peak memory 248660 kb
Host smart-fd82fe86-1b2f-43a2-a15c-b6bbb347f892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567342660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3567342660
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.2483811307
Short name T516
Test name
Test status
Simulation time 667959418 ps
CPU time 18.04 seconds
Started Aug 04 05:24:43 PM PDT 24
Finished Aug 04 05:25:02 PM PDT 24
Peak memory 242208 kb
Host smart-5bfc5dc1-ddb6-4f4b-a089-b3ef1609c7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483811307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2483811307
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.47935203
Short name T640
Test name
Test status
Simulation time 1363650586 ps
CPU time 21.47 seconds
Started Aug 04 05:24:40 PM PDT 24
Finished Aug 04 05:25:02 PM PDT 24
Peak memory 241968 kb
Host smart-4cd737f2-46f1-4c80-9e8c-c2f20bec56ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47935203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.47935203
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.3271107197
Short name T769
Test name
Test status
Simulation time 8847741438 ps
CPU time 23.57 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:25:11 PM PDT 24
Peak memory 248656 kb
Host smart-358631e3-4b2c-441a-9ee2-425f5687a269
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271107197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3271107197
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.2455182396
Short name T329
Test name
Test status
Simulation time 224393412 ps
CPU time 3.78 seconds
Started Aug 04 05:24:43 PM PDT 24
Finished Aug 04 05:24:47 PM PDT 24
Peak memory 241856 kb
Host smart-37c5198d-cb9d-4a6b-9fa8-173ac2eaf9a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2455182396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2455182396
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.1309240027
Short name T1093
Test name
Test status
Simulation time 412460530 ps
CPU time 6.91 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:24:54 PM PDT 24
Peak memory 242280 kb
Host smart-4510fd8a-0fbb-4f57-b439-64d14db101f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309240027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.1309240027
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.4274059409
Short name T890
Test name
Test status
Simulation time 35243183010 ps
CPU time 207.87 seconds
Started Aug 04 05:24:43 PM PDT 24
Finished Aug 04 05:28:11 PM PDT 24
Peak memory 259024 kb
Host smart-f5f37fd8-1a47-4729-a839-7b4a503c1018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274059409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
4274059409
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.4180604564
Short name T1111
Test name
Test status
Simulation time 65633799600 ps
CPU time 1976.47 seconds
Started Aug 04 05:24:45 PM PDT 24
Finished Aug 04 05:57:42 PM PDT 24
Peak memory 459160 kb
Host smart-6f256fa7-41cc-4d68-827a-8cd93de26b09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180604564 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.4180604564
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.2623947787
Short name T424
Test name
Test status
Simulation time 2007380611 ps
CPU time 15.1 seconds
Started Aug 04 05:24:45 PM PDT 24
Finished Aug 04 05:25:00 PM PDT 24
Peak memory 241972 kb
Host smart-db069e58-e44d-4281-a9cb-9ab1d994d6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623947787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2623947787
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.77647755
Short name T455
Test name
Test status
Simulation time 147040489 ps
CPU time 3.99 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:34 PM PDT 24
Peak memory 241928 kb
Host smart-62c053d8-9371-4a41-8c8f-17a234bd26fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77647755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.77647755
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.2667361519
Short name T872
Test name
Test status
Simulation time 383062024 ps
CPU time 11.68 seconds
Started Aug 04 05:26:40 PM PDT 24
Finished Aug 04 05:26:52 PM PDT 24
Peak memory 241964 kb
Host smart-63e855d3-0dd0-4515-a59d-ce82e90df6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667361519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.2667361519
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.2358298264
Short name T965
Test name
Test status
Simulation time 285660665 ps
CPU time 4.16 seconds
Started Aug 04 05:26:37 PM PDT 24
Finished Aug 04 05:26:41 PM PDT 24
Peak memory 241864 kb
Host smart-75de1bf9-90e2-4174-b651-3d4054a6f827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358298264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2358298264
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.3851954613
Short name T634
Test name
Test status
Simulation time 466395481 ps
CPU time 9.11 seconds
Started Aug 04 05:26:37 PM PDT 24
Finished Aug 04 05:26:46 PM PDT 24
Peak memory 241904 kb
Host smart-da70f79b-4ac1-4e0a-94ab-8fc033164c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851954613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3851954613
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.2203832426
Short name T242
Test name
Test status
Simulation time 702757055992 ps
CPU time 1238.17 seconds
Started Aug 04 05:26:40 PM PDT 24
Finished Aug 04 05:47:19 PM PDT 24
Peak memory 260776 kb
Host smart-ef17f378-116f-42e7-97e3-68656dc7cc55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203832426 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.2203832426
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.2273887942
Short name T1032
Test name
Test status
Simulation time 655065102 ps
CPU time 4.33 seconds
Started Aug 04 05:26:33 PM PDT 24
Finished Aug 04 05:26:37 PM PDT 24
Peak memory 242064 kb
Host smart-e72ac9cd-b528-4f67-894a-579a4b996715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273887942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2273887942
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.2822957746
Short name T950
Test name
Test status
Simulation time 151967476 ps
CPU time 3.31 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:34 PM PDT 24
Peak memory 241796 kb
Host smart-74e2e383-d423-484b-a6e4-85b4db7ca455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822957746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.2822957746
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.2896726148
Short name T810
Test name
Test status
Simulation time 138438076964 ps
CPU time 699.24 seconds
Started Aug 04 05:26:37 PM PDT 24
Finished Aug 04 05:38:17 PM PDT 24
Peak memory 263436 kb
Host smart-68e27005-13c7-48c8-b87c-54a73b68f15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896726148 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.2896726148
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.232272004
Short name T1072
Test name
Test status
Simulation time 397780988 ps
CPU time 4.36 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:34 PM PDT 24
Peak memory 241944 kb
Host smart-6e63aa6c-6b0b-41b7-adfc-22311f2cb50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232272004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.232272004
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.8147785
Short name T795
Test name
Test status
Simulation time 631653893 ps
CPU time 15.99 seconds
Started Aug 04 05:26:39 PM PDT 24
Finished Aug 04 05:26:55 PM PDT 24
Peak memory 242312 kb
Host smart-3f3c229f-c12b-4f17-b836-f9e5a5759983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8147785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.8147785
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.865477383
Short name T448
Test name
Test status
Simulation time 1667157323 ps
CPU time 5.14 seconds
Started Aug 04 05:26:31 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 241964 kb
Host smart-013b4743-3eec-45bf-9ab7-39ec31748c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865477383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.865477383
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.3575428753
Short name T690
Test name
Test status
Simulation time 311284044 ps
CPU time 7.42 seconds
Started Aug 04 05:26:33 PM PDT 24
Finished Aug 04 05:26:41 PM PDT 24
Peak memory 242036 kb
Host smart-3678667d-7063-47f1-b955-7bfba5a84e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575428753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.3575428753
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.1544278909
Short name T17
Test name
Test status
Simulation time 729315812152 ps
CPU time 1277.48 seconds
Started Aug 04 05:26:32 PM PDT 24
Finished Aug 04 05:47:49 PM PDT 24
Peak memory 265184 kb
Host smart-bf70591f-8e22-4fb0-b635-1903d9473d22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544278909 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.1544278909
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.3726083336
Short name T193
Test name
Test status
Simulation time 1468477437 ps
CPU time 5.14 seconds
Started Aug 04 05:26:32 PM PDT 24
Finished Aug 04 05:26:37 PM PDT 24
Peak memory 242356 kb
Host smart-2827213e-ea8a-446b-99bf-7b02df541e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726083336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3726083336
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.3137852676
Short name T145
Test name
Test status
Simulation time 4303931362 ps
CPU time 11.04 seconds
Started Aug 04 05:26:34 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 241940 kb
Host smart-e81087a7-2d81-4f86-a7fa-ac5c8ad8444f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137852676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3137852676
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.3530124993
Short name T1091
Test name
Test status
Simulation time 26422101969 ps
CPU time 600.9 seconds
Started Aug 04 05:26:33 PM PDT 24
Finished Aug 04 05:36:34 PM PDT 24
Peak memory 314500 kb
Host smart-49afe537-3188-426b-9f6c-84d0470bb095
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530124993 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.3530124993
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.630338278
Short name T1015
Test name
Test status
Simulation time 1962034467 ps
CPU time 6.18 seconds
Started Aug 04 05:26:31 PM PDT 24
Finished Aug 04 05:26:38 PM PDT 24
Peak memory 241944 kb
Host smart-641c3c6f-2b64-4378-8d27-7fcefbf25945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630338278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.630338278
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.1309382279
Short name T993
Test name
Test status
Simulation time 511789152 ps
CPU time 12.57 seconds
Started Aug 04 05:26:30 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 242004 kb
Host smart-c2647ea2-8585-4aa2-861b-451a2ca1b838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309382279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.1309382279
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.2437178090
Short name T694
Test name
Test status
Simulation time 105857921904 ps
CPU time 1021.69 seconds
Started Aug 04 05:26:31 PM PDT 24
Finished Aug 04 05:43:33 PM PDT 24
Peak memory 305312 kb
Host smart-474b8501-475f-4330-8360-39903d004008
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437178090 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.2437178090
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.2487052608
Short name T60
Test name
Test status
Simulation time 270191606 ps
CPU time 4.74 seconds
Started Aug 04 05:26:32 PM PDT 24
Finished Aug 04 05:26:37 PM PDT 24
Peak memory 242176 kb
Host smart-f13b5dc0-5fa7-4631-b8fc-2f7e117e7fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487052608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.2487052608
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2406739681
Short name T1055
Test name
Test status
Simulation time 516958181 ps
CPU time 4.17 seconds
Started Aug 04 05:26:32 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 241716 kb
Host smart-1ef0df66-195f-42bf-82ff-6300fad1704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406739681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2406739681
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.3458098277
Short name T607
Test name
Test status
Simulation time 30251192863 ps
CPU time 642.61 seconds
Started Aug 04 05:26:34 PM PDT 24
Finished Aug 04 05:37:16 PM PDT 24
Peak memory 310772 kb
Host smart-b85c507a-b8f3-48cd-a7ee-4b5851f473dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458098277 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.3458098277
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.4045637941
Short name T801
Test name
Test status
Simulation time 161013423 ps
CPU time 4.63 seconds
Started Aug 04 05:26:37 PM PDT 24
Finished Aug 04 05:26:41 PM PDT 24
Peak memory 242220 kb
Host smart-d14e91c3-42c7-458a-85cf-8066735eea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045637941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.4045637941
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.823682169
Short name T474
Test name
Test status
Simulation time 335936887 ps
CPU time 6.38 seconds
Started Aug 04 05:26:37 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 242116 kb
Host smart-f8409564-869f-4109-839f-fd92b2ddeccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823682169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.823682169
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.3446720453
Short name T131
Test name
Test status
Simulation time 238136007092 ps
CPU time 1714.89 seconds
Started Aug 04 05:26:32 PM PDT 24
Finished Aug 04 05:55:07 PM PDT 24
Peak memory 366876 kb
Host smart-685bf82a-58be-4f52-a992-6c346484f780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446720453 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.3446720453
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.3712363058
Short name T798
Test name
Test status
Simulation time 600700345 ps
CPU time 4.37 seconds
Started Aug 04 05:26:34 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 242116 kb
Host smart-d993349a-76a4-469c-9f6c-943f931a3b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712363058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.3712363058
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.590110555
Short name T610
Test name
Test status
Simulation time 588342139 ps
CPU time 6.68 seconds
Started Aug 04 05:26:34 PM PDT 24
Finished Aug 04 05:26:41 PM PDT 24
Peak memory 241892 kb
Host smart-e29d3c24-d09d-48e7-9935-8a8f95ea93cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590110555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.590110555
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2434831582
Short name T14
Test name
Test status
Simulation time 25213616492 ps
CPU time 549.53 seconds
Started Aug 04 05:26:36 PM PDT 24
Finished Aug 04 05:35:45 PM PDT 24
Peak memory 256868 kb
Host smart-ef2c9c7a-78d9-4b64-bcca-29a1f7012dae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434831582 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.2434831582
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.2979156888
Short name T1107
Test name
Test status
Simulation time 142987848 ps
CPU time 1.82 seconds
Started Aug 04 05:24:48 PM PDT 24
Finished Aug 04 05:24:50 PM PDT 24
Peak memory 240532 kb
Host smart-c439a04e-cd8b-4c3d-ab26-e4fb92ff63fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979156888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.2979156888
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.173045495
Short name T1010
Test name
Test status
Simulation time 10543902212 ps
CPU time 20.59 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:25:08 PM PDT 24
Peak memory 242788 kb
Host smart-1c6276b4-3f95-4414-82b6-f79259bfe1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173045495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.173045495
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.2370572769
Short name T110
Test name
Test status
Simulation time 8288814335 ps
CPU time 19.55 seconds
Started Aug 04 05:24:42 PM PDT 24
Finished Aug 04 05:25:01 PM PDT 24
Peak memory 243640 kb
Host smart-4e741901-ffc7-4e07-9cc8-b465681bd498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370572769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2370572769
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.434344169
Short name T489
Test name
Test status
Simulation time 1318644132 ps
CPU time 24.3 seconds
Started Aug 04 05:24:42 PM PDT 24
Finished Aug 04 05:25:07 PM PDT 24
Peak memory 241932 kb
Host smart-47cbb112-249c-482b-970d-3878126afb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434344169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.434344169
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.2479263134
Short name T353
Test name
Test status
Simulation time 1588066402 ps
CPU time 31.67 seconds
Started Aug 04 05:24:44 PM PDT 24
Finished Aug 04 05:25:16 PM PDT 24
Peak memory 241948 kb
Host smart-9b0f6e51-7d29-405b-8297-ba1d63d3943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479263134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2479263134
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.752312649
Short name T740
Test name
Test status
Simulation time 1602510266 ps
CPU time 18.46 seconds
Started Aug 04 05:24:49 PM PDT 24
Finished Aug 04 05:25:07 PM PDT 24
Peak memory 241932 kb
Host smart-7929c7e4-689e-44e0-a097-13a7a5958575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752312649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.752312649
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.2898570093
Short name T395
Test name
Test status
Simulation time 1787907349 ps
CPU time 15.95 seconds
Started Aug 04 05:24:46 PM PDT 24
Finished Aug 04 05:25:02 PM PDT 24
Peak memory 242248 kb
Host smart-279d727b-2862-437e-981a-cd5a1653c500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898570093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2898570093
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.343880441
Short name T927
Test name
Test status
Simulation time 123420017 ps
CPU time 5.71 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:24:53 PM PDT 24
Peak memory 242060 kb
Host smart-61e3ce33-beec-4d88-ac5b-068bdb8e13a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343880441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.343880441
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.1522535886
Short name T24
Test name
Test status
Simulation time 1577979256 ps
CPU time 16.21 seconds
Started Aug 04 05:24:43 PM PDT 24
Finished Aug 04 05:25:00 PM PDT 24
Peak memory 248676 kb
Host smart-d99ca245-6967-42c2-a23b-0e749f5864a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522535886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.1522535886
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2216459202
Short name T333
Test name
Test status
Simulation time 266463876 ps
CPU time 9.22 seconds
Started Aug 04 05:24:45 PM PDT 24
Finished Aug 04 05:24:54 PM PDT 24
Peak memory 242316 kb
Host smart-c5566a52-e3b2-4c0a-b9e9-ac5e43a60939
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2216459202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2216459202
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.1792176270
Short name T428
Test name
Test status
Simulation time 502805490 ps
CPU time 5.13 seconds
Started Aug 04 05:24:41 PM PDT 24
Finished Aug 04 05:24:47 PM PDT 24
Peak memory 241944 kb
Host smart-c2fb7347-9e54-4475-9a12-9065274300c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792176270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1792176270
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.3231948014
Short name T629
Test name
Test status
Simulation time 10997985514 ps
CPU time 169.29 seconds
Started Aug 04 05:24:48 PM PDT 24
Finished Aug 04 05:27:38 PM PDT 24
Peak memory 250584 kb
Host smart-094be85b-9c45-4da0-be6c-de8360466f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231948014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
3231948014
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.2136941617
Short name T1186
Test name
Test status
Simulation time 40388061890 ps
CPU time 101.72 seconds
Started Aug 04 05:24:46 PM PDT 24
Finished Aug 04 05:26:28 PM PDT 24
Peak memory 260528 kb
Host smart-5546e80b-edf3-4a92-94d4-c6eb33908fa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136941617 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.2136941617
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.2655031795
Short name T248
Test name
Test status
Simulation time 1641470971 ps
CPU time 16.24 seconds
Started Aug 04 05:24:45 PM PDT 24
Finished Aug 04 05:25:01 PM PDT 24
Peak memory 242536 kb
Host smart-d11f4f59-4ad3-4e4c-9085-dde99a5de239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655031795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2655031795
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.1679203155
Short name T461
Test name
Test status
Simulation time 462889050 ps
CPU time 3.53 seconds
Started Aug 04 05:26:37 PM PDT 24
Finished Aug 04 05:26:40 PM PDT 24
Peak memory 242360 kb
Host smart-e84fb12c-2627-40eb-bb88-8f4cb875a3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679203155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.1679203155
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.3861389392
Short name T669
Test name
Test status
Simulation time 164126921 ps
CPU time 6.67 seconds
Started Aug 04 05:26:35 PM PDT 24
Finished Aug 04 05:26:42 PM PDT 24
Peak memory 242352 kb
Host smart-d575bae0-df43-41d0-932b-67c25234b631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861389392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.3861389392
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.3994385815
Short name T352
Test name
Test status
Simulation time 116355816402 ps
CPU time 1320.49 seconds
Started Aug 04 05:26:33 PM PDT 24
Finished Aug 04 05:48:34 PM PDT 24
Peak memory 261448 kb
Host smart-5192b369-be5c-4d79-9a90-e302d8c0bde1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994385815 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.3994385815
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.1249829834
Short name T587
Test name
Test status
Simulation time 542359084 ps
CPU time 3.42 seconds
Started Aug 04 05:26:35 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 241964 kb
Host smart-628ec7d0-7073-43ce-a260-3f38ff11c979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249829834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.1249829834
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2262511205
Short name T841
Test name
Test status
Simulation time 241655573 ps
CPU time 5.99 seconds
Started Aug 04 05:26:32 PM PDT 24
Finished Aug 04 05:26:38 PM PDT 24
Peak memory 242012 kb
Host smart-3fadd525-b6df-4acd-8234-1684646a9a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262511205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2262511205
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.4098819014
Short name T834
Test name
Test status
Simulation time 24601166848 ps
CPU time 676.96 seconds
Started Aug 04 05:26:34 PM PDT 24
Finished Aug 04 05:37:51 PM PDT 24
Peak memory 277296 kb
Host smart-d9847666-6764-48a7-ab9b-ae955958d7d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098819014 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.4098819014
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.1605445403
Short name T552
Test name
Test status
Simulation time 294284956 ps
CPU time 16.76 seconds
Started Aug 04 05:26:35 PM PDT 24
Finished Aug 04 05:26:52 PM PDT 24
Peak memory 241916 kb
Host smart-fb1f7fca-afa3-4520-be15-2a474620274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605445403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.1605445403
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.3332035820
Short name T240
Test name
Test status
Simulation time 230161923176 ps
CPU time 1602.2 seconds
Started Aug 04 05:26:39 PM PDT 24
Finished Aug 04 05:53:22 PM PDT 24
Peak memory 294576 kb
Host smart-ebcb0ed7-12a1-47b1-8662-b09a6d41a05a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332035820 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.3332035820
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.2110163709
Short name T175
Test name
Test status
Simulation time 471859200 ps
CPU time 4.09 seconds
Started Aug 04 05:26:36 PM PDT 24
Finished Aug 04 05:26:40 PM PDT 24
Peak memory 242192 kb
Host smart-92b687a0-bc17-4167-97f9-b36abeeae6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110163709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.2110163709
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.2978938296
Short name T852
Test name
Test status
Simulation time 835689145 ps
CPU time 6.47 seconds
Started Aug 04 05:26:34 PM PDT 24
Finished Aug 04 05:26:41 PM PDT 24
Peak memory 241912 kb
Host smart-750403eb-9a57-4cdb-8dd8-2862b7abd91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978938296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.2978938296
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.2102805853
Short name T884
Test name
Test status
Simulation time 98397906974 ps
CPU time 2245.42 seconds
Started Aug 04 05:26:35 PM PDT 24
Finished Aug 04 06:04:01 PM PDT 24
Peak memory 304996 kb
Host smart-133a79c2-cedb-49a7-aae3-4fda0e741487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102805853 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.2102805853
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.4216119960
Short name T85
Test name
Test status
Simulation time 292947049 ps
CPU time 3.92 seconds
Started Aug 04 05:26:32 PM PDT 24
Finished Aug 04 05:26:36 PM PDT 24
Peak memory 241920 kb
Host smart-df2b5776-0619-48f6-bb6a-b0a1b48fa9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216119960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.4216119960
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.2010352664
Short name T986
Test name
Test status
Simulation time 217470556 ps
CPU time 4.8 seconds
Started Aug 04 05:26:40 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 242040 kb
Host smart-cf9c2dea-0ef3-40e3-8273-3fc8a01cee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010352664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.2010352664
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1234694547
Short name T246
Test name
Test status
Simulation time 437243061356 ps
CPU time 3349.96 seconds
Started Aug 04 05:26:35 PM PDT 24
Finished Aug 04 06:22:26 PM PDT 24
Peak memory 302452 kb
Host smart-6c676823-6813-4e6b-ba7a-03b30af00fbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234694547 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.1234694547
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.1765060299
Short name T273
Test name
Test status
Simulation time 152608824 ps
CPU time 3.57 seconds
Started Aug 04 05:26:34 PM PDT 24
Finished Aug 04 05:26:38 PM PDT 24
Peak memory 241924 kb
Host smart-4500e908-4033-4cfd-b883-2797081c7c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765060299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.1765060299
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.1374043260
Short name T811
Test name
Test status
Simulation time 157217344 ps
CPU time 6.17 seconds
Started Aug 04 05:26:34 PM PDT 24
Finished Aug 04 05:26:41 PM PDT 24
Peak memory 241948 kb
Host smart-bcf8b0c5-d3d0-4d94-82d8-c155722ff493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374043260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.1374043260
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.4231258446
Short name T820
Test name
Test status
Simulation time 149135529757 ps
CPU time 2083.34 seconds
Started Aug 04 05:26:36 PM PDT 24
Finished Aug 04 06:01:20 PM PDT 24
Peak memory 388072 kb
Host smart-89f98a7a-00a7-44fd-86d7-8e365a41ab06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231258446 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.4231258446
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.536201112
Short name T685
Test name
Test status
Simulation time 100259524 ps
CPU time 3.47 seconds
Started Aug 04 05:26:37 PM PDT 24
Finished Aug 04 05:26:41 PM PDT 24
Peak memory 241884 kb
Host smart-f9a19c89-75da-4714-a278-94b9f4c18be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536201112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.536201112
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.1243576180
Short name T523
Test name
Test status
Simulation time 158040053 ps
CPU time 4.24 seconds
Started Aug 04 05:26:36 PM PDT 24
Finished Aug 04 05:26:40 PM PDT 24
Peak memory 241828 kb
Host smart-40e9006d-ffc9-4a76-b82c-b928e2a763c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243576180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.1243576180
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.4152805956
Short name T762
Test name
Test status
Simulation time 53830599695 ps
CPU time 1628.15 seconds
Started Aug 04 05:26:36 PM PDT 24
Finished Aug 04 05:53:44 PM PDT 24
Peak memory 527168 kb
Host smart-a0dd59b0-900c-4608-b47b-8ec6685d88bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152805956 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.4152805956
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.835227099
Short name T490
Test name
Test status
Simulation time 1836064029 ps
CPU time 5.38 seconds
Started Aug 04 05:26:34 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 242040 kb
Host smart-2e926e77-c8a2-409e-998f-05eb57342b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835227099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.835227099
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.1615008098
Short name T791
Test name
Test status
Simulation time 345899814 ps
CPU time 4.94 seconds
Started Aug 04 05:26:40 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 241808 kb
Host smart-449dcde1-7cc9-41e9-8422-b098b004d1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615008098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1615008098
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.2086885415
Short name T611
Test name
Test status
Simulation time 67525164645 ps
CPU time 921.21 seconds
Started Aug 04 05:26:36 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 279232 kb
Host smart-ff5186c0-5add-4675-90f5-bcbe4c46abc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086885415 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.2086885415
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.3599306054
Short name T1078
Test name
Test status
Simulation time 100827010 ps
CPU time 3.93 seconds
Started Aug 04 05:26:36 PM PDT 24
Finished Aug 04 05:26:40 PM PDT 24
Peak memory 242192 kb
Host smart-bb8f1d0c-2ac3-4f31-a0d3-39660c93f26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599306054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3599306054
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.1693144397
Short name T696
Test name
Test status
Simulation time 437771391 ps
CPU time 4.92 seconds
Started Aug 04 05:26:38 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 242008 kb
Host smart-bdefa958-f6cd-496c-9b08-43f23213ac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693144397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1693144397
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.2360881196
Short name T553
Test name
Test status
Simulation time 187108650 ps
CPU time 4.22 seconds
Started Aug 04 05:26:37 PM PDT 24
Finished Aug 04 05:26:42 PM PDT 24
Peak memory 242024 kb
Host smart-d2759c0b-f843-4b2e-8ca4-38eef1c5046d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360881196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2360881196
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.1110401735
Short name T1102
Test name
Test status
Simulation time 803615896 ps
CPU time 5.16 seconds
Started Aug 04 05:26:38 PM PDT 24
Finished Aug 04 05:26:44 PM PDT 24
Peak memory 242192 kb
Host smart-5b04754f-28c4-4142-b5a0-e57888be98c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110401735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.1110401735
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.284727623
Short name T818
Test name
Test status
Simulation time 67572641 ps
CPU time 2.07 seconds
Started Aug 04 05:24:49 PM PDT 24
Finished Aug 04 05:24:51 PM PDT 24
Peak memory 240468 kb
Host smart-df0138ab-b48f-4b15-b5e5-1fcc167cb6cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284727623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.284727623
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.3008370640
Short name T71
Test name
Test status
Simulation time 7740051089 ps
CPU time 16.6 seconds
Started Aug 04 05:24:48 PM PDT 24
Finished Aug 04 05:25:04 PM PDT 24
Peak memory 243124 kb
Host smart-07729a6b-18b0-4bc1-bb14-30cce3301c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008370640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.3008370640
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.1075717358
Short name T43
Test name
Test status
Simulation time 1322498531 ps
CPU time 25.54 seconds
Started Aug 04 05:24:49 PM PDT 24
Finished Aug 04 05:25:14 PM PDT 24
Peak memory 248572 kb
Host smart-d569172b-fa35-44d2-ac4c-db58c2b758f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075717358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.1075717358
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.3710077291
Short name T898
Test name
Test status
Simulation time 3406882253 ps
CPU time 29.12 seconds
Started Aug 04 05:24:48 PM PDT 24
Finished Aug 04 05:25:17 PM PDT 24
Peak memory 242856 kb
Host smart-c6ca5b9f-29de-4b72-a8e0-6fd2b89da36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710077291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3710077291
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.2470771498
Short name T616
Test name
Test status
Simulation time 7297543117 ps
CPU time 13.13 seconds
Started Aug 04 05:24:48 PM PDT 24
Finished Aug 04 05:25:02 PM PDT 24
Peak memory 242996 kb
Host smart-7b676620-15f6-4ce3-95fe-ec95df4b0b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470771498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2470771498
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.4124827850
Short name T54
Test name
Test status
Simulation time 1773480753 ps
CPU time 5.77 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:24:53 PM PDT 24
Peak memory 242280 kb
Host smart-6615e2e1-c846-4934-88aa-ee71ae535460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124827850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.4124827850
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.2809342541
Short name T477
Test name
Test status
Simulation time 14073008857 ps
CPU time 32.91 seconds
Started Aug 04 05:24:49 PM PDT 24
Finished Aug 04 05:25:22 PM PDT 24
Peak memory 243460 kb
Host smart-be1aa213-c999-47e6-b179-71652d38fc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809342541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2809342541
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.2432267087
Short name T1076
Test name
Test status
Simulation time 550470810 ps
CPU time 5.53 seconds
Started Aug 04 05:24:49 PM PDT 24
Finished Aug 04 05:24:55 PM PDT 24
Peak memory 241888 kb
Host smart-3201eaed-5ad7-4d3e-9904-a9d66261ead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432267087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2432267087
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.1749025260
Short name T891
Test name
Test status
Simulation time 5619250621 ps
CPU time 20.03 seconds
Started Aug 04 05:24:44 PM PDT 24
Finished Aug 04 05:25:04 PM PDT 24
Peak memory 248652 kb
Host smart-7de586c6-420a-4011-87bf-a4fb8a817cf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749025260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.1749025260
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.800590587
Short name T1166
Test name
Test status
Simulation time 1878465657 ps
CPU time 6.5 seconds
Started Aug 04 05:24:49 PM PDT 24
Finished Aug 04 05:24:56 PM PDT 24
Peak memory 241988 kb
Host smart-bf9f6f3d-ce14-4443-9958-761c3354cb49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800590587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.800590587
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.2992180335
Short name T447
Test name
Test status
Simulation time 1159932265 ps
CPU time 16.41 seconds
Started Aug 04 05:24:47 PM PDT 24
Finished Aug 04 05:25:04 PM PDT 24
Peak memory 241920 kb
Host smart-b1a5dccd-9cd7-4f8e-baed-4c0306451290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992180335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.2992180335
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.3915657207
Short name T989
Test name
Test status
Simulation time 59935448801 ps
CPU time 140.37 seconds
Started Aug 04 05:24:49 PM PDT 24
Finished Aug 04 05:27:10 PM PDT 24
Peak memory 246904 kb
Host smart-77c07342-b589-4f9b-852f-080e6c12d6ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915657207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
3915657207
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.3132292277
Short name T304
Test name
Test status
Simulation time 99492152446 ps
CPU time 587.8 seconds
Started Aug 04 05:24:49 PM PDT 24
Finished Aug 04 05:34:37 PM PDT 24
Peak memory 265032 kb
Host smart-6713933f-78a6-4d76-b882-b46f98b5c6fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132292277 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.3132292277
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.1407720518
Short name T672
Test name
Test status
Simulation time 1244084028 ps
CPU time 6.79 seconds
Started Aug 04 05:24:51 PM PDT 24
Finished Aug 04 05:24:58 PM PDT 24
Peak memory 242032 kb
Host smart-57cd019e-b1d1-442a-8261-48e7c3c25515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407720518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1407720518
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.747097923
Short name T430
Test name
Test status
Simulation time 446028025 ps
CPU time 4.75 seconds
Started Aug 04 05:26:38 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 242064 kb
Host smart-ea329e96-dbfd-4229-93af-f57bc06a110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747097923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.747097923
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.2850631304
Short name T600
Test name
Test status
Simulation time 746656880 ps
CPU time 10.45 seconds
Started Aug 04 05:26:38 PM PDT 24
Finished Aug 04 05:26:48 PM PDT 24
Peak memory 242208 kb
Host smart-23165264-0eef-42ef-9bd4-e10f70d21034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850631304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2850631304
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.167651800
Short name T244
Test name
Test status
Simulation time 37218615931 ps
CPU time 424.38 seconds
Started Aug 04 05:26:38 PM PDT 24
Finished Aug 04 05:33:42 PM PDT 24
Peak memory 302900 kb
Host smart-e3442aa4-230c-4924-87b2-a18bb0ce3e62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167651800 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.167651800
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.2641185103
Short name T385
Test name
Test status
Simulation time 632857400 ps
CPU time 17.99 seconds
Started Aug 04 05:26:37 PM PDT 24
Finished Aug 04 05:26:55 PM PDT 24
Peak memory 242044 kb
Host smart-dbae0c82-c335-4eb2-a70c-ac0307ca7157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641185103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2641185103
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.3341843590
Short name T964
Test name
Test status
Simulation time 145196053 ps
CPU time 4.32 seconds
Started Aug 04 05:26:42 PM PDT 24
Finished Aug 04 05:26:46 PM PDT 24
Peak memory 242012 kb
Host smart-855b08ef-bfce-4684-bcf3-8674d50290d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341843590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.3341843590
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.3215713074
Short name T706
Test name
Test status
Simulation time 287013926 ps
CPU time 8.12 seconds
Started Aug 04 05:26:38 PM PDT 24
Finished Aug 04 05:26:47 PM PDT 24
Peak memory 241992 kb
Host smart-66b6bc15-e711-4725-8892-b6472e26a746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215713074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3215713074
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.666275136
Short name T662
Test name
Test status
Simulation time 178432327465 ps
CPU time 884.04 seconds
Started Aug 04 05:26:39 PM PDT 24
Finished Aug 04 05:41:23 PM PDT 24
Peak memory 265056 kb
Host smart-23827c34-45b4-4866-8fca-7c1326d701cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666275136 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.666275136
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.974289884
Short name T170
Test name
Test status
Simulation time 157887557 ps
CPU time 4.06 seconds
Started Aug 04 05:26:38 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 242192 kb
Host smart-ad6bfc67-c968-41f3-adcb-e87b0d3111b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974289884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.974289884
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.207173902
Short name T337
Test name
Test status
Simulation time 676855816 ps
CPU time 10.22 seconds
Started Aug 04 05:26:38 PM PDT 24
Finished Aug 04 05:26:49 PM PDT 24
Peak memory 241808 kb
Host smart-66b43c16-5bcc-4565-91de-898c4d3ded36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207173902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.207173902
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.4144324391
Short name T935
Test name
Test status
Simulation time 239015437647 ps
CPU time 1682.02 seconds
Started Aug 04 05:26:41 PM PDT 24
Finished Aug 04 05:54:44 PM PDT 24
Peak memory 413068 kb
Host smart-41b30654-09ab-493f-ba3a-aaabd5e1ac69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144324391 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.4144324391
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.1596880758
Short name T426
Test name
Test status
Simulation time 560392779 ps
CPU time 3.56 seconds
Started Aug 04 05:26:41 PM PDT 24
Finished Aug 04 05:26:45 PM PDT 24
Peak memory 242024 kb
Host smart-6959c259-bcbf-42a8-9ed9-2588dcee2638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596880758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.1596880758
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.2007188807
Short name T209
Test name
Test status
Simulation time 14670986171 ps
CPU time 30.15 seconds
Started Aug 04 05:26:41 PM PDT 24
Finished Aug 04 05:27:11 PM PDT 24
Peak memory 241872 kb
Host smart-7bf29ed7-60d9-474f-bab9-288c71bb8c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007188807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2007188807
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.3128392443
Short name T460
Test name
Test status
Simulation time 291777150149 ps
CPU time 843.29 seconds
Started Aug 04 05:26:41 PM PDT 24
Finished Aug 04 05:40:45 PM PDT 24
Peak memory 305564 kb
Host smart-56f0359d-02b3-430a-9d86-aba0baa7b8f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128392443 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.3128392443
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.1995497962
Short name T410
Test name
Test status
Simulation time 190353891 ps
CPU time 3.71 seconds
Started Aug 04 05:26:45 PM PDT 24
Finished Aug 04 05:26:49 PM PDT 24
Peak memory 242172 kb
Host smart-0e7ccfe9-b7c2-44a1-92b4-a831a0a58566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995497962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.1995497962
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.709136986
Short name T1150
Test name
Test status
Simulation time 649502108 ps
CPU time 8.65 seconds
Started Aug 04 05:26:43 PM PDT 24
Finished Aug 04 05:26:51 PM PDT 24
Peak memory 242176 kb
Host smart-8d4214bf-6f8b-40ec-ac9d-55ead4d56eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709136986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.709136986
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.3055290564
Short name T953
Test name
Test status
Simulation time 119678969 ps
CPU time 4.77 seconds
Started Aug 04 05:26:44 PM PDT 24
Finished Aug 04 05:26:49 PM PDT 24
Peak memory 242316 kb
Host smart-4805dc61-614f-48e1-9baf-51f1aa04a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055290564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.3055290564
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.4056290251
Short name T704
Test name
Test status
Simulation time 386556970 ps
CPU time 6.11 seconds
Started Aug 04 05:26:44 PM PDT 24
Finished Aug 04 05:26:51 PM PDT 24
Peak memory 241808 kb
Host smart-111a681d-5bc0-4ff8-9fab-e2cfc1cd07a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056290251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.4056290251
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1663470275
Short name T608
Test name
Test status
Simulation time 25428935597 ps
CPU time 536.92 seconds
Started Aug 04 05:26:41 PM PDT 24
Finished Aug 04 05:35:38 PM PDT 24
Peak memory 248824 kb
Host smart-ee539a55-f6dd-48c0-94fe-de855b9cd533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663470275 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1663470275
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.2976528600
Short name T81
Test name
Test status
Simulation time 2161365924 ps
CPU time 5.65 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:26:52 PM PDT 24
Peak memory 242468 kb
Host smart-289a1b58-be0d-4d9e-a2bd-8231a67dc891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976528600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.2976528600
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.3812536231
Short name T1103
Test name
Test status
Simulation time 2865971779 ps
CPU time 6.78 seconds
Started Aug 04 05:26:43 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 241904 kb
Host smart-6b659b81-ad1a-4b88-82b1-7bc7925b3388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812536231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3812536231
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.2744635864
Short name T643
Test name
Test status
Simulation time 104470930032 ps
CPU time 638.42 seconds
Started Aug 04 05:26:44 PM PDT 24
Finished Aug 04 05:37:23 PM PDT 24
Peak memory 259136 kb
Host smart-a8670421-09f7-4933-a397-7e78494d9798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744635864 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.2744635864
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.2297920626
Short name T570
Test name
Test status
Simulation time 256686777 ps
CPU time 3.45 seconds
Started Aug 04 05:26:43 PM PDT 24
Finished Aug 04 05:26:46 PM PDT 24
Peak memory 242308 kb
Host smart-7676f363-25ed-4258-8412-746f3cadd501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297920626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.2297920626
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.2247772356
Short name T588
Test name
Test status
Simulation time 454460191 ps
CPU time 5.52 seconds
Started Aug 04 05:26:44 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 242360 kb
Host smart-bbf1156a-cde1-4709-90b0-6c2e050e551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247772356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2247772356
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.712117541
Short name T823
Test name
Test status
Simulation time 108901101511 ps
CPU time 801.56 seconds
Started Aug 04 05:26:42 PM PDT 24
Finished Aug 04 05:40:03 PM PDT 24
Peak memory 289464 kb
Host smart-1f02248d-2836-4fa0-a9f8-2e88b1c02fed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712117541 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.712117541
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.3662568083
Short name T774
Test name
Test status
Simulation time 151114512 ps
CPU time 4.33 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 242140 kb
Host smart-8e6c0870-ad94-4286-a89c-257ffe09b74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662568083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3662568083
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.418501130
Short name T512
Test name
Test status
Simulation time 2561399133 ps
CPU time 22.83 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:27:09 PM PDT 24
Peak memory 241928 kb
Host smart-a3acbada-a85f-46c6-80c4-ce45bcf98247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418501130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.418501130
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2942083490
Short name T557
Test name
Test status
Simulation time 73691462446 ps
CPU time 800.52 seconds
Started Aug 04 05:26:43 PM PDT 24
Finished Aug 04 05:40:04 PM PDT 24
Peak memory 265076 kb
Host smart-e046c96c-2f48-4239-83de-58900d4561be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942083490 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2942083490
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.1867175529
Short name T1036
Test name
Test status
Simulation time 209436395 ps
CPU time 3.11 seconds
Started Aug 04 05:24:53 PM PDT 24
Finished Aug 04 05:24:56 PM PDT 24
Peak memory 240796 kb
Host smart-216c242f-50d5-49eb-ae6d-34a3457c083a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867175529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.1867175529
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.3270867848
Short name T1181
Test name
Test status
Simulation time 982502466 ps
CPU time 24.84 seconds
Started Aug 04 05:24:49 PM PDT 24
Finished Aug 04 05:25:14 PM PDT 24
Peak memory 242548 kb
Host smart-2aaeb5de-3365-4e10-bbf2-7aa4f06e50a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270867848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.3270867848
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.480119219
Short name T1146
Test name
Test status
Simulation time 2750321814 ps
CPU time 29.43 seconds
Started Aug 04 05:24:48 PM PDT 24
Finished Aug 04 05:25:18 PM PDT 24
Peak memory 242328 kb
Host smart-a2e756c9-94da-4ed9-ab6d-a7ca6eb87403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480119219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.480119219
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.1756717126
Short name T555
Test name
Test status
Simulation time 2042628061 ps
CPU time 27.98 seconds
Started Aug 04 05:24:50 PM PDT 24
Finished Aug 04 05:25:19 PM PDT 24
Peak memory 242064 kb
Host smart-ae21da4c-54ac-4a03-96ab-5b27b1a4c8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756717126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1756717126
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.3736783740
Short name T257
Test name
Test status
Simulation time 847443206 ps
CPU time 13.44 seconds
Started Aug 04 05:24:55 PM PDT 24
Finished Aug 04 05:25:08 PM PDT 24
Peak memory 242112 kb
Host smart-cc83c422-0fb8-4286-b2a8-1c8754a344b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736783740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3736783740
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.855215196
Short name T723
Test name
Test status
Simulation time 494462981 ps
CPU time 4.57 seconds
Started Aug 04 05:24:50 PM PDT 24
Finished Aug 04 05:24:55 PM PDT 24
Peak memory 242212 kb
Host smart-5465c60f-636c-4b4b-9c29-1cf6ff0ee353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855215196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.855215196
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.4104975907
Short name T656
Test name
Test status
Simulation time 1871661372 ps
CPU time 16.52 seconds
Started Aug 04 05:24:49 PM PDT 24
Finished Aug 04 05:25:06 PM PDT 24
Peak memory 246936 kb
Host smart-52dc1008-2d03-49e5-8342-e5a6d37510e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104975907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.4104975907
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.356907616
Short name T178
Test name
Test status
Simulation time 1245741952 ps
CPU time 27.92 seconds
Started Aug 04 05:24:50 PM PDT 24
Finished Aug 04 05:25:18 PM PDT 24
Peak memory 242312 kb
Host smart-3cf78ad1-4ba5-4d45-92aa-b3d2a866f3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356907616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.356907616
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.838872377
Short name T940
Test name
Test status
Simulation time 479367115 ps
CPU time 15.45 seconds
Started Aug 04 05:24:52 PM PDT 24
Finished Aug 04 05:25:07 PM PDT 24
Peak memory 241996 kb
Host smart-911a850a-31a6-4bdc-bd4d-c6e60c575ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838872377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.838872377
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.1362700856
Short name T925
Test name
Test status
Simulation time 863277205 ps
CPU time 18.31 seconds
Started Aug 04 05:24:52 PM PDT 24
Finished Aug 04 05:25:10 PM PDT 24
Peak memory 242084 kb
Host smart-cf8c630b-25c5-4a38-9c14-913b7169dbc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362700856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.1362700856
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.2416352622
Short name T271
Test name
Test status
Simulation time 5486704748 ps
CPU time 14.3 seconds
Started Aug 04 05:24:55 PM PDT 24
Finished Aug 04 05:25:09 PM PDT 24
Peak memory 241944 kb
Host smart-f68a7ec6-fac6-4edb-a392-e7afd1258fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416352622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.2416352622
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.515906307
Short name T256
Test name
Test status
Simulation time 447219973 ps
CPU time 4.02 seconds
Started Aug 04 05:24:51 PM PDT 24
Finished Aug 04 05:24:56 PM PDT 24
Peak memory 241780 kb
Host smart-8c08a1c9-fe33-494c-a7fa-39d80803eec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515906307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.515906307
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.647868352
Short name T747
Test name
Test status
Simulation time 40386770782 ps
CPU time 90.13 seconds
Started Aug 04 05:24:53 PM PDT 24
Finished Aug 04 05:26:24 PM PDT 24
Peak memory 258596 kb
Host smart-80bf4529-ecf5-451b-b164-d8fd35b59911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647868352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.647868352
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.339880402
Short name T436
Test name
Test status
Simulation time 73741322443 ps
CPU time 2045.04 seconds
Started Aug 04 05:24:58 PM PDT 24
Finished Aug 04 05:59:03 PM PDT 24
Peak memory 349988 kb
Host smart-2c96556b-1073-45ec-a4ad-a95178e75b47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339880402 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.339880402
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.1226543211
Short name T901
Test name
Test status
Simulation time 947150059 ps
CPU time 15.53 seconds
Started Aug 04 05:24:53 PM PDT 24
Finished Aug 04 05:25:08 PM PDT 24
Peak memory 248536 kb
Host smart-5c22167d-780a-4b38-898c-e9c5ccc0e6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226543211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1226543211
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.1498089200
Short name T676
Test name
Test status
Simulation time 126904225 ps
CPU time 4.74 seconds
Started Aug 04 05:26:42 PM PDT 24
Finished Aug 04 05:26:47 PM PDT 24
Peak memory 242184 kb
Host smart-9c511c7f-dfdf-4fcc-8d3c-07934a0d2c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498089200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1498089200
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.1725324308
Short name T1090
Test name
Test status
Simulation time 182415108 ps
CPU time 2.91 seconds
Started Aug 04 05:26:45 PM PDT 24
Finished Aug 04 05:26:48 PM PDT 24
Peak memory 241880 kb
Host smart-1aafa477-ea74-484a-a06e-ad4c10ed308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725324308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.1725324308
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.1034226992
Short name T734
Test name
Test status
Simulation time 98362817385 ps
CPU time 1242.99 seconds
Started Aug 04 05:26:41 PM PDT 24
Finished Aug 04 05:47:25 PM PDT 24
Peak memory 265104 kb
Host smart-a7372b73-d4ad-4e48-a0e9-989133fb1fa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034226992 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.1034226992
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.1822396741
Short name T207
Test name
Test status
Simulation time 179752397 ps
CPU time 3.82 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 242244 kb
Host smart-32d85a7c-07d1-4a30-88ff-476d8add3065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822396741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.1822396741
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.3295065860
Short name T272
Test name
Test status
Simulation time 220263339 ps
CPU time 3.35 seconds
Started Aug 04 05:26:44 PM PDT 24
Finished Aug 04 05:26:47 PM PDT 24
Peak memory 241836 kb
Host smart-548fdb65-2a76-4167-b335-9805c900d31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295065860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3295065860
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.796077374
Short name T15
Test name
Test status
Simulation time 112083697011 ps
CPU time 1054.47 seconds
Started Aug 04 05:26:44 PM PDT 24
Finished Aug 04 05:44:19 PM PDT 24
Peak memory 281536 kb
Host smart-7d97176b-3599-4816-917c-a778d3f5ea04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796077374 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.796077374
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.1491367757
Short name T1087
Test name
Test status
Simulation time 140810976 ps
CPU time 3.91 seconds
Started Aug 04 05:26:43 PM PDT 24
Finished Aug 04 05:26:47 PM PDT 24
Peak memory 241832 kb
Host smart-a21ead83-78db-45cb-a4ac-e83667d26675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491367757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.1491367757
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.3709881409
Short name T1161
Test name
Test status
Simulation time 173970370 ps
CPU time 7.37 seconds
Started Aug 04 05:26:42 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 241840 kb
Host smart-8c5819db-fa6a-464a-a3ed-cb063c39a129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709881409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3709881409
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.3751067119
Short name T873
Test name
Test status
Simulation time 235243332287 ps
CPU time 638.23 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:37:25 PM PDT 24
Peak memory 321652 kb
Host smart-3cf1ba52-9668-4f42-aa23-62781f1415a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751067119 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.3751067119
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.887874689
Short name T492
Test name
Test status
Simulation time 389164020 ps
CPU time 3.94 seconds
Started Aug 04 05:26:44 PM PDT 24
Finished Aug 04 05:26:48 PM PDT 24
Peak memory 241988 kb
Host smart-a69ad4e4-1846-48da-b113-d4e174f5900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887874689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.887874689
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2977699339
Short name T1025
Test name
Test status
Simulation time 385693490 ps
CPU time 6.33 seconds
Started Aug 04 05:26:42 PM PDT 24
Finished Aug 04 05:26:49 PM PDT 24
Peak memory 241972 kb
Host smart-d0ac9d5b-923b-4880-a1a0-719dbd0e55f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977699339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2977699339
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3299908436
Short name T300
Test name
Test status
Simulation time 551963375882 ps
CPU time 1166.31 seconds
Started Aug 04 05:26:42 PM PDT 24
Finished Aug 04 05:46:09 PM PDT 24
Peak memory 420140 kb
Host smart-d3456292-8d00-4554-8474-743f87efe3c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299908436 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.3299908436
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.506596420
Short name T463
Test name
Test status
Simulation time 143471549 ps
CPU time 3.98 seconds
Started Aug 04 05:26:45 PM PDT 24
Finished Aug 04 05:26:49 PM PDT 24
Peak memory 241956 kb
Host smart-bba99441-0a0f-4653-bef4-13e8807fd659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506596420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.506596420
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.801151248
Short name T1056
Test name
Test status
Simulation time 12100794234 ps
CPU time 26.02 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:27:12 PM PDT 24
Peak memory 242072 kb
Host smart-5cd44da9-a26d-4b91-93df-50b8acf160d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801151248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.801151248
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.1004860442
Short name T1023
Test name
Test status
Simulation time 132818381 ps
CPU time 5.17 seconds
Started Aug 04 05:26:45 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 242020 kb
Host smart-92aa6e91-4295-4a5a-bbe0-60af90d241cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004860442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1004860442
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.559709141
Short name T838
Test name
Test status
Simulation time 59972276219 ps
CPU time 426 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:33:52 PM PDT 24
Peak memory 252432 kb
Host smart-3e4ac0eb-f2b3-4688-8b7d-cf8d1e161f83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559709141 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.559709141
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.2285911438
Short name T538
Test name
Test status
Simulation time 148405341 ps
CPU time 4.1 seconds
Started Aug 04 05:26:45 PM PDT 24
Finished Aug 04 05:26:49 PM PDT 24
Peak memory 241984 kb
Host smart-b9f77f43-8728-40fc-83a4-547102eae870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285911438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2285911438
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.2718285107
Short name T772
Test name
Test status
Simulation time 3764717326 ps
CPU time 29.96 seconds
Started Aug 04 05:26:49 PM PDT 24
Finished Aug 04 05:27:19 PM PDT 24
Peak memory 241988 kb
Host smart-0013308c-d1b8-42ed-8da7-633464d8235d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718285107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.2718285107
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2729857094
Short name T468
Test name
Test status
Simulation time 126910245 ps
CPU time 4.24 seconds
Started Aug 04 05:26:47 PM PDT 24
Finished Aug 04 05:26:51 PM PDT 24
Peak memory 241924 kb
Host smart-a9a8c324-c290-4647-8645-32b16b4bff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729857094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2729857094
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.968008052
Short name T510
Test name
Test status
Simulation time 122938475 ps
CPU time 3.14 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 241824 kb
Host smart-cc6ff753-9592-4832-9142-4ae42e58ad67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968008052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.968008052
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.862561073
Short name T1127
Test name
Test status
Simulation time 620651972 ps
CPU time 6.51 seconds
Started Aug 04 05:26:45 PM PDT 24
Finished Aug 04 05:26:51 PM PDT 24
Peak memory 241896 kb
Host smart-4abd5139-f7a4-45e3-9dc3-8bd5651f549e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862561073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.862561073
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.611045282
Short name T1138
Test name
Test status
Simulation time 356482196 ps
CPU time 10.7 seconds
Started Aug 04 05:26:47 PM PDT 24
Finished Aug 04 05:26:57 PM PDT 24
Peak memory 242008 kb
Host smart-ae63591a-307a-48de-95ac-310dfa4f3875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611045282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.611045282
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.2455901087
Short name T370
Test name
Test status
Simulation time 589956144 ps
CPU time 4.28 seconds
Started Aug 04 05:26:49 PM PDT 24
Finished Aug 04 05:26:53 PM PDT 24
Peak memory 242192 kb
Host smart-37861cc6-e3e7-4d1e-8128-7273c96ca945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455901087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2455901087
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.102128692
Short name T1173
Test name
Test status
Simulation time 439501690 ps
CPU time 3.33 seconds
Started Aug 04 05:26:46 PM PDT 24
Finished Aug 04 05:26:50 PM PDT 24
Peak memory 242160 kb
Host smart-d63add57-7f6e-4db8-8f59-b2417ab33385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102128692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.102128692
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.3495640840
Short name T5
Test name
Test status
Simulation time 62999297702 ps
CPU time 677.42 seconds
Started Aug 04 05:26:48 PM PDT 24
Finished Aug 04 05:38:06 PM PDT 24
Peak memory 319376 kb
Host smart-c1b630a3-608f-449e-94b5-a256646da81d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495640840 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.3495640840
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%