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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10190 1 T1 2 T2 2 T3 16
true 16727 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 11161 1 T1 2 T2 3 T3 17
true 16798 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 100 1 T3 4 T67 2 T199 2
others[1] 88 1 T99 2 T67 2 T73 2
others[2] 110 1 T97 2 T99 6 T16 2
others[3] 80 1 T98 2 T16 4 T102 2
others[4] 88 1 T32 2 T97 2 T98 2
others[5] 80 1 T97 2 T73 4 T165 2
others[6] 104 1 T3 2 T16 6 T73 4
others[7] 124 1 T41 2 T198 2 T377 2
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T3 2 T32 2 T16 10
others[1] 92 1 T100 2 T67 2 T198 2
others[2] 76 1 T16 4 T73 2 T378 2
others[3] 114 1 T99 2 T61 2 T16 2
others[4] 54 1 T73 2 T379 2 T118 2
others[5] 76 1 T3 2 T16 2 T380 2
others[6] 80 1 T16 4 T73 4 T379 2
others[7] 104 1 T40 2 T200 2 T268 2
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 108 1 T37 2 T97 2 T173 2
others[1] 114 1 T3 2 T32 2 T16 6
others[2] 120 1 T97 2 T100 2 T41 2
others[3] 96 1 T99 2 T16 2 T268 2
others[4] 106 1 T3 2 T98 2 T16 4
others[5] 92 1 T32 2 T61 2 T16 4
others[6] 100 1 T3 2 T16 4 T67 2
others[7] 108 1 T3 2 T99 2 T61 2
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 50 1 T98 2 T16 4 T118 4
others[1] 80 1 T97 4 T99 2 T16 2
others[2] 62 1 T20 2 T96 2 T16 2
others[3] 76 1 T99 2 T16 2 T73 2
others[4] 54 1 T16 2 T73 2 T268 4
others[5] 68 1 T166 2 T379 2 T381 2
others[6] 68 1 T99 2 T165 2 T118 2
others[7] 62 1 T163 2 T248 2 T382 4
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T32 2 T16 2 T198 4
others[1] 96 1 T3 2 T96 2 T16 4
others[2] 100 1 T98 2 T41 2 T268 2
others[3] 76 1 T40 2 T16 6 T173 2
others[4] 112 1 T32 2 T16 2 T200 2
others[5] 98 1 T98 2 T16 2 T67 2
others[6] 74 1 T67 2 T248 2 T383 2
others[7] 102 1 T97 2 T99 2 T100 2
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 50 1 T3 2 T199 2 T384 4
others[1] 30 1 T16 2 T199 2 T173 2
others[2] 50 1 T102 2 T198 2 T200 2
others[3] 30 1 T199 2 T173 2 T200 2
others[4] 38 1 T198 2 T385 2 T386 2
others[5] 40 1 T40 4 T102 2 T385 2
others[6] 18 1 T173 2 T377 2 T85 2
others[7] 54 1 T164 2 T387 2 T118 2
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 116 1 T32 4 T33 2 T41 2
others[1] 88 1 T3 2 T37 2 T16 4
others[2] 86 1 T98 2 T100 2 T16 2
others[3] 84 1 T100 2 T16 6 T118 4
others[4] 96 1 T32 2 T97 2 T16 2
others[5] 110 1 T3 2 T173 2 T379 2
others[6] 86 1 T3 2 T97 2 T99 2
others[7] 112 1 T32 2 T98 2 T173 2
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T100 2 T61 2 T16 4
others[1] 92 1 T97 2 T98 2 T16 2
others[2] 84 1 T37 2 T97 2 T16 4
others[3] 102 1 T32 2 T98 2 T99 2
others[4] 92 1 T98 2 T73 4 T199 2
others[5] 112 1 T40 2 T16 2 T67 2
others[6] 80 1 T20 2 T379 2 T118 2
others[7] 106 1 T33 2 T99 2 T16 4
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T16 2 T67 4 T198 2
others[1] 72 1 T97 2 T98 2 T16 2
others[2] 76 1 T73 2 T165 2 T173 2
others[3] 94 1 T20 2 T96 2 T32 2
others[4] 104 1 T3 2 T97 2 T16 2
others[5] 106 1 T16 2 T200 2 T201 2
others[6] 102 1 T98 2 T99 2 T67 2
others[7] 128 1 T3 2 T97 2 T16 2
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 116 1 T32 4 T16 2 T67 6
others[1] 94 1 T67 2 T163 2 T377 2
others[2] 70 1 T3 2 T33 2 T16 2
others[3] 98 1 T16 4 T173 2 T201 2
others[4] 102 1 T20 2 T100 2 T61 2
others[5] 90 1 T32 2 T98 4 T102 2
others[6] 84 1 T3 2 T98 2 T166 2
others[7] 112 1 T37 2 T97 2 T16 4
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T3 2 T97 2 T100 2
others[1] 104 1 T5 2 T33 2 T200 2
others[2] 84 1 T16 2 T164 2 T381 2
others[3] 106 1 T99 2 T40 2 T16 2
others[4] 96 1 T3 2 T61 2 T67 2
others[5] 98 1 T198 2 T173 2 T377 2
others[6] 94 1 T16 2 T67 2 T41 2
others[7] 90 1 T20 2 T97 2 T16 2
false 14349 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 18 1 T8 1 T30 1 T247 1
others[1] 40 1 T16 2 T30 1 T206 1
others[2] 18 1 T206 1 T124 1 T208 2
others[3] 30 1 T5 2 T8 1 T10 1
others[4] 28 1 T8 1 T67 2 T30 1
others[5] 28 1 T10 1 T247 1 T206 1
others[6] 29 1 T8 1 T31 1 T247 1
others[7] 30 1 T10 1 T123 1 T206 1
false 14349 1 T1 4 T2 5 T3 21
true 2365 1 T3 4 T5 2 T8 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 25 1 T8 2 T247 1 T206 1
others[1] 32 1 T8 1 T30 2 T310 1
others[2] 36 1 T10 1 T16 2 T30 1
others[3] 14 1 T10 1 T30 1 T206 2
others[4] 29 1 T5 2 T8 1 T247 1
others[5] 30 1 T124 1 T388 1 T389 1
others[6] 28 1 T67 2 T390 2 T206 2
others[7] 27 1 T10 1 T247 1 T178 1
false 11656 1 T1 3 T2 3 T3 18
true 19124 1 T1 4 T2 5 T3 25


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 104 1 T99 2 T61 2 T16 4
others[1] 84 1 T3 2 T16 4 T67 2
others[2] 94 1 T16 2 T102 2 T41 2
others[3] 90 1 T97 2 T99 4 T67 2
others[4] 88 1 T99 2 T165 2 T391 2
others[5] 102 1 T97 2 T98 4 T56 2
others[6] 100 1 T3 2 T97 2 T16 2
others[7] 112 1 T3 2 T32 2 T16 2
false 7724 1 T1 1 T2 3 T3 2
true 16829 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T61 2 T16 2 T200 4
others[1] 80 1 T100 2 T390 2 T391 2
others[2] 96 1 T3 2 T99 2 T16 2
others[3] 68 1 T32 2 T16 2 T102 2
others[4] 80 1 T16 4 T380 2 T118 6
others[5] 80 1 T73 2 T378 2 T149 2
others[6] 92 1 T3 2 T40 2 T16 4
others[7] 98 1 T16 8 T73 4 T198 2
false 6811 1 T1 1 T2 2 T3 2
true 16585 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 114 1 T98 2 T61 2 T16 4
others[1] 106 1 T16 2 T67 2 T173 2
others[2] 102 1 T3 2 T37 2 T32 2
others[3] 100 1 T32 2 T97 2 T199 2
others[4] 94 1 T16 2 T73 2 T268 4
others[5] 112 1 T3 6 T99 2 T100 2
others[6] 102 1 T97 2 T61 2 T41 2
others[7] 114 1 T16 2 T164 2 T379 2
false 7210 1 T1 1 T2 3 T3 2
true 16612 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 26 1 T30 1 T247 1 T178 1
others[1] 20 1 T61 2 T178 1 T392 2
others[2] 23 1 T310 1 T311 1 T203 2
others[3] 31 1 T8 1 T229 1 T206 1
others[4] 35 1 T30 1 T199 2 T242 1
others[5] 24 1 T206 1 T118 2 T178 2
others[6] 29 1 T31 1 T198 2 T247 1
others[7] 35 1 T247 1 T393 2 T394 2
false 11597 1 T1 3 T2 3 T3 18
true 19094 1 T1 5 T2 6 T3 25


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T16 2 T73 2 T382 2
others[1] 52 1 T165 2 T381 2 T270 2
others[2] 56 1 T98 2 T99 2 T379 2
others[3] 70 1 T99 2 T16 2 T380 2
others[4] 72 1 T20 2 T96 2 T16 4
others[5] 54 1 T97 2 T16 4 T73 2
others[6] 60 1 T99 2 T73 2 T163 2
others[7] 76 1 T97 2 T268 2 T381 2
false 8968 1 T1 1 T2 3 T3 18
true 16837 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 37 1 T31 1 T382 2 T21 2
others[1] 32 1 T9 1 T206 2 T340 1
others[2] 27 1 T247 1 T123 1 T206 1
others[3] 22 1 T206 1 T56 2 T124 1
others[4] 22 1 T31 1 T170 2 T206 1
others[5] 22 1 T30 1 T229 1 T118 2
others[6] 24 1 T8 1 T10 1 T30 1
others[7] 29 1 T10 1 T123 2 T206 1
false 11545 1 T1 3 T2 3 T3 18
true 19057 1 T1 5 T2 6 T3 26


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 78 1 T165 2 T166 2 T200 2
others[1] 104 1 T96 2 T98 2 T67 4
others[2] 98 1 T16 8 T173 2 T383 2
others[3] 78 1 T97 2 T173 4 T200 2
others[4] 102 1 T3 2 T99 2 T166 2
others[5] 82 1 T100 2 T67 2 T173 2
others[6] 94 1 T32 2 T98 2 T16 4
others[7] 98 1 T32 2 T40 2 T16 4
false 7651 1 T1 1 T2 3 T3 2
true 16755 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 24 1 T10 1 T30 2 T31 2
others[1] 21 1 T8 1 T73 2 T206 1
others[2] 24 1 T30 1 T198 2 T178 1
others[3] 28 1 T8 1 T31 2 T123 1
others[4] 18 1 T206 2 T124 2 T395 1
others[5] 30 1 T199 2 T306 2 T124 2
others[6] 39 1 T8 1 T206 1 T310 1
others[7] 43 1 T9 1 T206 1 T311 1
false 11493 1 T1 3 T2 3 T3 18
true 18998 1 T1 4 T2 5 T3 24


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 34 1 T199 2 T387 2 T118 2
others[1] 20 1 T377 2 T384 2 T396 2
others[2] 40 1 T102 4 T397 2 T118 4
others[3] 40 1 T3 2 T173 2 T200 2
others[4] 50 1 T40 2 T198 2 T199 2
others[5] 52 1 T164 2 T173 2 T200 2
others[6] 30 1 T198 2 T199 2 T385 2
others[7] 44 1 T40 2 T16 2 T398 2
false 9904 1 T1 3 T2 3 T3 4
true 16790 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 128 1 T32 6 T99 2 T100 2
others[1] 92 1 T98 2 T16 2 T67 2
others[2] 88 1 T97 2 T100 2 T16 2
others[3] 96 1 T3 2 T41 2 T387 4
others[4] 88 1 T37 2 T98 2 T16 2
others[5] 88 1 T3 2 T16 4 T173 2
others[6] 82 1 T32 2 T97 2 T33 2
others[7] 116 1 T3 2 T41 2 T165 2
false 6873 1 T1 2 T2 2 T3 6
true 16578 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T97 2 T33 2 T16 4
others[1] 84 1 T37 2 T100 2 T16 4
others[2] 100 1 T97 2 T16 2 T73 2
others[3] 78 1 T32 2 T98 2 T16 4
others[4] 84 1 T98 2 T99 2 T40 2
others[5] 112 1 T20 2 T377 2 T391 2
others[6] 90 1 T73 4 T166 2 T377 2
others[7] 102 1 T98 2 T99 2 T16 2
false 6873 1 T1 2 T2 2 T3 6
true 16578 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 118 1 T3 2 T98 2 T16 4
others[1] 90 1 T67 2 T163 2 T200 2
others[2] 108 1 T96 2 T67 2 T73 2
others[3] 86 1 T97 2 T98 2 T100 2
others[4] 96 1 T3 2 T20 2 T32 2
others[5] 96 1 T16 2 T73 2 T118 2
others[6] 76 1 T399 2 T383 2 T118 2
others[7] 110 1 T97 2 T99 6 T73 2
false 6260 1 T1 1 T2 2 T3 1
true 16574 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 94 1 T98 2 T16 6 T67 4
others[1] 102 1 T20 2 T67 2 T165 4
others[2] 86 1 T3 2 T32 2 T97 2
others[3] 128 1 T3 2 T37 2 T98 2
others[4] 68 1 T16 4 T199 2 T201 2
others[5] 96 1 T32 2 T33 2 T102 2
others[6] 100 1 T32 2 T98 2 T16 2
others[7] 92 1 T100 2 T16 2 T163 2
false 6260 1 T1 1 T2 2 T3 1
true 16574 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 72 1 T32 2 T98 2 T56 2
others[1] 78 1 T20 2 T73 2 T268 2
others[2] 48 1 T20 2 T100 2 T67 6
others[3] 68 1 T73 2 T198 2 T199 2
others[4] 68 1 T16 2 T67 4 T118 4
others[5] 76 1 T16 2 T198 2 T268 2
others[6] 80 1 T32 2 T99 2 T16 2
others[7] 64 1 T32 2 T16 4 T102 2
false 6745 1 T1 2 T2 2 T3 7
true 17934 1 T1 4 T2 6 T3 25


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 56 1 T97 2 T100 2 T268 4
others[1] 48 1 T32 2 T201 2 T118 2
others[2] 70 1 T16 4 T67 2 T390 2
others[3] 84 1 T32 2 T67 4 T73 2
others[4] 66 1 T3 2 T173 2 T118 2
others[5] 62 1 T100 2 T67 2 T73 2
others[6] 66 1 T98 2 T100 2 T16 2
others[7] 92 1 T20 2 T16 2 T102 2
false 6745 1 T1 2 T2 2 T3 7
true 17934 1 T1 4 T2 6 T3 25


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 28 1 T3 2 T123 1 T310 1
others[1] 32 1 T8 2 T236 2 T31 1
others[2] 27 1 T8 1 T30 1 T31 1
others[3] 31 1 T8 1 T117 1 T212 2
others[4] 38 1 T9 1 T30 1 T247 1
others[5] 28 1 T10 1 T67 2 T30 2
others[6] 22 1 T10 2 T31 2 T206 1
others[7] 40 1 T8 1 T41 2 T30 1
false 11735 1 T1 3 T2 3 T3 18
true 19208 1 T1 5 T2 6 T3 27


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 70 1 T97 2 T40 2 T102 2
others[1] 104 1 T3 2 T201 2 T248 2
others[2] 96 1 T16 4 T67 2 T381 2
others[3] 86 1 T16 4 T349 2 T165 2
others[4] 106 1 T20 2 T33 2 T16 2
others[5] 84 1 T5 2 T99 2 T100 2
others[6] 100 1 T41 2 T73 2 T164 2
others[7] 110 1 T3 2 T97 2 T73 2
false 7731 1 T1 1 T2 3 T3 2
true 16790 1 T1 4 T2 5 T3 21


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 27 1 T247 1 T310 1 T396 2
others[1] 17 1 T61 2 T31 1 T247 1
others[2] 30 1 T199 2 T178 1 T310 1
others[3] 24 1 T30 1 T242 1 T393 2
others[4] 27 1 T8 1 T203 2 T339 2
others[5] 43 1 T206 1 T118 2 T178 1
others[6] 28 1 T30 1 T400 2 T229 1
others[7] 27 1 T198 2 T247 1 T206 1
false 14349 1 T1 4 T2 5 T3 21
true 2383 1 T1 1 T2 1 T3 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%