Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
otbn_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
otbn_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
otbn_req_during_lc_esc 2 0 2 100.00 100 1 1 0
otbn_req_during_otp_idle 2 0 2 100.00 100 1 1 2
otbn_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
otbn_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable otbn_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11606 1 T1 2 T3 20 T5 8
auto[1] 718 1 T3 4 T8 8 T10 3



Summary for Variable otbn_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11434 1 T1 2 T3 20 T5 8
auto[1] 890 1 T3 4 T8 5 T26 36



Summary for Variable otbn_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for otbn_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 12292 1 T1 2 T3 24 T5 8
lc_esc_on 32 1 T76 1 T118 1 T212 1



Summary for Variable otbn_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2308 1 T3 13 T5 6 T8 2
auto[1] 10016 1 T1 2 T3 11 T5 2



Summary for Variable otbn_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11572 1 T1 2 T3 18 T5 8
auto[1] 752 1 T3 6 T8 6 T10 3



Summary for Variable otbn_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12022 1 T1 2 T3 22 T5 8
auto[1] 302 1 T3 2 T8 1 T10 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%