SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 12 | 0 | 12 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
otbn_req_during_flash_addr_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_flash_data_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
otbn_req_during_otp_idle | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_sram_0_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_sram_1_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 11606 | 1 | T1 | 2 | T3 | 20 | T5 | 8 | ||||
auto[1] | 718 | 1 | T3 | 4 | T8 | 8 | T10 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 11434 | 1 | T1 | 2 | T3 | 20 | T5 | 8 | ||||
auto[1] | 890 | 1 | T3 | 4 | T8 | 5 | T26 | 36 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
lc_esc_off | 12292 | 1 | T1 | 2 | T3 | 24 | T5 | 8 | ||||
lc_esc_on | 32 | 1 | T76 | 1 | T118 | 1 | T212 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2308 | 1 | T3 | 13 | T5 | 6 | T8 | 2 | ||||
auto[1] | 10016 | 1 | T1 | 2 | T3 | 11 | T5 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 11572 | 1 | T1 | 2 | T3 | 18 | T5 | 8 | ||||
auto[1] | 752 | 1 | T3 | 6 | T8 | 6 | T10 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12022 | 1 | T1 | 2 | T3 | 22 | T5 | 8 | ||||
auto[1] | 302 | 1 | T3 | 2 | T8 | 1 | T10 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |