Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	45614	1			T9	43		T37	14		T10	481
access_err	62662	1			T1	2		T2	1		T3	77
write_blank_err	456	1			T9	1		T15	2		T168	1
ecc_uncorr_err	66791	1			T9	307		T15	124		T168	250
ecc_corr_err	1577	1			T37	7		T33	6		T129	1
no_err	88199	1			T1	38		T2	22		T3	55

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	714	1			T9	6		T15	3		T16	4
secret2	23768	1			T1	1		T2	2		T3	22
secret1	30391	1			T1	1		T2	3		T3	19
secret0	34012	1			T1	7		T2	3		T3	7
hw_cfg1	34195	1			T3	7		T8	43		T36	4
hw_cfg0	25837	1			T1	5		T2	6		T3	16
rot_creator_auth_state	19584	1			T1	5		T2	1		T3	10
rot_creator_auth_codesign	20988	1			T1	6		T2	2		T3	15
owner_sw_cfg	20052	1			T1	6		T2	2		T3	12
creator_sw_cfg	20954	1			T1	6		T3	11		T5	4
vendor_test	34804	1			T1	3		T2	4		T3	13

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4879	1			T9	43		T10	465		T236	484
fsm_err	secret1	1832	1			T213	331		T217	84		T237	195
fsm_err	secret0	3914	1			T105	32		T16	28		T135	34
fsm_err	hw_cfg1	2062	1			T129	2		T244	418		T208	181
fsm_err	hw_cfg0	3332	1			T67	204		T136	55		T211	64
fsm_err	rot_creator_auth_state	2815	1			T129	4		T93	249		T136	43
fsm_err	rot_creator_auth_codesign	3203	1			T129	4		T67	140		T135	33
fsm_err	owner_sw_cfg	2942	1			T10	16		T197	36		T90	95
fsm_err	creator_sw_cfg	3623	1			T135	25		T230	253		T343	44
fsm_err	vendor_test	17012	1			T37	14		T33	17		T61	112
access_err	life_cycle	714	1			T9	6		T15	3		T16	4
access_err	secret2	10918	1			T3	17		T5	2		T8	47
access_err	secret1	6258	1			T3	18		T37	3		T20	25
access_err	secret0	5130	1			T1	1		T3	4		T8	1
access_err	hw_cfg1	1185	1			T3	3		T8	5		T37	2
access_err	hw_cfg0	2313	1			T1	1		T3	4		T9	3
access_err	rot_creator_auth_state	5915	1			T3	4		T5	2		T8	26
access_err	rot_creator_auth_codesign	7919	1			T2	1		T3	10		T5	4
access_err	owner_sw_cfg	6918	1			T3	1		T8	28		T9	4
access_err	creator_sw_cfg	7890	1			T3	7		T5	3		T8	35
access_err	vendor_test	7502	1			T3	9		T8	39		T9	3
write_blank_err	secret2	10	1			T182	1		T203	2		T344	1
write_blank_err	secret1	32	1			T227	2		T73	1		T229	2
write_blank_err	secret0	44	1			T9	1		T227	2		T73	1
write_blank_err	hw_cfg1	78	1			T15	1		T168	1		T16	1
write_blank_err	hw_cfg0	27	1			T67	1		T345	1		T346	1
write_blank_err	rot_creator_auth_state	131	1			T16	1		T67	1		T227	1
write_blank_err	rot_creator_auth_codesign	65	1			T15	1		T227	5		T73	1
write_blank_err	owner_sw_cfg	29	1			T120	2		T212	3		T306	3
write_blank_err	creator_sw_cfg	13	1			T340	2		T347	1		T344	2
write_blank_err	vendor_test	27	1			T227	1		T120	1		T246	1
ecc_uncorr_err	secret2	2724	1			T228	35		T190	45		T182	475
ecc_uncorr_err	secret1	13670	1			T129	4		T73	215		T136	108
ecc_uncorr_err	secret0	16808	1			T9	307		T227	337		T202	55
ecc_uncorr_err	hw_cfg1	19938	1			T15	124		T168	250		T129	2
ecc_uncorr_err	hw_cfg0	8074	1			T67	503		T228	30		T345	168
ecc_uncorr_err	rot_creator_auth_state	2120	1			T136	55		T348	27		T174	27
ecc_uncorr_err	rot_creator_auth_codesign	1012	1			T129	3		T228	71		T135	71
ecc_uncorr_err	owner_sw_cfg	1369	1			T202	54		T228	37		T135	77
ecc_uncorr_err	creator_sw_cfg	1076	1			T135	40		T190	59		T194	16
ecc_corr_err	secret2	114	1			T40	3		T61	8		T41	6
ecc_corr_err	secret1	106	1			T40	11		T349	1		T41	4
ecc_corr_err	secret0	180	1			T40	2		T61	4		T349	1
ecc_corr_err	hw_cfg1	344	1			T37	5		T129	1		T40	11
ecc_corr_err	hw_cfg0	283	1			T40	2		T61	9		T349	4
ecc_corr_err	rot_creator_auth_state	143	1			T37	1		T61	14		T349	3
ecc_corr_err	rot_creator_auth_codesign	148	1			T33	1		T40	1		T61	1
ecc_corr_err	owner_sw_cfg	124	1			T33	4		T40	4		T61	1
ecc_corr_err	creator_sw_cfg	135	1			T37	1		T33	1		T40	2
no_err	secret2	5123	1			T1	1		T2	2		T3	5
no_err	secret1	8493	1			T1	1		T2	3		T3	1
no_err	secret0	7936	1			T1	6		T2	3		T3	3
no_err	hw_cfg1	10588	1			T3	4		T8	38		T36	4
no_err	hw_cfg0	11808	1			T1	4		T2	6		T3	12
no_err	rot_creator_auth_state	8460	1			T1	5		T2	1		T3	6
no_err	rot_creator_auth_codesign	8641	1			T1	6		T2	1		T3	5
no_err	owner_sw_cfg	8670	1			T1	6		T2	2		T3	11
no_err	creator_sw_cfg	8217	1			T1	6		T3	4		T5	1
no_err	vendor_test	10263	1			T1	3		T2	4		T3	4

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded