SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 43193 | 1 | T1 | 62 | T3 | 70 | T5 | 336 | ||||
access_err | 62280 | 1 | T3 | 14 | T4 | 564 | T7 | 14 | ||||
write_blank_err | 375 | 1 | T5 | 2 | T14 | 1 | T138 | 2 | ||||
ecc_uncorr_err | 64667 | 1 | T5 | 605 | T14 | 124 | T137 | 58 | ||||
ecc_corr_err | 1215 | 1 | T3 | 3 | T5 | 3 | T137 | 5 | ||||
no_err | 91054 | 1 | T1 | 1 | T2 | 118 | T3 | 50 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 739 | 1 | T5 | 10 | T14 | 8 | T15 | 4 | ||||
secret2 | 24074 | 1 | T2 | 19 | T3 | 4 | T4 | 128 | ||||
secret1 | 26691 | 1 | T2 | 9 | T3 | 5 | T4 | 102 | ||||
secret0 | 36881 | 1 | T2 | 18 | T3 | 7 | T4 | 102 | ||||
hw_cfg1 | 35893 | 1 | T2 | 6 | T4 | 99 | T7 | 8 | ||||
hw_cfg0 | 22038 | 1 | T2 | 4 | T3 | 14 | T4 | 110 | ||||
rot_creator_auth_state | 20544 | 1 | T2 | 8 | T4 | 140 | T7 | 9 | ||||
rot_creator_auth_codesign | 21977 | 1 | T1 | 63 | T2 | 14 | T3 | 17 | ||||
owner_sw_cfg | 21153 | 1 | T2 | 28 | T3 | 8 | T4 | 158 | ||||
creator_sw_cfg | 22040 | 1 | T2 | 5 | T3 | 3 | T4 | 177 | ||||
vendor_test | 30754 | 1 | T2 | 7 | T3 | 79 | T4 | 134 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 2713 | 1 | T148 | 62 | T221 | 66 | T125 | 18 | ||||
fsm_err | secret1 | 3037 | 1 | T175 | 32 | T323 | 40 | T149 | 13 | ||||
fsm_err | secret0 | 3536 | 1 | T198 | 36 | T206 | 346 | T324 | 28 | ||||
fsm_err | hw_cfg1 | 3460 | 1 | T5 | 336 | T158 | 24 | T87 | 71 | ||||
fsm_err | hw_cfg0 | 2595 | 1 | T250 | 121 | T147 | 33 | T235 | 132 | ||||
fsm_err | rot_creator_auth_state | 3797 | 1 | T164 | 36 | T15 | 117 | T87 | 72 | ||||
fsm_err | rot_creator_auth_codesign | 2805 | 1 | T1 | 62 | T325 | 45 | T158 | 24 | ||||
fsm_err | owner_sw_cfg | 3714 | 1 | T6 | 38 | T326 | 19 | T92 | 131 | ||||
fsm_err | creator_sw_cfg | 4255 | 1 | T199 | 275 | T200 | 266 | T158 | 24 | ||||
fsm_err | vendor_test | 13281 | 1 | T3 | 70 | T111 | 260 | T163 | 61 | ||||
access_err | life_cycle | 739 | 1 | T5 | 10 | T14 | 8 | T15 | 4 | ||||
access_err | secret2 | 10970 | 1 | T3 | 2 | T4 | 113 | T7 | 2 | ||||
access_err | secret1 | 5913 | 1 | T10 | 18 | T5 | 103 | T104 | 4 | ||||
access_err | secret0 | 4541 | 1 | T3 | 4 | T4 | 3 | T10 | 16 | ||||
access_err | hw_cfg1 | 1221 | 1 | T4 | 2 | T7 | 1 | T10 | 10 | ||||
access_err | hw_cfg0 | 2159 | 1 | T7 | 2 | T10 | 6 | T5 | 21 | ||||
access_err | rot_creator_auth_state | 6074 | 1 | T4 | 104 | T7 | 1 | T10 | 17 | ||||
access_err | rot_creator_auth_codesign | 8118 | 1 | T4 | 79 | T7 | 4 | T10 | 30 | ||||
access_err | owner_sw_cfg | 7138 | 1 | T3 | 7 | T4 | 88 | T7 | 3 | ||||
access_err | creator_sw_cfg | 7842 | 1 | T4 | 91 | T7 | 1 | T10 | 35 | ||||
access_err | vendor_test | 7565 | 1 | T3 | 1 | T4 | 84 | T10 | 25 | ||||
write_blank_err | secret2 | 13 | 1 | T15 | 1 | T263 | 1 | T327 | 1 | ||||
write_blank_err | secret1 | 20 | 1 | T5 | 1 | T281 | 1 | T328 | 1 | ||||
write_blank_err | secret0 | 54 | 1 | T5 | 1 | T138 | 1 | T88 | 1 | ||||
write_blank_err | hw_cfg1 | 64 | 1 | T14 | 1 | T203 | 1 | T204 | 1 | ||||
write_blank_err | hw_cfg0 | 12 | 1 | T124 | 1 | T140 | 1 | T329 | 1 | ||||
write_blank_err | rot_creator_auth_state | 118 | 1 | T88 | 2 | T330 | 1 | T278 | 2 | ||||
write_blank_err | rot_creator_auth_codesign | 43 | 1 | T88 | 3 | T278 | 2 | T249 | 6 | ||||
write_blank_err | owner_sw_cfg | 18 | 1 | T278 | 2 | T281 | 1 | T331 | 1 | ||||
write_blank_err | creator_sw_cfg | 6 | 1 | T278 | 1 | T240 | 1 | T332 | 2 | ||||
write_blank_err | vendor_test | 27 | 1 | T138 | 1 | T330 | 1 | T281 | 1 | ||||
ecc_uncorr_err | secret2 | 5207 | 1 | T137 | 21 | T15 | 525 | T87 | 76 | ||||
ecc_uncorr_err | secret1 | 8290 | 1 | T5 | 605 | T163 | 111 | T158 | 25 | ||||
ecc_uncorr_err | secret0 | 20179 | 1 | T137 | 15 | T138 | 296 | T88 | 311 | ||||
ecc_uncorr_err | hw_cfg1 | 19595 | 1 | T14 | 124 | T87 | 141 | T203 | 632 | ||||
ecc_uncorr_err | hw_cfg0 | 4918 | 1 | T164 | 76 | T158 | 48 | T333 | 6 | ||||
ecc_uncorr_err | rot_creator_auth_state | 2160 | 1 | T163 | 57 | T164 | 36 | T88 | 459 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 1780 | 1 | T163 | 66 | T164 | 33 | T87 | 70 | ||||
ecc_uncorr_err | owner_sw_cfg | 1119 | 1 | T210 | 44 | T194 | 12 | T159 | 148 | ||||
ecc_uncorr_err | creator_sw_cfg | 1419 | 1 | T137 | 22 | T163 | 73 | T158 | 47 | ||||
ecc_corr_err | secret2 | 74 | 1 | T164 | 1 | T334 | 1 | T263 | 2 | ||||
ecc_corr_err | secret1 | 129 | 1 | T117 | 5 | T334 | 2 | T27 | 2 | ||||
ecc_corr_err | secret0 | 139 | 1 | T5 | 3 | T137 | 1 | T163 | 1 | ||||
ecc_corr_err | hw_cfg1 | 204 | 1 | T137 | 1 | T117 | 1 | T27 | 2 | ||||
ecc_corr_err | hw_cfg0 | 190 | 1 | T3 | 2 | T137 | 1 | T117 | 8 | ||||
ecc_corr_err | rot_creator_auth_state | 118 | 1 | T163 | 2 | T158 | 2 | T27 | 3 | ||||
ecc_corr_err | rot_creator_auth_codesign | 133 | 1 | T137 | 1 | T163 | 2 | T164 | 2 | ||||
ecc_corr_err | owner_sw_cfg | 122 | 1 | T3 | 1 | T137 | 1 | T164 | 1 | ||||
ecc_corr_err | creator_sw_cfg | 106 | 1 | T117 | 3 | T334 | 2 | T27 | 1 | ||||
no_err | secret2 | 5097 | 1 | T2 | 19 | T3 | 2 | T4 | 15 | ||||
no_err | secret1 | 9302 | 1 | T2 | 9 | T3 | 5 | T4 | 102 | ||||
no_err | secret0 | 8432 | 1 | T2 | 18 | T3 | 3 | T4 | 99 | ||||
no_err | hw_cfg1 | 11349 | 1 | T2 | 6 | T4 | 97 | T7 | 7 | ||||
no_err | hw_cfg0 | 12164 | 1 | T2 | 4 | T3 | 12 | T4 | 110 | ||||
no_err | rot_creator_auth_state | 8277 | 1 | T2 | 8 | T4 | 36 | T7 | 8 | ||||
no_err | rot_creator_auth_codesign | 9098 | 1 | T1 | 1 | T2 | 14 | T3 | 17 | ||||
no_err | owner_sw_cfg | 9042 | 1 | T2 | 28 | T4 | 70 | T7 | 12 | ||||
no_err | creator_sw_cfg | 8412 | 1 | T2 | 5 | T3 | 3 | T4 | 86 | ||||
no_err | vendor_test | 9881 | 1 | T2 | 7 | T3 | 8 | T4 | 50 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |