Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	54765	1			T10	82		T13	240		T122	278
access_err	67963	1			T3	44		T6	12		T10	9
write_blank_err	419	1			T6	2		T4	1		T8	1
ecc_uncorr_err	74022	1			T6	370		T4	227		T33	78
ecc_corr_err	1581	1			T6	2		T33	1		T53	6
no_err	96879	1			T3	57		T6	32		T10	33

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	734	1			T6	12		T14	3		T15	12
secret2	27245	1			T3	18		T10	1		T5	15
secret1	30300	1			T3	7		T10	5		T5	9
secret0	39110	1			T3	7		T6	5		T10	6
hw_cfg1	41153	1			T3	10		T6	379		T10	2
hw_cfg0	30406	1			T3	16		T6	5		T10	85
rot_creator_auth_state	26544	1			T3	15		T6	3		T10	3
rot_creator_auth_codesign	23344	1			T3	10		T10	12		T4	4
owner_sw_cfg	20576	1			T3	4		T6	2		T10	4
creator_sw_cfg	22584	1			T3	7		T10	1		T5	13
vendor_test	33633	1			T3	7		T6	12		T10	5

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5045	1			T8	129		T267	12		T105	540
fsm_err	secret1	4906	1			T7	9		T337	15		T266	73
fsm_err	secret0	5311	1			T7	150		T40	178		T8	83
fsm_err	hw_cfg1	4312	1			T122	278		T19	48		T15	291
fsm_err	hw_cfg0	5771	1			T10	82		T340	15		T345	72
fsm_err	rot_creator_auth_state	5586	1			T99	402		T256	390		T243	121
fsm_err	rot_creator_auth_codesign	2514	1			T13	240		T174	56		T227	2
fsm_err	owner_sw_cfg	2085	1			T143	343		T163	53		T207	12
fsm_err	creator_sw_cfg	4433	1			T53	11		T112	74		T151	193
fsm_err	vendor_test	14802	1			T151	258		T84	51		T63	149
access_err	life_cycle	734	1			T6	12		T14	3		T15	12
access_err	secret2	11778	1			T3	14		T33	1		T7	85
access_err	secret1	6715	1			T57	13		T30	140		T31	15
access_err	secret0	5173	1			T3	1		T7	3		T18	3
access_err	hw_cfg1	1370	1			T3	3		T10	2		T122	2
access_err	hw_cfg0	2490	1			T3	8		T40	2		T18	2
access_err	rot_creator_auth_state	6462	1			T3	12		T10	1		T122	1
access_err	rot_creator_auth_codesign	8880	1			T3	2		T10	4		T7	69
access_err	owner_sw_cfg	7714	1			T3	1		T7	51		T53	5
access_err	creator_sw_cfg	8407	1			T3	1		T10	1		T7	62
access_err	vendor_test	8240	1			T3	2		T10	1		T7	48
write_blank_err	secret2	13	1			T15	2		T257	1		T346	1
write_blank_err	secret1	26	1			T143	1		T184	1		T161	1
write_blank_err	secret0	52	1			T83	1		T15	1		T270	1
write_blank_err	hw_cfg1	75	1			T6	2		T4	1		T8	1
write_blank_err	hw_cfg0	20	1			T167	1		T260	1		T282	1
write_blank_err	rot_creator_auth_state	102	1			T244	2		T22	2		T347	1
write_blank_err	rot_creator_auth_codesign	65	1			T15	3		T46	3		T243	2
write_blank_err	owner_sw_cfg	40	1			T243	1		T184	5		T245	2
write_blank_err	creator_sw_cfg	5	1			T83	2		T282	1		T348	2
write_blank_err	vendor_test	21	1			T83	2		T270	1		T144	1
ecc_uncorr_err	secret2	4797	1			T15	898		T227	4		T349	66
ecc_uncorr_err	secret1	8986	1			T233	112		T143	190		T184	444
ecc_uncorr_err	secret0	19303	1			T53	8		T83	660		T15	440
ecc_uncorr_err	hw_cfg1	23365	1			T6	370		T4	227		T8	215
ecc_uncorr_err	hw_cfg0	8738	1			T167	145		T168	5		T174	153
ecc_uncorr_err	rot_creator_auth_state	5001	1			T33	45		T174	123		T349	63
ecc_uncorr_err	rot_creator_auth_codesign	2152	1			T53	12		T168	2		T174	124
ecc_uncorr_err	owner_sw_cfg	867	1			T220	44		T186	10		T163	47
ecc_uncorr_err	creator_sw_cfg	813	1			T33	33		T53	14		T164	34
ecc_corr_err	secret2	117	1			T70	4		T48	1		T233	1
ecc_corr_err	secret1	142	1			T53	1		T63	8		T78	1
ecc_corr_err	secret0	151	1			T33	1		T53	2		T63	1
ecc_corr_err	hw_cfg1	307	1			T6	2		T63	14		T78	2
ecc_corr_err	hw_cfg0	265	1			T63	13		T34	14		T70	17
ecc_corr_err	rot_creator_auth_state	160	1			T63	8		T78	1		T34	12
ecc_corr_err	rot_creator_auth_codesign	127	1			T63	4		T34	2		T174	2
ecc_corr_err	owner_sw_cfg	147	1			T53	3		T34	16		T70	10
ecc_corr_err	creator_sw_cfg	165	1			T63	5		T78	2		T34	4
no_err	secret2	5495	1			T3	4		T10	1		T5	15
no_err	secret1	9525	1			T3	7		T10	5		T5	9
no_err	secret0	9120	1			T3	6		T6	5		T10	6
no_err	hw_cfg1	11724	1			T3	7		T6	5		T4	2
no_err	hw_cfg0	13122	1			T3	8		T6	5		T10	3
no_err	rot_creator_auth_state	9233	1			T3	3		T6	3		T10	2
no_err	rot_creator_auth_codesign	9606	1			T3	8		T10	8		T4	4
no_err	owner_sw_cfg	9723	1			T3	3		T6	2		T10	4
no_err	creator_sw_cfg	8761	1			T3	6		T5	13		T33	3
no_err	vendor_test	10570	1			T3	5		T6	12		T10	4

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded