Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	52299	1			T2	429		T3	546		T4	383
access_err	58465	1			T2	8		T3	62		T4	63
write_blank_err	398	1			T3	1		T11	3		T12	5
ecc_uncorr_err	65691	1			T3	202		T11	334		T108	113
ecc_corr_err	1451	1			T11	1		T26	16		T108	16
no_err	89058	1			T2	41		T3	212		T4	181

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	706	1			T12	2		T13	3		T14	20
secret2	23671	1			T2	2		T3	244		T4	23
secret1	31616	1			T2	3		T3	482		T4	287
secret0	33577	1			T3	23		T4	23		T7	5
hw_cfg1	33413	1			T2	1		T3	18		T4	26
hw_cfg0	25932	1			T2	8		T3	35		T4	41
rot_creator_auth_state	22126	1			T2	3		T3	24		T4	18
rot_creator_auth_codesign	21342	1			T2	9		T3	22		T4	16
owner_sw_cfg	20939	1			T2	7		T3	120		T4	27
creator_sw_cfg	22696	1			T2	439		T3	29		T4	136
vendor_test	31344	1			T2	6		T3	26		T4	30

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4200	1			T12	312		T37	380		T144	94
fsm_err	secret1	6114	1			T3	460		T4	272		T102	119
fsm_err	secret0	2270	1			T144	189		T320	189		T321	64
fsm_err	hw_cfg1	3705	1			T322	81		T226	133		T323	335
fsm_err	hw_cfg0	5049	1			T108	37		T148	248		T324	22
fsm_err	rot_creator_auth_state	4023	1			T235	465		T137	144		T184	44
fsm_err	rot_creator_auth_codesign	4222	1			T102	152		T325	286		T210	33
fsm_err	owner_sw_cfg	3748	1			T3	86		T183	57		T192	51
fsm_err	creator_sw_cfg	4773	1			T2	429		T4	111		T108	47
fsm_err	vendor_test	14195	1			T26	252		T66	77		T108	29
access_err	life_cycle	706	1			T12	2		T13	3		T14	20
access_err	secret2	10352	1			T3	21		T4	17		T5	7
access_err	secret1	5574	1			T26	22		T62	12		T27	26
access_err	secret0	4466	1			T3	2		T4	1		T6	2
access_err	hw_cfg1	1304	1			T3	2		T4	1		T6	4
access_err	hw_cfg0	2179	1			T26	12		T27	6		T52	4
access_err	rot_creator_auth_state	5542	1			T2	3		T3	4		T4	8
access_err	rot_creator_auth_codesign	7512	1			T2	2		T3	5		T4	4
access_err	owner_sw_cfg	6663	1			T3	14		T4	7		T5	3
access_err	creator_sw_cfg	7017	1			T2	2		T3	6		T4	9
access_err	vendor_test	7150	1			T2	1		T3	8		T4	16
write_blank_err	secret2	11	1			T3	1		T11	1		T144	1
write_blank_err	secret1	26	1			T14	1		T37	1		T137	1
write_blank_err	secret0	48	1			T13	1		T194	2		T106	1
write_blank_err	hw_cfg1	64	1			T11	1		T102	1		T106	1
write_blank_err	hw_cfg0	17	1			T12	1		T135	1		T326	1
write_blank_err	rot_creator_auth_state	125	1			T12	4		T105	2		T106	6
write_blank_err	rot_creator_auth_codesign	32	1			T14	1		T106	2		T135	3
write_blank_err	owner_sw_cfg	24	1			T14	1		T135	1		T319	2
write_blank_err	creator_sw_cfg	24	1			T319	3		T262	5		T327	3
write_blank_err	vendor_test	27	1			T11	1		T14	1		T37	1
ecc_uncorr_err	secret2	3818	1			T3	202		T11	334		T144	306
ecc_uncorr_err	secret1	10906	1			T108	28		T14	223		T37	606
ecc_uncorr_err	secret0	18514	1			T13	550		T155	10		T194	456
ecc_uncorr_err	hw_cfg1	17629	1			T102	730		T155	3		T106	398
ecc_uncorr_err	hw_cfg0	6682	1			T12	300		T155	6		T135	142
ecc_uncorr_err	rot_creator_auth_state	4023	1			T108	38		T12	431		T328	65
ecc_uncorr_err	rot_creator_auth_codesign	848	1			T155	9		T329	21		T183	95
ecc_uncorr_err	owner_sw_cfg	1055	1			T210	27		T184	96		T330	38
ecc_uncorr_err	creator_sw_cfg	2216	1			T108	47		T155	4		T183	53
ecc_corr_err	secret2	95	1			T26	1		T184	1		T331	4
ecc_corr_err	secret1	105	1			T26	1		T28	3		T159	1
ecc_corr_err	secret0	165	1			T26	1		T108	10		T28	4
ecc_corr_err	hw_cfg1	334	1			T11	1		T26	4		T108	1
ecc_corr_err	hw_cfg0	266	1			T26	6		T108	4		T38	3
ecc_corr_err	rot_creator_auth_state	130	1			T38	2		T155	1		T28	6
ecc_corr_err	rot_creator_auth_codesign	142	1			T26	2		T38	1		T28	12
ecc_corr_err	owner_sw_cfg	116	1			T26	1		T108	1		T38	4
ecc_corr_err	creator_sw_cfg	98	1			T38	1		T28	2		T329	2
no_err	secret2	5195	1			T2	2		T3	20		T4	6
no_err	secret1	8891	1			T2	3		T3	22		T4	15
no_err	secret0	8114	1			T3	21		T4	22		T7	5
no_err	hw_cfg1	10377	1			T2	1		T3	16		T4	25
no_err	hw_cfg0	11739	1			T2	8		T3	35		T4	41
no_err	rot_creator_auth_state	8283	1			T3	20		T4	10		T7	8
no_err	rot_creator_auth_codesign	8586	1			T2	7		T3	17		T4	12
no_err	owner_sw_cfg	9333	1			T2	7		T3	20		T4	20
no_err	creator_sw_cfg	8568	1			T2	8		T3	23		T4	16
no_err	vendor_test	9972	1			T2	5		T3	18		T4	14

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded