Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
secret1_lock	2	0	2	100.00	100	1	1	2
sram_index	4	0	4	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sram_req_lock_cross	8	0	8	100.00	100	1	1	0

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1570

1

T108

2

T102

27

T28

6

auto[1]

993

1

T102

37

T28

18

T128

3

---

Summary for Variable sram_index

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for sram_index

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x0]	86	1			T102	1		T109	1		T197	7
sram_key[0x1]	811	1			T108	1		T102	23		T28	8
sram_key[0x2]	793	1			T102	21		T28	8		T128	2
sram_key[0x3]	873	1			T108	1		T102	19		T28	8

---

Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for sram_req_lock_cross

Bins

sram_index	secret1_lock	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x0]	auto[0]	51	1			T109	1		T197	3		T239	3
sram_key[0x0]	auto[1]	35	1			T102	1		T197	4		T364	4
sram_key[0x1]	auto[0]	509	1			T108	1		T102	8		T28	2
sram_key[0x1]	auto[1]	302	1			T102	15		T28	6		T128	1
sram_key[0x2]	auto[0]	483	1			T102	10		T28	2		T128	1
sram_key[0x2]	auto[1]	310	1			T102	11		T28	6		T128	1
sram_key[0x3]	auto[0]	527	1			T108	1		T102	9		T28	2
sram_key[0x3]	auto[1]	346	1			T102	10		T28	6		T128	1