Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	52252	1			T4	131		T6	105		T111	296
access_err	63468	1			T1	71		T3	10		T4	91
write_blank_err	465	1			T1	2		T4	7		T11	1
ecc_uncorr_err	65631	1			T1	213		T4	330		T11	368
ecc_corr_err	1434	1			T125	3		T120	1		T122	3
no_err	92319	1			T1	38		T3	38		T4	210

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	806	1			T1	28		T4	10		T11	3
secret2	27037	1			T1	8		T3	2		T4	182
secret1	29048	1			T1	2		T3	9		T4	40
secret0	34215	1			T1	4		T3	4		T4	338
hw_cfg1	37571	1			T1	216		T3	1		T4	20
hw_cfg0	24415	1			T1	2		T3	8		T4	22
rot_creator_auth_state	22880	1			T1	6		T3	5		T4	28
rot_creator_auth_codesign	22589	1			T1	25		T3	2		T4	32
owner_sw_cfg	21410	1			T1	21		T3	4		T4	43
creator_sw_cfg	23459	1			T1	2		T3	5		T4	26
vendor_test	32139	1			T1	10		T3	8		T4	28

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5223	1			T4	131		T6	105		T327	151
fsm_err	secret1	2560	1			T31	39		T78	115		T14	48
fsm_err	secret0	3712	1			T157	19		T162	109		T79	240
fsm_err	hw_cfg1	4418	1			T116	523		T241	58		T144	22
fsm_err	hw_cfg0	4996	1			T328	107		T148	824		T145	162
fsm_err	rot_creator_auth_state	3977	1			T111	296		T238	160		T215	73
fsm_err	rot_creator_auth_codesign	4253	1			T225	648		T207	143		T65	75
fsm_err	owner_sw_cfg	3797	1			T163	249		T329	557		T235	245
fsm_err	creator_sw_cfg	5016	1			T196	347		T135	392		T330	100
fsm_err	vendor_test	14300	1			T119	89		T76	55		T32	26
access_err	life_cycle	806	1			T1	28		T4	10		T11	3
access_err	secret2	10958	1			T1	8		T3	2		T4	22
access_err	secret1	6018	1			T5	27		T120	1		T123	2
access_err	secret0	5061	1			T3	1		T5	21		T11	2
access_err	hw_cfg1	1220	1			T5	1		T10	1		T11	4
access_err	hw_cfg0	2036	1			T5	5		T21	2		T22	9
access_err	rot_creator_auth_state	5957	1			T1	2		T3	1		T4	8
access_err	rot_creator_auth_codesign	8266	1			T1	17		T3	2		T4	4
access_err	owner_sw_cfg	7419	1			T1	13		T3	1		T4	13
access_err	creator_sw_cfg	7948	1			T1	1		T4	15		T5	12
access_err	vendor_test	7779	1			T1	2		T3	3		T4	19
write_blank_err	secret2	13	1			T4	1		T11	1		T161	1
write_blank_err	secret1	27	1			T233	1		T141	2		T331	1
write_blank_err	secret0	47	1			T4	1		T31	2		T162	1
write_blank_err	hw_cfg1	75	1			T1	1		T120	2		T162	1
write_blank_err	hw_cfg0	12	1			T78	1		T332	1		T98	1
write_blank_err	rot_creator_auth_state	128	1			T1	1		T4	1		T162	6
write_blank_err	rot_creator_auth_codesign	60	1			T4	4		T120	2		T333	10
write_blank_err	owner_sw_cfg	22	1			T334	1		T331	4		T335	1
write_blank_err	creator_sw_cfg	34	1			T163	1		T336	1		T78	1
write_blank_err	vendor_test	47	1			T120	1		T231	1		T337	1
ecc_uncorr_err	secret2	5494	1			T4	15		T11	368		T161	620
ecc_uncorr_err	secret1	11104	1			T125	41		T171	24		T173	52
ecc_uncorr_err	secret0	16394	1			T4	315		T125	15		T31	867
ecc_uncorr_err	hw_cfg1	20837	1			T1	213		T125	21		T120	179
ecc_uncorr_err	hw_cfg0	4633	1			T171	39		T170	63		T174	49
ecc_uncorr_err	rot_creator_auth_state	4019	1			T171	9		T207	625		T173	39
ecc_uncorr_err	rot_creator_auth_codesign	718	1			T171	26		T170	60		T113	7
ecc_uncorr_err	owner_sw_cfg	534	1			T171	12		T173	67		T193	22
ecc_uncorr_err	creator_sw_cfg	1898	1			T125	16		T163	399		T171	10
ecc_corr_err	secret2	67	1			T32	4		T39	1		T23	1
ecc_corr_err	secret1	111	1			T125	1		T171	1		T174	2
ecc_corr_err	secret0	122	1			T122	1		T32	1		T173	2
ecc_corr_err	hw_cfg1	284	1			T120	1		T76	5		T32	4
ecc_corr_err	hw_cfg0	266	1			T125	1		T122	1		T76	1
ecc_corr_err	rot_creator_auth_state	150	1			T76	1		T32	1		T171	2
ecc_corr_err	rot_creator_auth_codesign	159	1			T76	2		T32	5		T326	1
ecc_corr_err	owner_sw_cfg	157	1			T125	1		T76	3		T32	4
ecc_corr_err	creator_sw_cfg	118	1			T122	1		T76	1		T32	3
no_err	secret2	5282	1			T4	13		T6	10		T7	2
no_err	secret1	9228	1			T1	2		T3	9		T4	40
no_err	secret0	8879	1			T1	4		T3	3		T4	22
no_err	hw_cfg1	10737	1			T1	2		T3	1		T4	20
no_err	hw_cfg0	12472	1			T1	2		T3	8		T4	22
no_err	rot_creator_auth_state	8649	1			T1	3		T3	4		T4	19
no_err	rot_creator_auth_codesign	9133	1			T1	8		T4	24		T5	28
no_err	owner_sw_cfg	9481	1			T1	8		T3	3		T4	30
no_err	creator_sw_cfg	8445	1			T1	1		T3	5		T4	11
no_err	vendor_test	10013	1			T1	8		T3	5		T4	9

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded