SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 51772 | 1 | T101 | 5 | T63 | 80 | T102 | 89 | ||||
access_err | 56983 | 1 | T1 | 74 | T2 | 1 | T5 | 18 | ||||
write_blank_err | 364 | 1 | T9 | 1 | T6 | 1 | T98 | 1 | ||||
ecc_uncorr_err | 57431 | 1 | T2 | 79 | T9 | 469 | T6 | 645 | ||||
ecc_corr_err | 1330 | 1 | T96 | 4 | T138 | 16 | T50 | 49 | ||||
no_err | 84808 | 1 | T1 | 171 | T2 | 4 | T5 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 570 | 1 | T6 | 2 | T7 | 7 | T13 | 4 | ||||
secret2 | 23536 | 1 | T1 | 28 | T2 | 2 | T5 | 7 | ||||
secret1 | 24794 | 1 | T1 | 24 | T5 | 5 | T9 | 2 | ||||
secret0 | 30803 | 1 | T1 | 24 | T5 | 5 | T9 | 474 | ||||
hw_cfg1 | 41491 | 1 | T1 | 27 | T2 | 39 | T5 | 4 | ||||
hw_cfg0 | 20471 | 1 | T1 | 17 | T5 | 2 | T10 | 46 | ||||
rot_creator_auth_state | 17801 | 1 | T1 | 22 | T5 | 2 | T9 | 2 | ||||
rot_creator_auth_codesign | 20473 | 1 | T1 | 19 | T5 | 1 | T6 | 4 | ||||
owner_sw_cfg | 19203 | 1 | T1 | 32 | T9 | 12 | T6 | 4 | ||||
creator_sw_cfg | 19444 | 1 | T1 | 35 | T2 | 42 | T5 | 4 | ||||
vendor_test | 34102 | 1 | T1 | 17 | T2 | 1 | T5 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 3712 | 1 | T138 | 66 | T206 | 92 | T146 | 6 | ||||
fsm_err | secret1 | 4880 | 1 | T13 | 7 | T12 | 265 | T253 | 1 | ||||
fsm_err | secret0 | 3188 | 1 | T103 | 214 | T62 | 27 | T269 | 207 | ||||
fsm_err | hw_cfg1 | 4630 | 1 | T13 | 170 | T16 | 124 | T113 | 275 | ||||
fsm_err | hw_cfg0 | 5129 | 1 | T101 | 5 | T88 | 609 | T240 | 334 | ||||
fsm_err | rot_creator_auth_state | 2811 | 1 | T248 | 89 | T341 | 127 | T329 | 276 | ||||
fsm_err | rot_creator_auth_codesign | 2839 | 1 | T251 | 384 | T342 | 15 | T189 | 4 | ||||
fsm_err | owner_sw_cfg | 3036 | 1 | T62 | 233 | T146 | 19 | T343 | 52 | ||||
fsm_err | creator_sw_cfg | 3638 | 1 | T102 | 89 | T138 | 53 | T91 | 590 | ||||
fsm_err | vendor_test | 17909 | 1 | T63 | 80 | T50 | 176 | T92 | 18 | ||||
access_err | life_cycle | 570 | 1 | T6 | 2 | T7 | 7 | T13 | 4 | ||||
access_err | secret2 | 10228 | 1 | T1 | 12 | T5 | 6 | T9 | 4 | ||||
access_err | secret1 | 5604 | 1 | T5 | 1 | T10 | 18 | T15 | 7 | ||||
access_err | secret0 | 4498 | 1 | T5 | 4 | T10 | 4 | T24 | 2 | ||||
access_err | hw_cfg1 | 1180 | 1 | T1 | 2 | T2 | 1 | T5 | 2 | ||||
access_err | hw_cfg0 | 2143 | 1 | T10 | 3 | T63 | 1 | T15 | 1 | ||||
access_err | rot_creator_auth_state | 5330 | 1 | T1 | 10 | T5 | 1 | T10 | 33 | ||||
access_err | rot_creator_auth_codesign | 7497 | 1 | T1 | 12 | T10 | 41 | T15 | 7 | ||||
access_err | owner_sw_cfg | 6168 | 1 | T1 | 16 | T9 | 3 | T10 | 2 | ||||
access_err | creator_sw_cfg | 7146 | 1 | T1 | 16 | T5 | 2 | T10 | 19 | ||||
access_err | vendor_test | 6619 | 1 | T1 | 6 | T5 | 2 | T10 | 10 | ||||
write_blank_err | secret2 | 9 | 1 | T7 | 1 | T12 | 1 | T16 | 1 | ||||
write_blank_err | secret1 | 16 | 1 | T344 | 1 | T345 | 1 | T290 | 1 | ||||
write_blank_err | secret0 | 44 | 1 | T9 | 1 | T7 | 1 | T13 | 1 | ||||
write_blank_err | hw_cfg1 | 65 | 1 | T6 | 1 | T98 | 1 | T7 | 1 | ||||
write_blank_err | hw_cfg0 | 7 | 1 | T228 | 1 | T272 | 1 | T281 | 1 | ||||
write_blank_err | rot_creator_auth_state | 94 | 1 | T178 | 1 | T12 | 1 | T16 | 2 | ||||
write_blank_err | rot_creator_auth_codesign | 70 | 1 | T13 | 5 | T62 | 1 | T346 | 1 | ||||
write_blank_err | owner_sw_cfg | 21 | 1 | T13 | 1 | T347 | 1 | T348 | 3 | ||||
write_blank_err | creator_sw_cfg | 18 | 1 | T13 | 5 | T12 | 5 | T349 | 1 | ||||
write_blank_err | vendor_test | 20 | 1 | T13 | 1 | T228 | 1 | T347 | 1 | ||||
ecc_uncorr_err | secret2 | 4524 | 1 | T7 | 705 | T12 | 515 | T16 | 306 | ||||
ecc_uncorr_err | secret1 | 5760 | 1 | T138 | 122 | T146 | 39 | T139 | 21 | ||||
ecc_uncorr_err | secret0 | 15212 | 1 | T9 | 469 | T96 | 44 | T7 | 172 | ||||
ecc_uncorr_err | hw_cfg1 | 25674 | 1 | T2 | 38 | T6 | 645 | T98 | 195 | ||||
ecc_uncorr_err | hw_cfg0 | 1763 | 1 | T146 | 20 | T149 | 139 | T228 | 118 | ||||
ecc_uncorr_err | rot_creator_auth_state | 1067 | 1 | T146 | 21 | T350 | 2 | T127 | 164 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 1254 | 1 | T138 | 159 | T62 | 410 | T146 | 24 | ||||
ecc_uncorr_err | owner_sw_cfg | 1389 | 1 | T146 | 17 | T139 | 8 | T351 | 37 | ||||
ecc_uncorr_err | creator_sw_cfg | 788 | 1 | T2 | 41 | T146 | 18 | T149 | 62 | ||||
ecc_corr_err | secret2 | 82 | 1 | T50 | 2 | T146 | 3 | T43 | 2 | ||||
ecc_corr_err | secret1 | 118 | 1 | T138 | 3 | T50 | 10 | T92 | 1 | ||||
ecc_corr_err | secret0 | 140 | 1 | T138 | 1 | T50 | 1 | T139 | 1 | ||||
ecc_corr_err | hw_cfg1 | 239 | 1 | T96 | 3 | T50 | 8 | T146 | 2 | ||||
ecc_corr_err | hw_cfg0 | 246 | 1 | T138 | 3 | T50 | 11 | T351 | 1 | ||||
ecc_corr_err | rot_creator_auth_state | 106 | 1 | T50 | 2 | T92 | 2 | T146 | 1 | ||||
ecc_corr_err | rot_creator_auth_codesign | 137 | 1 | T138 | 7 | T50 | 3 | T139 | 3 | ||||
ecc_corr_err | owner_sw_cfg | 102 | 1 | T96 | 1 | T138 | 1 | T50 | 12 | ||||
ecc_corr_err | creator_sw_cfg | 160 | 1 | T138 | 1 | T146 | 7 | T139 | 4 | ||||
no_err | secret2 | 4981 | 1 | T1 | 16 | T2 | 2 | T5 | 1 | ||||
no_err | secret1 | 8416 | 1 | T1 | 24 | T5 | 4 | T9 | 2 | ||||
no_err | secret0 | 7721 | 1 | T1 | 24 | T5 | 1 | T9 | 4 | ||||
no_err | hw_cfg1 | 9703 | 1 | T1 | 25 | T5 | 2 | T9 | 2 | ||||
no_err | hw_cfg0 | 11183 | 1 | T1 | 17 | T5 | 2 | T10 | 43 | ||||
no_err | rot_creator_auth_state | 8393 | 1 | T1 | 12 | T5 | 1 | T9 | 2 | ||||
no_err | rot_creator_auth_codesign | 8676 | 1 | T1 | 7 | T5 | 1 | T6 | 4 | ||||
no_err | owner_sw_cfg | 8487 | 1 | T1 | 16 | T9 | 9 | T6 | 4 | ||||
no_err | creator_sw_cfg | 7694 | 1 | T1 | 19 | T2 | 1 | T5 | 2 | ||||
no_err | vendor_test | 9554 | 1 | T1 | 11 | T2 | 1 | T5 | 10 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |