Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

766

1

T12

7

T59

11

T14

4

all_values[1]

766

1

T12

7

T59

11

T14

4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

847

1

T12

8

T59

13

T14

5

auto[1]

685

1

T12

6

T59

9

T14

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

646

1

T12

5

T59

12

T14

5

auto[1]

886

1

T12

9

T59

10

T14

3

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

938

1

T12

9

T59

18

T14

5

auto[1]

594

1

T12

5

T59

4

T14

3

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

173

1

T12

3

T14

1

T95

1

all_values[0]

auto[0]

auto[0]

auto[1]

82

1

T12

1

T59

1

T141

2

all_values[0]

auto[0]

auto[1]

auto[0]

150

1

T12

1

T59

3

T14

2

all_values[0]

auto[0]

auto[1]

auto[1]

67

1

T59

4

T141

1

T97

2

all_values[0]

auto[1]

auto[0]

auto[1]

178

1

T12

1

T59

2

T14

1

all_values[0]

auto[1]

auto[1]

auto[1]

116

1

T12

1

T59

1

T141

1

all_values[1]

auto[0]

auto[0]

auto[0]

186

1

T59

8

T14

2

T95

1

all_values[1]

auto[0]

auto[0]

auto[1]

72

1

T12

2

T59

1

T95

1

all_values[1]

auto[0]

auto[1]

auto[0]

137

1

T12

1

T59

1

T142

4

all_values[1]

auto[0]

auto[1]

auto[1]

71

1

T12

1

T97

3

T152

1

all_values[1]

auto[1]

auto[0]

auto[1]

156

1

T12

1

T59

1

T14

1

all_values[1]

auto[1]

auto[1]

auto[1]

144

1

T12

2

T14

1

T95

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal