Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
flash_addr_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_lc_esc	2	0	2	100.00	100	1	1	0
flash_addr_req_during_otbn_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_otp_idle	2	0	2	100.00	100	1	1	2
flash_addr_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable flash_addr_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9138

1

T1

8

T3

163

T4

10

auto[1]

1656

1

T3

9

T5

1

T15

1

---

Summary for Variable flash_addr_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for flash_addr_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

10770

1

T1

8

T3

172

T4

10

lc_esc_on

24

1

T6

1

T143

1

T95

1

---

Summary for Variable flash_addr_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10064

1

T1

5

T3

167

T4

10

auto[1]

730

1

T1

3

T3

5

T6

2

---

Summary for Variable flash_addr_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1796

1

T1

4

T3

77

T100

3

auto[1]

8998

1

T1

4

T3

95

T4

10

---

Summary for Variable flash_addr_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10172

1

T1

5

T3

157

T4

10

auto[1]

622

1

T1

3

T3

15

T6

3

---

Summary for Variable flash_addr_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10537

1

T1

8

T3

161

T4

10

auto[1]

257

1

T3

11

T102

2

T105

2