Summary for Variable dai_access_cmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for dai_access_cmd
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
dai_digest |
1906 |
1 |
|
|
T3 |
31 |
|
T5 |
3 |
|
T15 |
7 |
dai_wr |
3888 |
1 |
|
|
T1 |
2 |
|
T3 |
41 |
|
T4 |
1 |
dai_rd |
5954 |
1 |
|
|
T1 |
2 |
|
T3 |
74 |
|
T4 |
1 |
Summary for Variable lc_creator_seed_sw_rw_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_creator_seed_sw_rw_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4576 |
1 |
|
|
T3 |
69 |
|
T4 |
2 |
|
T5 |
1 |
auto[1] |
7172 |
1 |
|
|
T1 |
4 |
|
T3 |
77 |
|
T5 |
8 |
Summary for Cross dai_access_secret2
Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins for dai_access_secret2
Bins
lc_creator_seed_sw_rw_en | dai_access_cmd | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
dai_digest |
875 |
1 |
|
|
T3 |
12 |
|
T15 |
2 |
|
T6 |
15 |
auto[0] |
dai_wr |
1378 |
1 |
|
|
T3 |
20 |
|
T4 |
1 |
|
T15 |
3 |
auto[0] |
dai_rd |
2323 |
1 |
|
|
T3 |
37 |
|
T4 |
1 |
|
T5 |
1 |
auto[1] |
dai_digest |
1031 |
1 |
|
|
T3 |
19 |
|
T5 |
3 |
|
T15 |
5 |
auto[1] |
dai_wr |
2510 |
1 |
|
|
T1 |
2 |
|
T3 |
21 |
|
T5 |
2 |
auto[1] |
dai_rd |
3631 |
1 |
|
|
T1 |
2 |
|
T3 |
37 |
|
T5 |
3 |