Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	41366	1			T2	57		T109	118		T6	358
access_err	53145	1			T1	12		T3	588		T4	6
write_blank_err	352	1			T17	1		T108	1		T20	2
ecc_uncorr_err	55120	1			T4	242		T17	457		T108	280
ecc_corr_err	1501	1			T4	3		T109	8		T66	26
no_err	72233	1			T1	61		T3	687		T4	25

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	579	1			T20	2		T21	10		T8	7
secret2	22113	1			T1	3		T3	133		T4	2
secret1	23623	1			T1	3		T3	149		T4	2
secret0	27006	1			T1	8		T2	57		T3	106
hw_cfg1	29895	1			T1	5		T3	83		T4	131
hw_cfg0	23198	1			T1	5		T3	110		T4	2
rot_creator_auth_state	16462	1			T1	4		T3	111		T4	4
rot_creator_auth_codesign	18175	1			T1	8		T3	152		T4	62
owner_sw_cfg	16965	1			T1	15		T3	108		T4	52
creator_sw_cfg	16303	1			T1	9		T3	164		T4	5
vendor_test	29398	1			T1	13		T3	159		T4	12

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4045	1			T317	119		T323	319		T158	31
fsm_err	secret1	3491	1			T7	71		T140	236		T324	103
fsm_err	secret0	4313	1			T2	57		T156	54		T99	163
fsm_err	hw_cfg1	3213	1			T210	398		T248	276		T250	315
fsm_err	hw_cfg0	4296	1			T143	179		T144	316		T313	1
fsm_err	rot_creator_auth_state	1429	1			T95	24		T125	191		T252	86
fsm_err	rot_creator_auth_codesign	2875	1			T6	183		T325	15		T157	295
fsm_err	owner_sw_cfg	1178	1			T220	46		T159	120		T212	37
fsm_err	creator_sw_cfg	1665	1			T109	118		T326	99		T240	46
fsm_err	vendor_test	14861	1			T6	175		T66	63		T201	50
access_err	life_cycle	579	1			T20	2		T21	10		T8	7
access_err	secret2	8768	1			T3	83		T4	2		T5	2
access_err	secret1	6225	1			T1	2		T3	99		T15	20
access_err	secret0	5069	1			T1	2		T3	71		T4	2
access_err	hw_cfg1	1215	1			T1	1		T3	17		T5	2
access_err	hw_cfg0	2138	1			T3	38		T15	12		T6	60
access_err	rot_creator_auth_state	4418	1			T3	47		T4	1		T5	4
access_err	rot_creator_auth_codesign	6686	1			T1	4		T3	84		T5	4
access_err	owner_sw_cfg	5830	1			T1	1		T3	33		T5	4
access_err	creator_sw_cfg	6320	1			T3	75		T4	1		T5	2
access_err	vendor_test	5897	1			T1	2		T3	41		T5	6
write_blank_err	secret2	10	1			T8	1		T241	1		T327	1
write_blank_err	secret1	20	1			T108	1		T163	1		T328	1
write_blank_err	secret0	38	1			T21	1		T8	1		T10	1
write_blank_err	hw_cfg1	61	1			T17	1		T21	2		T10	1
write_blank_err	hw_cfg0	20	1			T20	2		T175	1		T269	1
write_blank_err	rot_creator_auth_state	107	1			T21	2		T125	15		T329	4
write_blank_err	rot_creator_auth_codesign	36	1			T21	1		T8	5		T328	2
write_blank_err	owner_sw_cfg	32	1			T21	4		T328	1		T125	2
write_blank_err	creator_sw_cfg	15	1			T21	4		T8	2		T321	1
write_blank_err	vendor_test	13	1			T330	1		T269	1		T183	1
ecc_uncorr_err	secret2	4591	1			T8	464		T171	9		T241	201
ecc_uncorr_err	secret1	7561	1			T108	280		T109	48		T163	268
ecc_uncorr_err	secret0	11534	1			T109	44		T162	39		T8	232
ecc_uncorr_err	hw_cfg1	16565	1			T4	130		T17	457		T21	528
ecc_uncorr_err	hw_cfg0	6428	1			T109	45		T20	133		T164	98
ecc_uncorr_err	rot_creator_auth_state	3044	1			T164	148		T214	58		T158	45
ecc_uncorr_err	rot_creator_auth_codesign	1523	1			T4	62		T109	42		T164	33
ecc_uncorr_err	owner_sw_cfg	2149	1			T4	50		T109	46		T213	14
ecc_uncorr_err	creator_sw_cfg	1725	1			T109	42		T331	38		T171	9
ecc_corr_err	secret2	49	1			T66	4		T164	1		T331	4
ecc_corr_err	secret1	135	1			T66	10		T78	1		T164	1
ecc_corr_err	secret0	177	1			T4	1		T109	3		T66	1
ecc_corr_err	hw_cfg1	329	1			T66	3		T78	2		T68	5
ecc_corr_err	hw_cfg0	284	1			T66	3		T20	1		T68	3
ecc_corr_err	rot_creator_auth_state	127	1			T4	1		T109	1		T70	1
ecc_corr_err	rot_creator_auth_codesign	128	1			T109	1		T66	3		T78	1
ecc_corr_err	owner_sw_cfg	127	1			T4	1		T68	2		T70	6
ecc_corr_err	creator_sw_cfg	145	1			T109	3		T66	2		T78	3
no_err	secret2	4650	1			T1	3		T3	50		T5	10
no_err	secret1	6191	1			T1	1		T3	50		T4	2
no_err	secret0	5875	1			T1	6		T3	35		T4	1
no_err	hw_cfg1	8512	1			T1	4		T3	66		T4	1
no_err	hw_cfg0	10032	1			T1	5		T3	72		T4	2
no_err	rot_creator_auth_state	7337	1			T1	4		T3	64		T4	2
no_err	rot_creator_auth_codesign	6927	1			T1	4		T3	68		T5	11
no_err	owner_sw_cfg	7649	1			T1	14		T3	75		T4	1
no_err	creator_sw_cfg	6433	1			T1	9		T3	89		T4	4
no_err	vendor_test	8627	1			T1	11		T3	118		T4	12

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded