Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	43543	1			T4	23		T9	21		T10	21
access_err	51972	1			T2	49		T4	1332		T9	3
write_blank_err	434	1			T4	12		T8	1		T14	2
ecc_uncorr_err	60616	1			T4	1380		T9	374		T8	216
ecc_corr_err	1256	1			T4	3		T9	14		T93	3
no_err	74901	1			T2	74		T3	9		T4	1429

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	637	1			T4	5		T8	2		T14	3
secret2	21385	1			T2	13		T3	1		T4	322
secret1	25846	1			T2	16		T3	2		T4	244
secret0	30970	1			T2	9		T4	699		T9	28
hw_cfg1	34018	1			T2	8		T3	3		T4	541
hw_cfg0	25318	1			T2	12		T3	1		T4	926
rot_creator_auth_state	15191	1			T2	11		T4	290		T9	84
rot_creator_auth_codesign	16833	1			T2	14		T4	304		T9	2
owner_sw_cfg	17622	1			T2	10		T4	294		T9	92
creator_sw_cfg	17565	1			T2	12		T4	254		T9	49
vendor_test	27337	1			T2	18		T3	2		T4	300

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2790	1			T4	23		T10	21		T222	34
fsm_err	secret1	4466	1			T130	170		T192	7		T305	28
fsm_err	secret0	3466	1			T9	21		T118	428		T306	159
fsm_err	hw_cfg1	5810	1			T149	19		T240	209		T307	5
fsm_err	hw_cfg0	5507	1			T204	338		T135	207		T136	235
fsm_err	rot_creator_auth_state	1455	1			T148	48		T155	56		T308	285
fsm_err	rot_creator_auth_codesign	1386	1			T309	71		T150	22		T164	165
fsm_err	owner_sw_cfg	3331	1			T61	321		T310	107		T311	12
fsm_err	creator_sw_cfg	2828	1			T150	17		T151	57		T152	12
fsm_err	vendor_test	12504	1			T93	27		T70	175		T155	65
access_err	life_cycle	637	1			T4	5		T8	2		T14	3
access_err	secret2	8967	1			T2	13		T4	243		T9	1
access_err	secret1	5948	1			T4	140		T11	16		T24	44
access_err	secret0	4439	1			T2	3		T4	116		T9	1
access_err	hw_cfg1	1153	1			T2	1		T4	23		T9	1
access_err	hw_cfg0	2010	1			T4	52		T11	12		T24	12
access_err	rot_creator_auth_state	4461	1			T2	3		T4	89		T11	2
access_err	rot_creator_auth_codesign	6535	1			T2	1		T4	194		T11	33
access_err	owner_sw_cfg	5380	1			T2	9		T4	167		T11	20
access_err	creator_sw_cfg	6380	1			T2	8		T4	138		T11	10
access_err	vendor_test	6062	1			T2	11		T4	165		T11	8
write_blank_err	secret2	15	1			T15	1		T162	1		T312	1
write_blank_err	secret1	19	1			T8	1		T66	1		T12	1
write_blank_err	secret0	43	1			T4	1		T61	1		T12	1
write_blank_err	hw_cfg1	68	1			T4	2		T14	1		T154	1
write_blank_err	hw_cfg0	24	1			T4	1		T156	1		T313	1
write_blank_err	rot_creator_auth_state	139	1			T4	6		T14	1		T156	1
write_blank_err	rot_creator_auth_codesign	66	1			T4	1		T23	1		T300	3
write_blank_err	owner_sw_cfg	16	1			T314	1		T315	1		T316	1
write_blank_err	creator_sw_cfg	21	1			T156	1		T15	1		T23	1
write_blank_err	vendor_test	23	1			T4	1		T12	1		T15	1
ecc_uncorr_err	secret2	4782	1			T9	37		T15	662		T162	164
ecc_uncorr_err	secret1	8512	1			T9	75		T8	216		T66	203
ecc_uncorr_err	secret0	16312	1			T4	428		T93	22		T61	560
ecc_uncorr_err	hw_cfg1	18163	1			T4	311		T9	48		T14	422
ecc_uncorr_err	hw_cfg0	7401	1			T4	641		T156	667		T313	431
ecc_uncorr_err	rot_creator_auth_state	1845	1			T9	84		T93	60		T317	43
ecc_uncorr_err	rot_creator_auth_codesign	1361	1			T93	30		T318	202		T319	89
ecc_uncorr_err	owner_sw_cfg	863	1			T9	88		T151	98		T317	53
ecc_uncorr_err	creator_sw_cfg	1377	1			T9	42		T155	64		T150	24
ecc_corr_err	secret2	88	1			T9	1		T150	1		T52	5
ecc_corr_err	secret1	108	1			T9	1		T155	1		T125	2
ecc_corr_err	secret0	157	1			T9	2		T93	1		T103	9
ecc_corr_err	hw_cfg1	248	1			T4	3		T9	6		T70	3
ecc_corr_err	hw_cfg0	210	1			T9	1		T125	1		T103	9
ecc_corr_err	rot_creator_auth_state	130	1			T93	1		T103	4		T162	1
ecc_corr_err	rot_creator_auth_codesign	109	1			T62	2		T31	3		T25	9
ecc_corr_err	owner_sw_cfg	102	1			T9	2		T93	1		T103	9
ecc_corr_err	creator_sw_cfg	104	1			T9	1		T103	4		T25	4
no_err	secret2	4743	1			T3	1		T4	56		T9	3
no_err	secret1	6793	1			T2	16		T3	2		T4	104
no_err	secret0	6553	1			T2	6		T4	154		T9	4
no_err	hw_cfg1	8576	1			T2	7		T3	3		T4	202
no_err	hw_cfg0	10166	1			T2	12		T3	1		T4	232
no_err	rot_creator_auth_state	7161	1			T2	8		T4	195		T11	23
no_err	rot_creator_auth_codesign	7376	1			T2	13		T4	109		T9	2
no_err	owner_sw_cfg	7930	1			T2	1		T4	127		T9	2
no_err	creator_sw_cfg	6855	1			T2	4		T4	116		T9	6
no_err	vendor_test	8748	1			T2	7		T3	2		T4	134

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded