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LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR |
LINE 118
EXPRESSION (req_i[4] & gen_normal_case.prio_mask_q[4])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR |
LINE 118
EXPRESSION (req_i[5] & gen_normal_case.prio_mask_q[5])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[6] & gen_normal_case.prio_mask_q[6])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[7] & gen_normal_case.prio_mask_q[7])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[8] & gen_normal_case.prio_mask_q[8])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[9] & gen_normal_case.prio_mask_q[9])
----1--- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T9,T11 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[10] & gen_normal_case.prio_mask_q[10])
----1---- ---------------2---------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR |
LINE 118
EXPRESSION (req_i[11] & gen_normal_case.prio_mask_q[11])
----1---- ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T9 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 118
EXPRESSION (req_i[12] & gen_normal_case.prio_mask_q[12])
----1---- ---------------2---------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR |
LINE 118
EXPRESSION (req_i[13] & gen_normal_case.prio_mask_q[13])
----1---- ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[5] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[6] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[7] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[8] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[9] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[10] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ready_i)
----1---- -----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[11] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] & ready_i)
----1---- -----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[12] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ready_i)
----1---- -----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | 1 | Unreachable | |
LINE 126
EXPRESSION (req_i[13] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ready_i)
----1---- -----------------------------------2---------------------------------- ---3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | 1 | Unreachable | |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[4])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[5])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
vcs_gen_start:level=4,offset=5:vcs_gen_end:VC_COV_UNR |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[6])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[7])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[8])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[9])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T3,T4 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[10])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T2,T3,T4 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ((~ready_i)))
-----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[11])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T4,T5 |
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] & ((~ready_i)))
-----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[12])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T2,T4,T5 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ((~ready_i)))
-----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Excluded | |
vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[13])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i))))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Excluded | |
vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i)))
-----------------------------------1---------------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
| 0 | 1 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T66 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T66 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
| 0 | 1 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1]))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T9,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1]))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1]))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T4,T5 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Unreachable | |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1]))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Excluded | |
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Excluded | |
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1]))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Excluded | |
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Excluded | |
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1]))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Excluded | |
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C1]))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T198,T243,T171 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C1])
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C1]))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C1])
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1]))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Excluded | |
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]))
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Excluded | |
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C1]))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Unreachable | |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C1])
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Unreachable | |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Excluded | |
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Excluded | |
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Unreachable | |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Unreachable | |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T2,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Unreachable | |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
| 1 | 1 | Excluded | |
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T66 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T4,T5 |