Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	41161	1			T10	98		T11	237		T76	35
access_err	50337	1			T4	38		T10	24		T5	37
write_blank_err	327	1			T8	5		T9	3		T98	1
ecc_uncorr_err	53413	1			T8	951		T9	554		T137	81
ecc_corr_err	1159	1			T9	1		T137	5		T58	23
no_err	69388	1			T4	82		T10	29		T5	41

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	636	1			T8	24		T9	8		T15	11
secret2	19910	1			T4	13		T10	8		T5	3
secret1	24711	1			T4	12		T10	2		T5	11
secret0	26861	1			T4	11		T10	5		T5	7
hw_cfg1	28305	1			T4	10		T10	5		T5	6
hw_cfg0	20323	1			T4	18		T10	98		T5	6
rot_creator_auth_state	18458	1			T4	9		T10	6		T5	4
rot_creator_auth_codesign	17505	1			T4	13		T10	15		T5	5
owner_sw_cfg	17467	1			T4	7		T10	5		T5	7
creator_sw_cfg	16775	1			T4	9		T10	2		T5	12
vendor_test	24834	1			T4	18		T10	5		T5	17

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3176	1			T16	38		T314	322		T156	61
fsm_err	secret1	5336	1			T143	404		T146	582		T315	360
fsm_err	secret0	3903	1			T316	152		T125	40		T317	96
fsm_err	hw_cfg1	1451	1			T98	419		T15	202		T243	127
fsm_err	hw_cfg0	4567	1			T10	98		T8	67		T142	7
fsm_err	rot_creator_auth_state	2145	1			T96	177		T318	175		T167	57
fsm_err	rot_creator_auth_codesign	3520	1			T15	238		T167	121		T319	138
fsm_err	owner_sw_cfg	2795	1			T166	389		T137	21		T16	8
fsm_err	creator_sw_cfg	3272	1			T11	237		T98	521		T320	1
fsm_err	vendor_test	10996	1			T76	35		T110	342		T72	119
access_err	life_cycle	636	1			T8	24		T9	8		T15	11
access_err	secret2	8395	1			T4	6		T10	8		T5	2
access_err	secret1	5862	1			T4	10		T5	10		T6	14
access_err	secret0	4533	1			T4	3		T10	3		T5	6
access_err	hw_cfg1	1213	1			T4	4		T5	4		T6	7
access_err	hw_cfg0	2187	1			T4	3		T5	2		T6	4
access_err	rot_creator_auth_state	4159	1			T10	3		T5	1		T6	3
access_err	rot_creator_auth_codesign	6107	1			T4	2		T10	6		T6	8
access_err	owner_sw_cfg	5440	1			T4	3		T5	1		T6	2
access_err	creator_sw_cfg	6062	1			T4	3		T10	1		T5	6
access_err	vendor_test	5743	1			T4	4		T10	3		T5	5
write_blank_err	secret2	13	1			T120	1		T18	1		T321	1
write_blank_err	secret1	19	1			T143	2		T322	1		T321	1
write_blank_err	secret0	35	1			T8	2		T160	2		T162	1
write_blank_err	hw_cfg1	65	1			T98	1		T15	1		T160	2
write_blank_err	hw_cfg0	12	1			T9	2		T323	1		T321	1
write_blank_err	rot_creator_auth_state	84	1			T8	1		T15	2		T143	1
write_blank_err	rot_creator_auth_codesign	63	1			T8	1		T143	2		T17	2
write_blank_err	owner_sw_cfg	8	1			T128	1		T198	1		T324	1
write_blank_err	creator_sw_cfg	9	1			T129	1		T323	2		T270	1
write_blank_err	vendor_test	19	1			T8	1		T9	1		T15	2
ecc_uncorr_err	secret2	3894	1			T120	173		T156	59		T18	51
ecc_uncorr_err	secret1	7462	1			T143	1207		T322	330		T175	62
ecc_uncorr_err	secret0	12160	1			T8	951		T162	108		T167	57
ecc_uncorr_err	hw_cfg1	17234	1			T137	23		T98	735		T15	255
ecc_uncorr_err	hw_cfg0	3899	1			T9	554		T156	106		T175	68
ecc_uncorr_err	rot_creator_auth_state	5088	1			T137	27		T173	169		T156	58
ecc_uncorr_err	rot_creator_auth_codesign	1097	1			T173	114		T325	10		T199	54
ecc_uncorr_err	owner_sw_cfg	1554	1			T137	31		T167	52		T173	57
ecc_uncorr_err	creator_sw_cfg	1025	1			T167	128		T156	118		T326	80
ecc_corr_err	secret2	66	1			T58	1		T173	2		T156	1
ecc_corr_err	secret1	124	1			T58	2		T72	2		T167	2
ecc_corr_err	secret0	147	1			T137	3		T58	1		T160	3
ecc_corr_err	hw_cfg1	228	1			T137	1		T58	4		T160	2
ecc_corr_err	hw_cfg0	199	1			T9	1		T137	1		T58	5
ecc_corr_err	rot_creator_auth_state	86	1			T58	3		T167	2		T173	1
ecc_corr_err	rot_creator_auth_codesign	109	1			T72	2		T73	1		T175	1
ecc_corr_err	owner_sw_cfg	88	1			T156	1		T175	2		T113	1
ecc_corr_err	creator_sw_cfg	112	1			T58	7		T167	1		T173	4
no_err	secret2	4366	1			T4	7		T5	1		T6	4
no_err	secret1	5908	1			T4	2		T10	2		T5	1
no_err	secret0	6083	1			T4	8		T10	2		T5	1
no_err	hw_cfg1	8114	1			T4	6		T10	5		T5	2
no_err	hw_cfg0	9459	1			T4	15		T5	4		T6	13
no_err	rot_creator_auth_state	6896	1			T4	9		T10	3		T5	3
no_err	rot_creator_auth_codesign	6609	1			T4	11		T10	9		T5	5
no_err	owner_sw_cfg	7582	1			T4	4		T10	5		T5	6
no_err	creator_sw_cfg	6295	1			T4	6		T10	1		T5	6
no_err	vendor_test	8076	1			T4	14		T10	2		T5	12

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded