Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	42054	1			T12	318		T71	60		T117	150
access_err	54880	1			T5	57		T6	17		T11	37
write_blank_err	343	1			T8	2		T146	1		T14	1
ecc_uncorr_err	54614	1			T71	227		T8	202		T146	623
ecc_corr_err	1452	1			T71	9		T47	18		T40	71
no_err	74968	1			T3	3		T5	93		T6	122

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	584	1			T8	4		T14	6		T13	9
secret2	19553	1			T5	17		T6	15		T11	9
secret1	21898	1			T3	1		T5	16		T6	11
secret0	28207	1			T5	16		T6	22		T11	5
hw_cfg1	31670	1			T5	6		T6	10		T11	11
hw_cfg0	19853	1			T5	11		T6	18		T11	8
rot_creator_auth_state	18296	1			T5	18		T6	15		T11	10
rot_creator_auth_codesign	18264	1			T3	2		T5	13		T6	11
owner_sw_cfg	18850	1			T5	21		T6	11		T11	14
creator_sw_cfg	21593	1			T5	11		T6	12		T11	14
vendor_test	29543	1			T5	21		T6	14		T11	8

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2190	1			T250	81		T318	44		T209	135
fsm_err	secret1	2695	1			T329	156		T325	19		T210	142
fsm_err	secret0	2521	1			T117	150		T330	79		T331	16
fsm_err	hw_cfg1	2639	1			T70	189		T108	28		T158	320
fsm_err	hw_cfg0	3346	1			T118	39		T119	108		T112	409
fsm_err	rot_creator_auth_state	2459	1			T12	318		T145	156		T232	69
fsm_err	rot_creator_auth_codesign	2365	1			T320	492		T178	10		T179	21
fsm_err	owner_sw_cfg	3163	1			T71	60		T108	291		T143	71
fsm_err	creator_sw_cfg	6208	1			T116	96		T233	243		T243	392
fsm_err	vendor_test	14468	1			T47	116		T110	257		T40	116
access_err	life_cycle	584	1			T8	4		T14	6		T13	9
access_err	secret2	8988	1			T5	3		T6	9		T11	7
access_err	secret1	6219	1			T11	3		T26	2		T40	38
access_err	secret0	4841	1			T5	7		T11	2		T7	5
access_err	hw_cfg1	1264	1			T5	2		T6	1		T11	5
access_err	hw_cfg0	2488	1			T11	2		T26	1		T27	2
access_err	rot_creator_auth_state	4539	1			T5	3		T6	1		T11	1
access_err	rot_creator_auth_codesign	6892	1			T5	12		T11	2		T7	16
access_err	owner_sw_cfg	5970	1			T5	11		T6	1		T11	6
access_err	creator_sw_cfg	6770	1			T5	4		T6	4		T11	5
access_err	vendor_test	6325	1			T5	15		T6	1		T11	4
write_blank_err	secret2	10	1			T38	1		T224	1		T198	1
write_blank_err	secret1	15	1			T114	2		T225	1		T332	1
write_blank_err	secret0	36	1			T116	2		T159	1		T126	1
write_blank_err	hw_cfg1	63	1			T8	1		T146	1		T225	1
write_blank_err	hw_cfg0	10	1			T13	1		T114	1		T333	1
write_blank_err	rot_creator_auth_state	115	1			T8	1		T14	1		T114	11
write_blank_err	rot_creator_auth_codesign	30	1			T13	1		T334	3		T335	1
write_blank_err	owner_sw_cfg	19	1			T13	2		T126	5		T336	1
write_blank_err	creator_sw_cfg	16	1			T114	1		T116	2		T224	4
write_blank_err	vendor_test	29	1			T116	1		T224	1		T334	1
ecc_uncorr_err	secret2	3544	1			T38	62		T224	500		T144	15
ecc_uncorr_err	secret1	6177	1			T114	539		T225	581		T337	13
ecc_uncorr_err	secret0	14129	1			T71	69		T116	593		T337	11
ecc_uncorr_err	hw_cfg1	18523	1			T8	202		T146	623		T319	44
ecc_uncorr_err	hw_cfg0	3784	1			T71	58		T13	165		T114	366
ecc_uncorr_err	rot_creator_auth_state	3460	1			T14	331		T337	6		T338	62
ecc_uncorr_err	rot_creator_auth_codesign	1386	1			T71	100		T337	9		T143	138
ecc_uncorr_err	owner_sw_cfg	1836	1			T176	125		T339	65		T177	46
ecc_uncorr_err	creator_sw_cfg	1775	1			T319	13		T143	70		T160	151
ecc_corr_err	secret2	101	1			T40	7		T106	2		T337	4
ecc_corr_err	secret1	129	1			T71	2		T47	5		T106	2
ecc_corr_err	secret0	145	1			T47	2		T40	6		T106	5
ecc_corr_err	hw_cfg1	278	1			T71	1		T47	2		T40	24
ecc_corr_err	hw_cfg0	252	1			T47	4		T40	7		T106	3
ecc_corr_err	rot_creator_auth_state	155	1			T47	2		T40	3		T106	4
ecc_corr_err	rot_creator_auth_codesign	140	1			T71	4		T40	3		T106	3
ecc_corr_err	owner_sw_cfg	118	1			T71	1		T47	1		T40	4
ecc_corr_err	creator_sw_cfg	134	1			T71	1		T47	2		T40	17
no_err	secret2	4720	1			T5	14		T6	6		T11	2
no_err	secret1	6663	1			T3	1		T5	16		T6	11
no_err	secret0	6535	1			T5	9		T6	22		T11	3
no_err	hw_cfg1	8903	1			T5	4		T6	9		T11	6
no_err	hw_cfg0	9973	1			T5	11		T6	18		T11	6
no_err	rot_creator_auth_state	7568	1			T5	15		T6	14		T11	9
no_err	rot_creator_auth_codesign	7451	1			T3	2		T5	1		T6	11
no_err	owner_sw_cfg	7744	1			T5	10		T6	10		T11	8
no_err	creator_sw_cfg	6690	1			T5	7		T6	8		T11	9
no_err	vendor_test	8721	1			T5	6		T6	13		T11	4

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded