Summary for Variable keymgr_rd_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for keymgr_rd_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3753 |
1 |
|
|
T4 |
1 |
|
T5 |
4 |
|
T6 |
3 |
auto[1] |
2442 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T5 |
1 |
Summary for Variable secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret2_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4234 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
1 |
auto[1] |
1961 |
1 |
|
|
T5 |
2 |
|
T11 |
5 |
|
T47 |
4 |
Summary for Cross keymgr_output_conditions
Samples crossed: keymgr_rd_en secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for keymgr_output_conditions
Bins
keymgr_rd_en | secret2_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
2542 |
1 |
|
|
T4 |
1 |
|
T5 |
2 |
|
T6 |
3 |
auto[0] |
auto[1] |
1211 |
1 |
|
|
T5 |
2 |
|
T11 |
4 |
|
T47 |
3 |
auto[1] |
auto[0] |
1692 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T5 |
1 |
auto[1] |
auto[1] |
750 |
1 |
|
|
T11 |
1 |
|
T47 |
1 |
|
T27 |
7 |