Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv


Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
keymgr_rd_en 2 0 2 100.00 100 1 1 2
secret2_lock 2 0 2 100.00 100 1 1 2


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
keymgr_output_conditions 4 0 4 100.00 100 1 1 0


Summary for Variable keymgr_rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for keymgr_rd_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3549 1 T1 1 T2 23 T3 2
auto[1] 2448 1 T2 7 T3 4 T4 6


Summary for Variable secret2_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret2_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4110 1 T1 1 T2 24 T3 4
auto[1] 1887 1 T2 6 T3 2 T5 17


Summary for Cross keymgr_output_conditions

Samples crossed: keymgr_rd_en secret2_lock
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for keymgr_output_conditions

Bins
keymgr_rd_ensecret2_lockCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2416 1 T1 1 T2 17 T3 2
auto[0] auto[1] 1133 1 T2 6 T5 11 T38 4
auto[1] auto[0] 1694 1 T2 7 T3 2 T4 6
auto[1] auto[1] 754 1 T3 2 T5 6 T96 3

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