Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	46116	1			T4	104		T13	35		T100	15
access_err	50472	1			T2	171		T3	4		T4	10
write_blank_err	380	1			T5	6		T6	11		T142	1
ecc_uncorr_err	55528	1			T1	109		T4	547		T11	600
ecc_corr_err	1439	1			T1	8		T4	16		T11	7
no_err	72233	1			T1	32		T2	157		T3	37

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	700	1			T5	3		T6	20		T16	2
secret2	22179	1			T1	2		T2	24		T3	4
secret1	25471	1			T1	38		T2	46		T3	1
secret0	30622	1			T1	16		T2	20		T3	5
hw_cfg1	26553	1			T2	44		T4	2		T9	4
hw_cfg0	24226	1			T1	18		T2	21		T3	7
rot_creator_auth_state	17885	1			T1	15		T2	35		T3	4
rot_creator_auth_codesign	17915	1			T1	6		T2	43		T3	6
owner_sw_cfg	18269	1			T1	33		T2	23		T3	1
creator_sw_cfg	16210	1			T1	4		T2	42		T3	8
vendor_test	26138	1			T1	17		T2	30		T3	5

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5150	1			T153	490		T164	626		T182	326
fsm_err	secret1	2784	1			T13	35		T145	412		T327	88
fsm_err	secret0	4107	1			T151	247		T19	168		T248	272
fsm_err	hw_cfg1	2400	1			T6	139		T110	426		T148	143
fsm_err	hw_cfg0	4952	1			T6	263		T150	179		T152	51
fsm_err	rot_creator_auth_state	4583	1			T221	32		T21	44		T328	527
fsm_err	rot_creator_auth_codesign	3565	1			T4	35		T224	52		T179	12
fsm_err	owner_sw_cfg	3992	1			T100	15		T172	35		T246	12
fsm_err	creator_sw_cfg	2647	1			T247	43		T179	12		T249	314
fsm_err	vendor_test	11936	1			T4	69		T72	143		T77	148
access_err	life_cycle	700	1			T5	3		T6	20		T16	2
access_err	secret2	8538	1			T2	14		T3	4		T4	3
access_err	secret1	5440	1			T2	28		T9	4		T6	78
access_err	secret0	4593	1			T2	11		T9	1		T32	4
access_err	hw_cfg1	1113	1			T2	2		T5	1		T32	3
access_err	hw_cfg0	1992	1			T2	16		T32	1		T6	14
access_err	rot_creator_auth_state	4496	1			T2	23		T4	1		T6	41
access_err	rot_creator_auth_codesign	6171	1			T2	35		T9	5		T5	2
access_err	owner_sw_cfg	5525	1			T2	5		T4	2		T9	3
access_err	creator_sw_cfg	6069	1			T2	27		T4	2		T9	2
access_err	vendor_test	5835	1			T2	10		T4	2		T9	2
write_blank_err	secret2	11	1			T134	1		T329	1		T143	1
write_blank_err	secret1	26	1			T171	1		T110	1		T326	1
write_blank_err	secret0	41	1			T6	4		T110	1		T330	1
write_blank_err	hw_cfg1	62	1			T6	1		T142	1		T16	1
write_blank_err	hw_cfg0	16	1			T5	1		T209	1		T134	1
write_blank_err	rot_creator_auth_state	108	1			T5	3		T6	3		T110	2
write_blank_err	rot_creator_auth_codesign	48	1			T5	2		T6	2		T326	2
write_blank_err	owner_sw_cfg	22	1			T160	1		T331	1		T31	2
write_blank_err	creator_sw_cfg	19	1			T331	1		T31	3		T68	1
write_blank_err	vendor_test	27	1			T6	1		T110	1		T134	1
ecc_uncorr_err	secret2	3877	1			T1	2		T134	292		T179	9
ecc_uncorr_err	secret1	10544	1			T1	33		T4	72		T11	197
ecc_uncorr_err	secret0	15543	1			T1	12		T11	135		T6	1348
ecc_uncorr_err	hw_cfg1	14220	1			T142	168		T172	70		T16	616
ecc_uncorr_err	hw_cfg0	7131	1			T1	16		T4	199		T11	138
ecc_uncorr_err	rot_creator_auth_state	1310	1			T1	14		T4	70		T170	49
ecc_uncorr_err	rot_creator_auth_codesign	945	1			T4	69		T11	65		T221	47
ecc_uncorr_err	owner_sw_cfg	1171	1			T1	32		T4	65		T170	34
ecc_uncorr_err	creator_sw_cfg	787	1			T4	72		T11	65		T172	33
ecc_corr_err	secret2	90	1			T221	1		T43	2		T225	1
ecc_corr_err	secret1	116	1			T4	1		T77	2		T172	2
ecc_corr_err	secret0	153	1			T1	2		T4	2		T11	2
ecc_corr_err	hw_cfg1	273	1			T4	1		T6	3		T72	17
ecc_corr_err	hw_cfg0	254	1			T1	2		T4	7		T11	2
ecc_corr_err	rot_creator_auth_state	115	1			T11	2		T72	7		T77	2
ecc_corr_err	rot_creator_auth_codesign	164	1			T1	3		T4	3		T72	7
ecc_corr_err	owner_sw_cfg	122	1			T72	2		T77	5		T170	1
ecc_corr_err	creator_sw_cfg	152	1			T1	1		T4	2		T11	1
no_err	secret2	4513	1			T2	10		T9	2		T13	1
no_err	secret1	6561	1			T1	5		T2	18		T3	1
no_err	secret0	6185	1			T1	2		T2	9		T3	5
no_err	hw_cfg1	8485	1			T2	42		T4	1		T9	4
no_err	hw_cfg0	9881	1			T2	5		T3	7		T4	3
no_err	rot_creator_auth_state	7273	1			T1	1		T2	12		T3	4
no_err	rot_creator_auth_codesign	7022	1			T1	3		T2	8		T3	6
no_err	owner_sw_cfg	7437	1			T1	1		T2	18		T3	1
no_err	creator_sw_cfg	6536	1			T1	3		T2	15		T3	8
no_err	vendor_test	8340	1			T1	17		T2	20		T3	5

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded