SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 43569 | 1 | T12 | 464 | T100 | 91 | T128 | 144 | ||||
access_err | 52080 | 1 | T6 | 2 | T7 | 21 | T12 | 2 | ||||
write_blank_err | 310 | 1 | T8 | 1 | T9 | 1 | T10 | 4 | ||||
ecc_uncorr_err | 52103 | 1 | T116 | 471 | T8 | 371 | T146 | 341 | ||||
ecc_corr_err | 1350 | 1 | T116 | 2 | T106 | 4 | T96 | 39 | ||||
no_err | 73274 | 1 | T3 | 71 | T6 | 12 | T7 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 543 | 1 | T8 | 5 | T9 | 3 | T10 | 6 | ||||
secret2 | 20396 | 1 | T3 | 8 | T6 | 2 | T7 | 6 | ||||
secret1 | 26359 | 1 | T3 | 6 | T6 | 3 | T7 | 4 | ||||
secret0 | 27804 | 1 | T3 | 4 | T7 | 8 | T12 | 8 | ||||
hw_cfg1 | 29146 | 1 | T3 | 7 | T7 | 6 | T13 | 3 | ||||
hw_cfg0 | 18663 | 1 | T3 | 5 | T7 | 1 | T12 | 5 | ||||
rot_creator_auth_state | 20115 | 1 | T3 | 17 | T12 | 4 | T13 | 1 | ||||
rot_creator_auth_codesign | 19228 | 1 | T3 | 9 | T6 | 2 | T12 | 4 | ||||
owner_sw_cfg | 16227 | 1 | T3 | 4 | T6 | 2 | T7 | 3 | ||||
creator_sw_cfg | 17385 | 1 | T3 | 6 | T7 | 3 | T12 | 465 | ||||
vendor_test | 26820 | 1 | T3 | 5 | T6 | 5 | T7 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 4785 | 1 | T108 | 177 | T373 | 54 | T285 | 232 | ||||
fsm_err | secret1 | 4677 | 1 | T15 | 31 | T156 | 15 | T284 | 117 | ||||
fsm_err | secret0 | 3521 | 1 | T128 | 144 | T168 | 65 | T374 | 399 | ||||
fsm_err | hw_cfg1 | 2510 | 1 | T286 | 104 | T191 | 39 | T287 | 179 | ||||
fsm_err | hw_cfg0 | 3425 | 1 | T155 | 162 | T375 | 210 | T161 | 8 | ||||
fsm_err | rot_creator_auth_state | 3066 | 1 | T196 | 115 | T191 | 41 | T376 | 14 | ||||
fsm_err | rot_creator_auth_codesign | 4074 | 1 | T190 | 47 | T318 | 207 | T197 | 61 | ||||
fsm_err | owner_sw_cfg | 1815 | 1 | T192 | 35 | T222 | 12 | T251 | 20 | ||||
fsm_err | creator_sw_cfg | 3265 | 1 | T12 | 464 | T280 | 64 | T186 | 34 | ||||
fsm_err | vendor_test | 12431 | 1 | T100 | 91 | T97 | 73 | T106 | 7 | ||||
access_err | life_cycle | 543 | 1 | T8 | 5 | T9 | 3 | T10 | 6 | ||||
access_err | secret2 | 8656 | 1 | T6 | 2 | T7 | 4 | T129 | 9 | ||||
access_err | secret1 | 5773 | 1 | T7 | 4 | T18 | 12 | T92 | 4 | ||||
access_err | secret0 | 4865 | 1 | T7 | 7 | T12 | 1 | T129 | 3 | ||||
access_err | hw_cfg1 | 1215 | 1 | T7 | 4 | T129 | 1 | T18 | 6 | ||||
access_err | hw_cfg0 | 2145 | 1 | T18 | 4 | T19 | 1 | T101 | 12 | ||||
access_err | rot_creator_auth_state | 4516 | 1 | T12 | 1 | T129 | 3 | T18 | 14 | ||||
access_err | rot_creator_auth_codesign | 6683 | 1 | T129 | 9 | T18 | 35 | T101 | 25 | ||||
access_err | owner_sw_cfg | 5552 | 1 | T7 | 2 | T17 | 2 | T129 | 15 | ||||
access_err | creator_sw_cfg | 6285 | 1 | T129 | 6 | T18 | 14 | T111 | 2 | ||||
access_err | vendor_test | 5847 | 1 | T17 | 2 | T129 | 7 | T18 | 14 | ||||
write_blank_err | secret2 | 5 | 1 | T8 | 1 | T377 | 1 | T378 | 1 | ||||
write_blank_err | secret1 | 22 | 1 | T172 | 1 | T262 | 1 | T379 | 1 | ||||
write_blank_err | secret0 | 38 | 1 | T175 | 1 | T380 | 1 | T14 | 1 | ||||
write_blank_err | hw_cfg1 | 61 | 1 | T9 | 1 | T172 | 1 | T173 | 1 | ||||
write_blank_err | hw_cfg0 | 7 | 1 | T381 | 1 | T369 | 1 | T382 | 1 | ||||
write_blank_err | rot_creator_auth_state | 102 | 1 | T10 | 4 | T172 | 2 | T14 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 30 | 1 | T16 | 1 | T263 | 2 | T147 | 7 | ||||
write_blank_err | owner_sw_cfg | 9 | 1 | T16 | 2 | T263 | 1 | T382 | 1 | ||||
write_blank_err | creator_sw_cfg | 14 | 1 | T147 | 2 | T88 | 1 | T383 | 2 | ||||
write_blank_err | vendor_test | 22 | 1 | T88 | 1 | T383 | 1 | T378 | 1 | ||||
ecc_uncorr_err | secret2 | 2128 | 1 | T8 | 371 | T190 | 54 | T185 | 102 | ||||
ecc_uncorr_err | secret1 | 9212 | 1 | T146 | 69 | T168 | 196 | T174 | 22 | ||||
ecc_uncorr_err | secret0 | 13138 | 1 | T168 | 66 | T174 | 15 | T175 | 153 | ||||
ecc_uncorr_err | hw_cfg1 | 16545 | 1 | T9 | 602 | T172 | 439 | T173 | 468 | ||||
ecc_uncorr_err | hw_cfg0 | 2983 | 1 | T116 | 130 | T146 | 49 | T168 | 66 | ||||
ecc_uncorr_err | rot_creator_auth_state | 5000 | 1 | T116 | 199 | T10 | 445 | T168 | 62 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 1057 | 1 | T116 | 73 | T146 | 147 | T185 | 61 | ||||
ecc_uncorr_err | owner_sw_cfg | 973 | 1 | T146 | 76 | T168 | 72 | T190 | 44 | ||||
ecc_uncorr_err | creator_sw_cfg | 1067 | 1 | T116 | 69 | T190 | 56 | T185 | 66 | ||||
ecc_corr_err | secret2 | 77 | 1 | T116 | 2 | T76 | 1 | T185 | 1 | ||||
ecc_corr_err | secret1 | 132 | 1 | T106 | 1 | T96 | 5 | T172 | 1 | ||||
ecc_corr_err | secret0 | 126 | 1 | T96 | 16 | T168 | 1 | T56 | 4 | ||||
ecc_corr_err | hw_cfg1 | 259 | 1 | T106 | 3 | T96 | 2 | T55 | 8 | ||||
ecc_corr_err | hw_cfg0 | 246 | 1 | T96 | 10 | T55 | 4 | T56 | 1 | ||||
ecc_corr_err | rot_creator_auth_state | 125 | 1 | T168 | 1 | T174 | 2 | T76 | 7 | ||||
ecc_corr_err | rot_creator_auth_codesign | 135 | 1 | T96 | 1 | T55 | 2 | T146 | 1 | ||||
ecc_corr_err | owner_sw_cfg | 129 | 1 | T96 | 3 | T55 | 3 | T146 | 2 | ||||
ecc_corr_err | creator_sw_cfg | 121 | 1 | T96 | 2 | T55 | 5 | T146 | 3 | ||||
no_err | secret2 | 4745 | 1 | T3 | 8 | T7 | 2 | T12 | 5 | ||||
no_err | secret1 | 6543 | 1 | T3 | 6 | T6 | 3 | T12 | 9 | ||||
no_err | secret0 | 6116 | 1 | T3 | 4 | T7 | 1 | T12 | 7 | ||||
no_err | hw_cfg1 | 8556 | 1 | T3 | 7 | T7 | 2 | T13 | 3 | ||||
no_err | hw_cfg0 | 9857 | 1 | T3 | 5 | T7 | 1 | T12 | 5 | ||||
no_err | rot_creator_auth_state | 7306 | 1 | T3 | 17 | T12 | 3 | T13 | 1 | ||||
no_err | rot_creator_auth_codesign | 7249 | 1 | T3 | 9 | T6 | 2 | T12 | 4 | ||||
no_err | owner_sw_cfg | 7749 | 1 | T3 | 4 | T6 | 2 | T7 | 1 | ||||
no_err | creator_sw_cfg | 6633 | 1 | T3 | 6 | T7 | 3 | T12 | 1 | ||||
no_err | vendor_test | 8520 | 1 | T3 | 5 | T6 | 5 | T7 | 3 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |