Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	43837	1			T4	65		T94	61		T98	92
access_err	52646	1			T4	2		T7	32		T8	23
write_blank_err	394	1			T9	1		T148	1		T171	1
ecc_uncorr_err	59408	1			T98	178		T9	564		T148	263
ecc_corr_err	1350	1			T94	55		T98	3		T81	29
no_err	73265	1			T2	135		T4	14		T7	32

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	667	1			T9	2		T10	2		T11	4
secret2	23002	1			T2	14		T4	2		T7	6
secret1	25651	1			T2	10		T7	9		T8	16
secret0	29693	1			T2	7		T4	1		T7	8
hw_cfg1	29147	1			T2	12		T4	68		T7	3
hw_cfg0	22447	1			T2	20		T7	6		T8	6
rot_creator_auth_state	17422	1			T2	19		T4	2		T7	3
rot_creator_auth_codesign	17900	1			T2	20		T4	3		T7	12
owner_sw_cfg	18723	1			T2	8		T7	3		T8	5
creator_sw_cfg	17772	1			T2	16		T4	3		T7	5
vendor_test	28476	1			T2	9		T4	2		T7	9

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2458	1			T125	15		T252	256		T357	79
fsm_err	secret1	4749	1			T244	272		T184	55		T358	473
fsm_err	secret0	3775	1			T98	44		T115	57		T168	18
fsm_err	hw_cfg1	4226	1			T4	65		T193	205		T262	310
fsm_err	hw_cfg0	4486	1			T14	35		T219	63		T359	138
fsm_err	rot_creator_auth_state	1098	1			T115	57		T169	24		T360	149
fsm_err	rot_creator_auth_codesign	2521	1			T162	55		T181	35		T163	57
fsm_err	owner_sw_cfg	3750	1			T152	47		T198	265		T183	48
fsm_err	creator_sw_cfg	3124	1			T156	2		T115	61		T361	224
fsm_err	vendor_test	13650	1			T94	61		T98	48		T100	8
access_err	life_cycle	667	1			T9	2		T10	2		T11	4
access_err	secret2	8870	1			T4	2		T7	5		T8	6
access_err	secret1	5676	1			T7	9		T8	9		T94	30
access_err	secret0	4610	1			T7	8		T94	16		T95	5
access_err	hw_cfg1	1183	1			T8	4		T12	2		T95	3
access_err	hw_cfg0	2216	1			T7	1		T8	2		T94	1
access_err	rot_creator_auth_state	4619	1			T7	2		T94	4		T95	4
access_err	rot_creator_auth_codesign	6621	1			T7	6		T94	31		T95	5
access_err	owner_sw_cfg	5601	1			T8	1		T94	25		T95	12
access_err	creator_sw_cfg	6358	1			T8	1		T94	5		T95	6
access_err	vendor_test	6225	1			T7	1		T94	33		T95	2
write_blank_err	secret2	17	1			T171	1		T199	1		T232	1
write_blank_err	secret1	19	1			T9	1		T11	1		T119	1
write_blank_err	secret0	38	1			T15	1		T199	1		T362	1
write_blank_err	hw_cfg1	55	1			T148	1		T10	1		T233	1
write_blank_err	hw_cfg0	15	1			T231	1		T356	1		T350	1
write_blank_err	rot_creator_auth_state	130	1			T11	1		T363	6		T199	1
write_blank_err	rot_creator_auth_codesign	70	1			T197	1		T231	3		T356	2
write_blank_err	owner_sw_cfg	25	1			T364	2		T365	1		T366	8
write_blank_err	creator_sw_cfg	6	1			T367	1		T107	1		T368	2
write_blank_err	vendor_test	19	1			T199	1		T350	1		T90	2
ecc_uncorr_err	secret2	6760	1			T156	6		T171	454		T162	60
ecc_uncorr_err	secret1	8375	1			T9	564		T11	334		T115	55
ecc_uncorr_err	secret0	14798	1			T98	42		T162	25		T15	50
ecc_uncorr_err	hw_cfg1	14865	1			T98	44		T148	263		T156	2
ecc_uncorr_err	hw_cfg0	5978	1			T98	48		T155	95		T156	4
ecc_uncorr_err	rot_creator_auth_state	4250	1			T98	44		T162	37		T115	47
ecc_uncorr_err	rot_creator_auth_codesign	1437	1			T156	4		T115	61		T152	52
ecc_uncorr_err	owner_sw_cfg	1459	1			T155	85		T152	111		T208	55
ecc_uncorr_err	creator_sw_cfg	1486	1			T156	6		T152	59		T208	42
ecc_corr_err	secret2	90	1			T94	14		T82	2		T130	1
ecc_corr_err	secret1	129	1			T94	4		T98	2		T162	1
ecc_corr_err	secret0	141	1			T94	3		T98	1		T81	2
ecc_corr_err	hw_cfg1	241	1			T94	5		T81	6		T71	5
ecc_corr_err	hw_cfg0	197	1			T94	3		T81	2		T71	1
ecc_corr_err	rot_creator_auth_state	105	1			T94	6		T81	2		T71	1
ecc_corr_err	rot_creator_auth_codesign	166	1			T94	9		T81	5		T155	1
ecc_corr_err	owner_sw_cfg	157	1			T94	1		T81	8		T155	1
ecc_corr_err	creator_sw_cfg	124	1			T94	10		T81	4		T156	1
no_err	secret2	4807	1			T2	14		T7	1		T8	1
no_err	secret1	6703	1			T2	10		T8	7		T91	23
no_err	secret0	6331	1			T2	7		T4	1		T8	1
no_err	hw_cfg1	8577	1			T2	12		T4	3		T7	3
no_err	hw_cfg0	9555	1			T2	20		T7	5		T8	4
no_err	rot_creator_auth_state	7220	1			T2	19		T4	2		T7	1
no_err	rot_creator_auth_codesign	7085	1			T2	20		T4	3		T7	6
no_err	owner_sw_cfg	7731	1			T2	8		T7	3		T8	4
no_err	creator_sw_cfg	6674	1			T2	16		T4	3		T7	5
no_err	vendor_test	8582	1			T2	9		T4	2		T7	8

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded