Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
keymgr_rd_en	2	0	2	100.00	100	1	1	2
secret2_lock	2	0	2	100.00	100	1	1	2

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
keymgr_output_conditions	4	0	4	100.00	100	1	1	0

Summary for Variable keymgr_rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for keymgr_rd_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3692

1

T2

4

T3

1

T6

1

auto[1]

2430

1

T4

1

T7

4

T8

2

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Summary for Variable secret2_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret2_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4166

1

T2

3

T3

1

T6

1

auto[1]

1956

1

T2

1

T7

9

T8

4

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Summary for Cross keymgr_output_conditions

Samples crossed: keymgr_rd_en secret2_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for keymgr_output_conditions

Bins

keymgr_rd_en

secret2_lock

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

2495

1

T2

3

T3

1

T6

1

auto[0]

auto[1]

1197

1

T2

1

T7

5

T8

2

auto[1]

auto[0]

1671

1

T4

1

T12

1

T99

1

auto[1]

auto[1]

759

1

T7

4

T8

2

T12

2