Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

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Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
flash_data_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_lc_esc	2	0	2	100.00	100	1	1	0
flash_data_req_during_otbn_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_otp_idle	2	0	2	100.00	100	1	1	2
flash_data_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable flash_data_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9405

1

T3

4

T6

28

T7

6

auto[1]

641

1

T119

5

T123

3

T174

1

---

Summary for Variable flash_data_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for flash_data_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

10014

1

T3

4

T6

28

T7

6

lc_esc_on

32

1

T291

1

T169

1

T400

1

---

Summary for Variable flash_data_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9421

1

T3

4

T6

28

T7

6

auto[1]

625

1

T117

1

T119

7

T123

5

---

Summary for Variable flash_data_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1543

1

T6

14

T115

11

T117

3

auto[1]

8503

1

T3

4

T6

14

T7

6

---

Summary for Variable flash_data_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8412

1

T3

4

T6

27

T7

6

auto[1]

1634

1

T6

1

T8

1

T122

3

---

Summary for Variable flash_data_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9809

1

T3

4

T6

28

T7

6

auto[1]

237

1

T119

4

T123

2

T282

2