Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	45028	1			T4	135		T7	10		T95	93
access_err	47936	1			T6	14		T7	11		T12	195
write_blank_err	291	1			T8	3		T146	1		T9	2
ecc_uncorr_err	51089	1			T8	611		T134	524		T146	401
ecc_corr_err	1448	1			T7	5		T134	9		T70	1
no_err	70019	1			T3	65		T6	24		T7	20

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	538	1			T8	7		T9	5		T10	7
secret2	16457	1			T3	6		T6	4		T7	4
secret1	24516	1			T3	9		T6	1		T7	4
secret0	28304	1			T3	5		T6	5		T7	2
hw_cfg1	27632	1			T3	6		T6	4		T7	2
hw_cfg0	23661	1			T3	6		T6	2		T7	6
rot_creator_auth_state	16202	1			T3	7		T6	5		T7	5
rot_creator_auth_codesign	17070	1			T3	7		T6	4		T7	3
owner_sw_cfg	16965	1			T3	5		T4	135		T6	1
creator_sw_cfg	15900	1			T3	4		T6	7		T12	41
vendor_test	28566	1			T3	10		T6	5		T7	16

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2790	1			T200	225		T285	337		T169	175
fsm_err	secret1	4248	1			T197	32		T286	211		T158	322
fsm_err	secret0	5107	1			T156	50		T294	18		T398	268
fsm_err	hw_cfg1	3380	1			T399	86		T400	62		T172	56
fsm_err	hw_cfg0	3795	1			T155	38		T171	4		T191	12
fsm_err	rot_creator_auth_state	2459	1			T198	65		T192	7		T401	39
fsm_err	rot_creator_auth_codesign	3431	1			T238	14		T178	12		T291	474
fsm_err	owner_sw_cfg	2407	1			T4	135		T188	4		T189	6
fsm_err	creator_sw_cfg	2558	1			T176	10		T192	9		T217	37
fsm_err	vendor_test	14853	1			T7	10		T95	93		T70	9
access_err	life_cycle	538	1			T8	7		T9	5		T10	7
access_err	secret2	8174	1			T6	3		T7	3		T12	14
access_err	secret1	5249	1			T6	1		T7	4		T12	22
access_err	secret0	4411	1			T6	2		T12	26		T94	20
access_err	hw_cfg1	1121	1			T6	1		T7	1		T12	4
access_err	hw_cfg0	2026	1			T7	1		T12	12		T94	2
access_err	rot_creator_auth_state	4135	1			T12	18		T8	1		T94	19
access_err	rot_creator_auth_codesign	5822	1			T6	2		T7	1		T12	20
access_err	owner_sw_cfg	5162	1			T7	1		T12	32		T94	33
access_err	creator_sw_cfg	5901	1			T6	3		T12	29		T94	23
access_err	vendor_test	5397	1			T6	2		T12	18		T8	2
write_blank_err	secret2	4	1			T22	1		T402	1		T377	1
write_blank_err	secret1	21	1			T9	1		T403	1		T404	1
write_blank_err	secret0	33	1			T8	1		T146	1		T109	1
write_blank_err	hw_cfg1	52	1			T10	1		T405	1		T109	1
write_blank_err	hw_cfg0	19	1			T111	1		T147	1		T390	1
write_blank_err	rot_creator_auth_state	93	1			T8	1		T9	1		T233	1
write_blank_err	rot_creator_auth_codesign	26	1			T111	1		T327	4		T147	1
write_blank_err	owner_sw_cfg	19	1			T26	6		T260	1		T22	1
write_blank_err	creator_sw_cfg	4	1			T327	1		T258	1		T390	1
write_blank_err	vendor_test	20	1			T8	1		T406	2		T390	1
ecc_uncorr_err	secret2	1063	1			T216	37		T189	10		T407	4
ecc_uncorr_err	secret1	8388	1			T134	60		T9	245		T175	13
ecc_uncorr_err	secret0	12525	1			T8	611		T134	137		T146	401
ecc_uncorr_err	hw_cfg1	14809	1			T134	62		T10	652		T178	10
ecc_uncorr_err	hw_cfg0	8352	1			T176	4		T177	9		T178	14
ecc_uncorr_err	rot_creator_auth_state	2710	1			T134	130		T233	602		T408	689
ecc_uncorr_err	rot_creator_auth_codesign	812	1			T134	69		T171	6		T216	86
ecc_uncorr_err	owner_sw_cfg	1837	1			T134	66		T175	39		T178	13
ecc_uncorr_err	creator_sw_cfg	593	1			T175	44		T178	8		T171	6
ecc_corr_err	secret2	96	1			T36	3		T37	1		T81	1
ecc_corr_err	secret1	135	1			T134	1		T175	8		T37	1
ecc_corr_err	secret0	112	1			T81	3		T171	1		T58	7
ecc_corr_err	hw_cfg1	232	1			T7	1		T175	3		T176	2
ecc_corr_err	hw_cfg0	327	1			T7	2		T134	7		T187	1
ecc_corr_err	rot_creator_auth_state	159	1			T187	1		T175	5		T176	2
ecc_corr_err	rot_creator_auth_codesign	140	1			T7	1		T134	1		T175	2
ecc_corr_err	owner_sw_cfg	102	1			T7	1		T36	3		T37	2
ecc_corr_err	creator_sw_cfg	145	1			T70	1		T36	10		T177	1
no_err	secret2	4330	1			T3	6		T6	1		T7	1
no_err	secret1	6475	1			T3	9		T12	13		T8	7
no_err	secret0	6116	1			T3	5		T6	3		T7	2
no_err	hw_cfg1	8038	1			T3	6		T6	3		T12	27
no_err	hw_cfg0	9142	1			T3	6		T6	2		T7	3
no_err	rot_creator_auth_state	6646	1			T3	7		T6	5		T7	5
no_err	rot_creator_auth_codesign	6839	1			T3	7		T6	2		T7	1
no_err	owner_sw_cfg	7438	1			T3	5		T6	1		T7	2
no_err	creator_sw_cfg	6699	1			T3	4		T6	4		T12	12
no_err	vendor_test	8296	1			T3	10		T6	3		T7	6

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded