Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	37867	1			T5	22		T66	115		T124	19
access_err	47711	1			T11	17		T130	9		T8	15
write_blank_err	320	1			T8	2		T198	2		T9	1
ecc_uncorr_err	51889	1			T130	76		T8	269		T198	436
ecc_corr_err	1383	1			T5	3		T130	2		T8	1
no_err	67531	1			T5	17		T7	70		T6	61

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	551	1			T8	11		T9	9		T10	4
secret2	17287	1			T5	1		T7	7		T6	2
secret1	22959	1			T5	4		T7	9		T6	15
secret0	28850	1			T7	7		T6	4		T11	12
hw_cfg1	28803	1			T5	2		T7	5		T6	12
hw_cfg0	19736	1			T5	2		T7	5		T6	8
rot_creator_auth_state	16766	1			T5	3		T7	2		T6	4
rot_creator_auth_codesign	15493	1			T5	4		T7	5		T6	3
owner_sw_cfg	16310	1			T5	1		T7	11		T6	1
creator_sw_cfg	14098	1			T5	2		T7	14		T6	2
vendor_test	25848	1			T5	23		T7	5		T6	10

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3533	1			T210	204		T201	70		T365	361
fsm_err	secret1	2972	1			T124	19		T245	112		T255	24
fsm_err	secret0	4088	1			T144	456		T254	71		T273	182
fsm_err	hw_cfg1	3307	1			T153	33		T277	100		T366	65
fsm_err	hw_cfg0	2600	1			T244	255		T367	486		T223	15
fsm_err	rot_creator_auth_state	2710	1			T167	51		T163	51		T164	18
fsm_err	rot_creator_auth_codesign	2000	1			T152	29		T164	22		T368	9
fsm_err	owner_sw_cfg	2552	1			T146	599		T369	110		T157	2
fsm_err	creator_sw_cfg	1389	1			T218	19		T153	46		T109	34
fsm_err	vendor_test	12716	1			T5	22		T66	115		T37	90
access_err	life_cycle	551	1			T8	11		T9	9		T10	4
access_err	secret2	8020	1			T130	4		T86	38		T87	4
access_err	secret1	5340	1			T86	23		T87	3		T88	6
access_err	secret0	4375	1			T11	1		T86	26		T87	2
access_err	hw_cfg1	1119	1			T86	2		T87	2		T88	1
access_err	hw_cfg0	2139	1			T86	10		T88	1		T116	4
access_err	rot_creator_auth_state	4130	1			T11	4		T8	1		T86	19
access_err	rot_creator_auth_codesign	6001	1			T11	1		T8	3		T86	19
access_err	owner_sw_cfg	5026	1			T11	6		T86	5		T88	2
access_err	creator_sw_cfg	5769	1			T11	3		T130	5		T86	14
access_err	vendor_test	5241	1			T11	2		T86	24		T88	7
write_blank_err	secret2	3	1			T91	1		T370	1		T371	1
write_blank_err	secret1	17	1			T372	1		T373	1		T268	1
write_blank_err	secret0	36	1			T198	1		T221	1		T212	1
write_blank_err	hw_cfg1	56	1			T8	2		T9	1		T259	1
write_blank_err	hw_cfg0	18	1			T10	1		T374	1		T15	1
write_blank_err	rot_creator_auth_state	102	1			T10	5		T259	5		T317	1
write_blank_err	rot_creator_auth_codesign	17	1			T15	1		T282	2		T375	1
write_blank_err	owner_sw_cfg	27	1			T10	2		T376	1		T236	6
write_blank_err	creator_sw_cfg	23	1			T317	4		T377	1		T236	9
write_blank_err	vendor_test	21	1			T198	1		T221	1		T259	1
ecc_uncorr_err	secret2	1186	1			T130	45		T167	49		T261	39
ecc_uncorr_err	secret1	8416	1			T153	54		T109	20		T163	95
ecc_uncorr_err	secret0	14580	1			T198	436		T153	159		T221	423
ecc_uncorr_err	hw_cfg1	16180	1			T8	269		T152	30		T9	686
ecc_uncorr_err	hw_cfg0	5721	1			T152	16		T153	52		T167	103
ecc_uncorr_err	rot_creator_auth_state	3059	1			T317	308		T261	131		T378	78
ecc_uncorr_err	rot_creator_auth_codesign	647	1			T130	31		T153	44		T109	42
ecc_uncorr_err	owner_sw_cfg	1601	1			T261	31		T163	95		T378	41
ecc_uncorr_err	creator_sw_cfg	499	1			T152	28		T153	52		T167	106
ecc_corr_err	secret2	73	1			T195	1		T152	1		T362	4
ecc_corr_err	secret1	133	1			T5	1		T195	7		T129	3
ecc_corr_err	secret0	164	1			T37	5		T261	2		T48	10
ecc_corr_err	hw_cfg1	240	1			T130	1		T8	1		T37	1
ecc_corr_err	hw_cfg0	238	1			T5	1		T66	1		T195	2
ecc_corr_err	rot_creator_auth_state	131	1			T37	1		T153	1		T261	4
ecc_corr_err	rot_creator_auth_codesign	149	1			T5	1		T153	2		T167	5
ecc_corr_err	owner_sw_cfg	145	1			T130	1		T66	1		T37	2
ecc_corr_err	creator_sw_cfg	110	1			T152	1		T37	1		T129	1
no_err	secret2	4472	1			T5	1		T7	7		T6	2
no_err	secret1	6081	1			T5	3		T7	9		T6	15
no_err	secret0	5607	1			T7	7		T6	4		T11	11
no_err	hw_cfg1	7901	1			T5	2		T7	5		T6	12
no_err	hw_cfg0	9020	1			T5	1		T7	5		T6	8
no_err	rot_creator_auth_state	6634	1			T5	3		T7	2		T6	4
no_err	rot_creator_auth_codesign	6679	1			T5	3		T7	5		T6	3
no_err	owner_sw_cfg	6959	1			T5	1		T7	11		T6	1
no_err	creator_sw_cfg	6308	1			T5	2		T7	14		T6	2
no_err	vendor_test	7870	1			T5	1		T7	5		T6	10

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded