Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	47256	1			T35	74		T55	18		T94	336
access_err	43034	1			T4	11		T9	4		T35	1
write_blank_err	368	1			T6	1		T7	1		T8	4
ecc_uncorr_err	54628	1			T133	149		T6	727		T159	95
ecc_corr_err	1435	1			T35	5		T133	10		T36	7
no_err	66819	1			T2	68		T4	17		T9	41

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	616	1			T6	3		T7	5		T8	4
secret2	17816	1			T2	11		T4	8		T9	2
secret1	20588	1			T2	4		T4	4		T9	3
secret0	28277	1			T2	6		T9	6		T5	5
hw_cfg1	31923	1			T2	7		T4	1		T9	4
hw_cfg0	20478	1			T2	6		T4	1		T5	7
rot_creator_auth_state	19952	1			T2	6		T9	4		T5	11
rot_creator_auth_codesign	16484	1			T2	3		T4	2		T9	4
owner_sw_cfg	16356	1			T2	9		T4	1		T9	8
creator_sw_cfg	15284	1			T2	5		T4	5		T9	3
vendor_test	25766	1			T2	11		T4	6		T9	11

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3132	1			T182	68		T259	67		T179	61
fsm_err	secret1	4940	1			T169	125		T165	19		T16	404
fsm_err	secret0	3788	1			T317	20		T170	1		T165	215
fsm_err	hw_cfg1	4957	1			T385	626		T257	75		T175	42
fsm_err	hw_cfg0	4602	1			T173	84		T313	254		T378	332
fsm_err	rot_creator_auth_state	3263	1			T181	7		T201	47		T221	136
fsm_err	rot_creator_auth_codesign	3460	1			T185	44		T181	7		T201	47
fsm_err	owner_sw_cfg	3412	1			T94	336		T96	150		T180	31
fsm_err	creator_sw_cfg	2713	1			T185	49		T115	41		T260	27
fsm_err	vendor_test	12989	1			T35	74		T55	18		T133	43
access_err	life_cycle	616	1			T6	3		T7	5		T8	4
access_err	secret2	7308	1			T4	8		T35	1		T51	9
access_err	secret1	4784	1			T4	2		T51	7		T55	1
access_err	secret0	3822	1			T9	2		T51	2		T95	8
access_err	hw_cfg1	1091	1			T9	2		T51	7		T95	3
access_err	hw_cfg0	1838	1			T95	1		T98	2		T123	1
access_err	rot_creator_auth_state	3497	1			T51	3		T95	2		T98	7
access_err	rot_creator_auth_codesign	5332	1			T51	5		T95	10		T98	16
access_err	owner_sw_cfg	4684	1			T95	2		T98	17		T123	2
access_err	creator_sw_cfg	5065	1			T4	1		T51	4		T55	1
access_err	vendor_test	4997	1			T51	8		T95	17		T98	22
write_blank_err	secret2	8	1			T386	1		T107	1		T151	1
write_blank_err	secret1	15	1			T387	1		T236	1		T388	1
write_blank_err	secret0	37	1			T184	1		T389	1		T14	1
write_blank_err	hw_cfg1	66	1			T6	1		T7	1		T8	1
write_blank_err	hw_cfg0	11	1			T383	1		T99	1		T306	1
write_blank_err	rot_creator_auth_state	109	1			T186	1		T230	1		T237	2
write_blank_err	rot_creator_auth_codesign	44	1			T14	3		T390	7		T238	2
write_blank_err	owner_sw_cfg	53	1			T8	3		T390	3		T391	2
write_blank_err	creator_sw_cfg	11	1			T239	1		T392	1		T393	3
write_blank_err	vendor_test	14	1			T390	1		T238	3		T246	2
ecc_uncorr_err	secret2	3012	1			T181	5		T115	49		T182	136
ecc_uncorr_err	secret1	4564	1			T159	9		T181	5		T182	152
ecc_uncorr_err	secret0	14746	1			T184	567		T180	73		T389	347
ecc_uncorr_err	hw_cfg1	17926	1			T6	727		T7	429		T8	494
ecc_uncorr_err	hw_cfg0	4882	1			T159	7		T185	45		T181	8
ecc_uncorr_err	rot_creator_auth_state	6315	1			T133	72		T181	7		T115	39
ecc_uncorr_err	rot_creator_auth_codesign	779	1			T133	35		T159	40		T196	37
ecc_uncorr_err	owner_sw_cfg	1086	1			T185	52		T115	51		T201	52
ecc_uncorr_err	creator_sw_cfg	1318	1			T133	42		T159	39		T180	71
ecc_corr_err	secret2	100	1			T180	2		T185	3		T181	1
ecc_corr_err	secret1	106	1			T35	1		T133	5		T115	3
ecc_corr_err	secret0	133	1			T36	1		T159	4		T52	2
ecc_corr_err	hw_cfg1	300	1			T35	1		T36	1		T159	2
ecc_corr_err	hw_cfg0	244	1			T133	2		T180	2		T139	4
ecc_corr_err	rot_creator_auth_state	164	1			T35	1		T133	2		T36	1
ecc_corr_err	rot_creator_auth_codesign	151	1			T35	2		T36	3		T159	2
ecc_corr_err	owner_sw_cfg	129	1			T133	1		T36	1		T180	3
ecc_corr_err	creator_sw_cfg	108	1			T159	3		T180	1		T52	3
no_err	secret2	4256	1			T2	11		T9	2		T5	5
no_err	secret1	6179	1			T2	4		T4	2		T9	3
no_err	secret0	5751	1			T2	6		T9	4		T5	5
no_err	hw_cfg1	7583	1			T2	7		T4	1		T9	2
no_err	hw_cfg0	8901	1			T2	6		T4	1		T5	7
no_err	rot_creator_auth_state	6604	1			T2	6		T9	4		T5	11
no_err	rot_creator_auth_codesign	6718	1			T2	3		T4	2		T9	4
no_err	owner_sw_cfg	6992	1			T2	9		T4	1		T9	8
no_err	creator_sw_cfg	6069	1			T2	5		T4	4		T9	3
no_err	vendor_test	7766	1			T2	11		T4	6		T9	11

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded