Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

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Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
lc_esc_during_flash_addr_req	2	0	2	100.00	100	1	1	2
lc_esc_during_flash_data_req	2	0	2	100.00	100	1	1	2
lc_esc_during_lc_otp_prog_req	2	0	2	100.00	100	1	1	2
lc_esc_during_otbn_req	2	0	2	100.00	100	1	1	2
lc_esc_during_otp_idle	2	0	2	100.00	100	1	1	2
lc_esc_during_sram_0_req	2	0	2	100.00	100	1	1	2
lc_esc_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable lc_esc_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

336

1

T222

2

T266

2

T167

2

auto[1]

38

1

T385

1

T458

1

T459

1

---

Summary for Variable lc_esc_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

332

1

T222

2

T266

2

T167

1

auto[1]

42

1

T167

1

T137

1

T460

1

---

Summary for Variable lc_esc_during_lc_otp_prog_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_lc_otp_prog_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

334

1

T222

2

T266

2

T167

2

auto[1]

40

1

T13

1

T237

1

T461

1

---

Summary for Variable lc_esc_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338

1

T222

2

T266

2

T167

2

auto[1]

36

1

T156

1

T462

1

T284

2

---

Summary for Variable lc_esc_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36

1

T137

1

T236

1

T237

1

auto[1]

338

1

T222

2

T266

2

T167

2

---

Summary for Variable lc_esc_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323

1

T222

1

T266

1

T167

2

auto[1]

51

1

T222

1

T266

1

T374

1

---

Summary for Variable lc_esc_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324

1

T222

1

T266

1

T167

2

auto[1]

50

1

T222

1

T266

1

T374

1