Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	2	0	2	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	8	0	8	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr_pin

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_pins[0]

148770

1

T2

28

T3

4

T7

89

all_pins[1]

148770

1

T2

28

T3

4

T7

89

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	235276	1			T2	29		T3	5		T7	89
values[0x1]	62264	1			T2	27		T3	3		T7	89
transitions[0x0=>0x1]	46464	1			T2	27		T3	3		T7	89
transitions[0x1=>0x0]	46375	1			T2	27		T3	3		T7	88

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	103262	1			T2	1		T3	1		T4	19
all_pins[0]	values[0x1]	45508	1			T2	27		T3	3		T7	89
all_pins[0]	transitions[0x0=>0x1]	37660	1			T2	27		T3	3		T7	89
all_pins[0]	transitions[0x1=>0x0]	8908	1			T4	6		T12	25		T90	9
all_pins[1]	values[0x0]	132014	1			T2	28		T3	4		T7	89
all_pins[1]	values[0x1]	16756	1			T4	9		T12	49		T90	9
all_pins[1]	transitions[0x0=>0x1]	8804	1			T4	6		T12	25		T90	9
all_pins[1]	transitions[0x1=>0x0]	37467	1			T2	27		T3	3		T7	88