Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	45640	1			T3	45		T125	264		T146	53
access_err	53446	1			T4	30		T5	59		T6	3
write_blank_err	377	1			T5	8		T8	11		T9	1
ecc_uncorr_err	54116	1			T5	157		T145	134		T146	324
ecc_corr_err	1317	1			T12	39		T145	1		T146	18
no_err	74079	1			T2	42		T4	23		T5	58

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	710	1			T5	8		T8	14		T9	3
secret2	21014	1			T2	6		T4	8		T5	15
secret1	26070	1			T2	2		T4	6		T5	2
secret0	30791	1			T2	6		T4	11		T5	169
hw_cfg1	26949	1			T2	5		T4	2		T5	6
hw_cfg0	23755	1			T2	2		T4	5		T5	15
rot_creator_auth_state	17915	1			T2	7		T4	5		T5	26
rot_creator_auth_codesign	18216	1			T2	4		T3	45		T4	10
owner_sw_cfg	19095	1			T2	6		T4	4		T5	7
creator_sw_cfg	17105	1			T2	3		T4	2		T5	15
vendor_test	27355	1			T2	1		T5	10		T6	2

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3947	1			T222	127		T167	304		T155	22
fsm_err	secret1	4088	1			T125	264		T171	43		T157	106
fsm_err	secret0	3652	1			T374	266		T170	40		T375	59
fsm_err	hw_cfg1	2668	1			T171	54		T219	20		T301	68
fsm_err	hw_cfg0	4537	1			T115	186		T156	323		T172	32
fsm_err	rot_creator_auth_state	4083	1			T146	53		T266	333		T117	4
fsm_err	rot_creator_auth_codesign	2879	1			T3	45		T194	64		T242	25
fsm_err	owner_sw_cfg	4543	1			T170	12		T225	79		T263	535
fsm_err	creator_sw_cfg	2757	1			T117	7		T172	39		T376	47
fsm_err	vendor_test	12486	1			T49	99		T50	19		T87	18
access_err	life_cycle	710	1			T5	8		T8	14		T9	3
access_err	secret2	8716	1			T4	5		T5	15		T12	4
access_err	secret1	6323	1			T4	6		T12	22		T90	7
access_err	secret0	4779	1			T4	11		T12	2		T90	6
access_err	hw_cfg1	1157	1			T12	3		T24	2		T125	1
access_err	hw_cfg0	2305	1			T6	3		T90	3		T24	7
access_err	rot_creator_auth_state	4677	1			T4	3		T5	13		T12	8
access_err	rot_creator_auth_codesign	6738	1			T4	5		T5	5		T12	14
access_err	owner_sw_cfg	5586	1			T5	3		T12	4		T90	6
access_err	creator_sw_cfg	6466	1			T5	11		T12	17		T90	2
access_err	vendor_test	5989	1			T5	4		T12	9		T90	3
write_blank_err	secret2	8	1			T318	1		T377	1		T378	1
write_blank_err	secret1	23	1			T228	1		T379	1		T265	1
write_blank_err	secret0	44	1			T5	1		T8	1		T9	1
write_blank_err	hw_cfg1	49	1			T8	1		T238	1		T380	1
write_blank_err	hw_cfg0	18	1			T228	1		T134	1		T381	1
write_blank_err	rot_creator_auth_state	139	1			T5	4		T8	6		T175	1
write_blank_err	rot_creator_auth_codesign	43	1			T8	3		T175	1		T382	3
write_blank_err	owner_sw_cfg	29	1			T5	2		T318	4		T256	2
write_blank_err	creator_sw_cfg	11	1			T368	3		T91	1		T383	1
write_blank_err	vendor_test	13	1			T5	1		T318	1		T382	1
ecc_uncorr_err	secret2	3481	1			T176	54		T318	370		T171	64
ecc_uncorr_err	secret1	9188	1			T145	71		T117	7		T170	14
ecc_uncorr_err	secret0	15943	1			T5	157		T145	63		T146	51
ecc_uncorr_err	hw_cfg1	13907	1			T146	49		T8	200		T117	6
ecc_uncorr_err	hw_cfg0	6686	1			T146	24		T117	6		T192	72
ecc_uncorr_err	rot_creator_auth_state	1706	1			T146	96		T174	78		T117	6
ecc_uncorr_err	rot_creator_auth_codesign	1126	1			T176	72		T384	8		T192	70
ecc_uncorr_err	owner_sw_cfg	1056	1			T146	53		T177	29		T184	24
ecc_uncorr_err	creator_sw_cfg	1023	1			T146	51		T174	74		T176	69
ecc_corr_err	secret2	68	1			T100	2		T170	1		T76	1
ecc_corr_err	secret1	76	1			T12	3		T146	5		T35	1
ecc_corr_err	secret0	135	1			T12	4		T146	4		T8	1
ecc_corr_err	hw_cfg1	288	1			T12	16		T146	1		T49	12
ecc_corr_err	hw_cfg0	212	1			T12	10		T49	4		T176	1
ecc_corr_err	rot_creator_auth_state	151	1			T146	1		T49	1		T176	3
ecc_corr_err	rot_creator_auth_codesign	112	1			T12	3		T145	1		T146	7
ecc_corr_err	owner_sw_cfg	145	1			T12	1		T49	1		T117	2
ecc_corr_err	creator_sw_cfg	130	1			T12	2		T49	2		T35	2
no_err	secret2	4794	1			T2	6		T4	3		T6	5
no_err	secret1	6372	1			T2	2		T5	2		T6	2
no_err	secret0	6238	1			T2	6		T5	11		T6	2
no_err	hw_cfg1	8880	1			T2	5		T4	2		T5	6
no_err	hw_cfg0	9997	1			T2	2		T4	5		T5	15
no_err	rot_creator_auth_state	7159	1			T2	7		T4	2		T5	9
no_err	rot_creator_auth_codesign	7318	1			T2	4		T4	5		T5	4
no_err	owner_sw_cfg	7736	1			T2	6		T4	4		T5	2
no_err	creator_sw_cfg	6718	1			T2	3		T4	2		T5	4
no_err	vendor_test	8867	1			T2	1		T5	5		T6	2

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded