Group : tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg
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Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
lc_prog_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_lc_esc 2 0 2 100.00 100 1 1 0
lc_prog_req_during_otbn_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_otp_idle 2 0 2 100.00 100 1 1 2
lc_prog_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable lc_prog_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_flash_addr_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19902 1 T5 4 T8 4 T7 2
auto[1] 732 1 T113 1 T132 1 T88 1



Summary for Variable lc_prog_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_flash_data_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19888 1 T5 4 T8 4 T7 2
auto[1] 746 1 T132 2 T88 1 T89 2



Summary for Variable lc_prog_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for lc_prog_req_during_lc_esc

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
lc_esc_off 20601 1 T5 4 T8 4 T7 2
lc_esc_on 33 1 T293 1 T100 1 T483 1



Summary for Variable lc_prog_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_otbn_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19249 1 T5 4 T8 3 T7 2
auto[1] 1385 1 T8 1 T9 4 T130 1



Summary for Variable lc_prog_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_otp_idle

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 11281 1 T5 2 T8 2 T7 1
auto[1] 9353 1 T5 2 T8 2 T7 1



Summary for Variable lc_prog_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_sram_0_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19284 1 T5 4 T8 4 T7 2
auto[1] 1350 1 T130 2 T113 1 T132 3



Summary for Variable lc_prog_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_sram_1_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19341 1 T5 4 T8 4 T7 2
auto[1] 1293 1 T130 1 T113 2 T132 2