Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	47324	1			T9	59		T13	76		T73	12
access_err	55098	1			T3	14		T9	7		T95	3
write_blank_err	302	1			T10	1		T11	3		T128	2
ecc_uncorr_err	51741	1			T9	22		T10	260		T11	378
ecc_corr_err	1525	1			T9	7		T73	4		T11	4
no_err	75365	1			T3	41		T5	28		T8	54

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	520	1			T10	15		T11	14		T12	2
secret2	21096	1			T3	4		T5	4		T8	8
secret1	27371	1			T3	5		T5	5		T8	5
secret0	29475	1			T3	8		T8	6		T9	6
hw_cfg1	27684	1			T3	3		T5	5		T8	1
hw_cfg0	19814	1			T3	4		T8	6		T7	1
rot_creator_auth_state	17772	1			T3	6		T8	6		T9	35
rot_creator_auth_codesign	19358	1			T3	4		T5	4		T8	9
owner_sw_cfg	16855	1			T3	12		T5	2		T8	4
creator_sw_cfg	20134	1			T3	2		T5	2		T8	4
vendor_test	31276	1			T3	7		T5	6		T8	5

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2544	1			T329	441		T259	353		T379	86
fsm_err	secret1	5487	1			T159	106		T380	71		T245	512
fsm_err	secret0	3976	1			T293	3		T381	72		T382	459
fsm_err	hw_cfg1	3111	1			T117	142		T15	109		T254	320
fsm_err	hw_cfg0	4207	1			T120	209		T157	48		T383	345
fsm_err	rot_creator_auth_state	2221	1			T9	31		T171	9		T172	9
fsm_err	rot_creator_auth_codesign	3092	1			T166	40		T167	45		T194	65
fsm_err	owner_sw_cfg	2235	1			T9	10		T13	76		T156	67
fsm_err	creator_sw_cfg	4264	1			T158	23		T159	53		T257	269
fsm_err	vendor_test	16187	1			T9	18		T73	12		T102	98
access_err	life_cycle	520	1			T10	15		T11	14		T12	2
access_err	secret2	9513	1			T3	4		T9	7		T106	1
access_err	secret1	6092	1			T113	4		T132	2		T96	11
access_err	secret0	5064	1			T3	1		T130	1		T113	10
access_err	hw_cfg1	1208	1			T95	3		T113	3		T96	12
access_err	hw_cfg0	2437	1			T113	4		T88	1		T103	18
access_err	rot_creator_auth_state	4577	1			T3	3		T130	2		T113	2
access_err	rot_creator_auth_codesign	6820	1			T113	7		T10	16		T96	14
access_err	owner_sw_cfg	6004	1			T3	4		T130	2		T113	11
access_err	creator_sw_cfg	6529	1			T3	2		T113	9		T96	33
access_err	vendor_test	6334	1			T113	8		T10	9		T96	25
write_blank_err	secret2	9	1			T260	1		T384	1		T264	1
write_blank_err	secret1	21	1			T218	1		T217	1		T233	1
write_blank_err	secret0	36	1			T12	1		T15	1		T385	1
write_blank_err	hw_cfg1	49	1			T10	1		T11	3		T128	2
write_blank_err	hw_cfg0	6	1			T386	1		T382	1		T387	1
write_blank_err	rot_creator_auth_state	96	1			T173	1		T12	5		T217	2
write_blank_err	rot_creator_auth_codesign	25	1			T266	1		T388	1		T265	2
write_blank_err	owner_sw_cfg	13	1			T203	1		T389	3		T386	1
write_blank_err	creator_sw_cfg	15	1			T390	6		T391	1		T240	1
write_blank_err	vendor_test	32	1			T233	1		T203	2		T385	1
ecc_uncorr_err	secret2	4233	1			T171	6		T260	421		T166	35
ecc_uncorr_err	secret1	9005	1			T218	378		T156	121		T205	46
ecc_uncorr_err	secret0	13595	1			T9	2		T157	48		T12	437
ecc_uncorr_err	hw_cfg1	13876	1			T9	10		T10	260		T11	378
ecc_uncorr_err	hw_cfg0	2547	1			T156	70		T157	40		T171	11
ecc_uncorr_err	rot_creator_auth_state	3365	1			T173	618		T156	66		T157	46
ecc_uncorr_err	rot_creator_auth_codesign	2170	1			T9	10		T171	9		T205	54
ecc_uncorr_err	owner_sw_cfg	596	1			T158	21		T159	32		T172	5
ecc_uncorr_err	creator_sw_cfg	2354	1			T157	48		T205	117		T166	36
ecc_corr_err	secret2	76	1			T73	3		T51	2		T49	7
ecc_corr_err	secret1	152	1			T9	1		T102	3		T74	2
ecc_corr_err	secret0	155	1			T74	3		T156	1		T157	2
ecc_corr_err	hw_cfg1	332	1			T9	3		T11	4		T102	1
ecc_corr_err	hw_cfg0	225	1			T9	2		T73	1		T102	1
ecc_corr_err	rot_creator_auth_state	133	1			T9	1		T102	2		T74	6
ecc_corr_err	rot_creator_auth_codesign	123	1			T102	1		T74	2		T51	8
ecc_corr_err	owner_sw_cfg	177	1			T74	8		T156	2		T157	2
ecc_corr_err	creator_sw_cfg	152	1			T102	1		T74	1		T156	2
no_err	secret2	4721	1			T5	4		T8	8		T7	1
no_err	secret1	6614	1			T3	5		T5	5		T8	5
no_err	secret0	6649	1			T3	7		T8	6		T9	4
no_err	hw_cfg1	9108	1			T3	3		T5	5		T8	1
no_err	hw_cfg0	10392	1			T3	4		T8	6		T7	1
no_err	rot_creator_auth_state	7380	1			T3	3		T8	6		T9	3
no_err	rot_creator_auth_codesign	7128	1			T3	4		T5	4		T8	9
no_err	owner_sw_cfg	7830	1			T3	8		T5	2		T8	4
no_err	creator_sw_cfg	6820	1			T5	2		T8	4		T25	3
no_err	vendor_test	8723	1			T3	7		T5	6		T8	5

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded