Go
back
72 always_ff @(posedge clk_i or negedge rst_ni) begin
73 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
74 1/1 err_q <= '0;
Tests: T1 T2 T3
75 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
76 1/1 err_q <= 1'b1;
Tests: T27 T28 T29
77 end
MISSING_ELSE
78 end
79
80 // integrity error output is permanent and should be used for alert generation
81 // register errors are transactional
82 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
83
84 // outgoing integrity generation
85 tlul_pkg::tl_d2h_t tl_o_pre;
86 tlul_rsp_intg_gen #(
87 .EnableRspIntgGen(1),
88 .EnableDataIntgGen(1)
89 ) u_rsp_intg_gen (
90 .tl_i(tl_o_pre),
91 .tl_o(tl_o)
92 );
93
94 tlul_pkg::tl_h2d_t tl_socket_h2d [2];
95 tlul_pkg::tl_d2h_t tl_socket_d2h [2];
96
97 logic [0:0] reg_steer;
98
99 // socket_1n connection
100 1/1 assign tl_reg_h2d = tl_socket_h2d[1];
Tests: T1 T2 T3
101 1/1 assign tl_socket_d2h[1] = tl_reg_d2h;
Tests: T1 T2 T3
102
103 1/1 assign tl_win_o = tl_socket_h2d[0];
Tests: T1 T2 T3
104 1/1 assign tl_socket_d2h[0] = tl_win_i;
Tests: T1 T2 T3
105
106 // Create Socket_1n
107 tlul_socket_1n #(
108 .N (2),
109 .HReqPass (1'b1),
110 .HRspPass (1'b1),
111 .DReqPass ({2{1'b1}}),
112 .DRspPass ({2{1'b1}}),
113 .HReqDepth (4'h0),
114 .HRspDepth (4'h0),
115 .DReqDepth ({2{4'h0}}),
116 .DRspDepth ({2{4'h0}}),
117 .ExplicitErrs (1'b0)
118 ) u_socket (
119 .clk_i (clk_i),
120 .rst_ni (rst_ni),
121 .tl_h_i (tl_i),
122 .tl_h_o (tl_o_pre),
123 .tl_d_o (tl_socket_h2d),
124 .tl_d_i (tl_socket_d2h),
125 .dev_select_i (reg_steer)
126 );
127
128 // Create steering logic
129 always_comb begin
130 1/1 reg_steer =
Tests: T1 T2 T3
131 tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 1'd0 :
132 // Default set to register
133 1'd1;
134
135 // Override this in case of an integrity error
136 1/1 if (intg_err) begin
Tests: T1 T2 T3
137 1/1 reg_steer = 1'd1;
Tests: T302 T303 T304
138 end
MISSING_ELSE
139 end
140
141 tlul_adapter_reg #(
142 .RegAw(AW),
143 .RegDw(DW),
144 .EnableDataIntgGen(0)
145 ) u_reg_if (
146 .clk_i (clk_i),
147 .rst_ni (rst_ni),
148
149 .tl_i (tl_reg_h2d),
150 .tl_o (tl_reg_d2h),
151
152 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
153 .intg_error_o(),
154
155 .we_o (reg_we),
156 .re_o (reg_re),
157 .addr_o (reg_addr),
158 .wdata_o (reg_wdata),
159 .be_o (reg_be),
160 .busy_i (reg_busy),
161 .rdata_i (reg_rdata),
162 .error_i (reg_error)
163 );
164
165 // cdc oversampling signals
166
167 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
168 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T2 T3 T5
169
170 // Define SW related signals
171 // Format: <reg>_<field>_{wd|we|qs}
172 // or <reg>_{wd|we|qs} if field == 1 or 0
173 logic intr_state_we;
174 logic intr_state_otp_operation_done_qs;
175 logic intr_state_otp_operation_done_wd;
176 logic intr_state_otp_error_qs;
177 logic intr_state_otp_error_wd;
178 logic intr_enable_we;
179 logic intr_enable_otp_operation_done_qs;
180 logic intr_enable_otp_operation_done_wd;
181 logic intr_enable_otp_error_qs;
182 logic intr_enable_otp_error_wd;
183 logic intr_test_we;
184 logic intr_test_otp_operation_done_wd;
185 logic intr_test_otp_error_wd;
186 logic alert_test_we;
187 logic alert_test_fatal_macro_error_wd;
188 logic alert_test_fatal_check_error_wd;
189 logic alert_test_fatal_bus_integ_error_wd;
190 logic alert_test_fatal_prim_otp_alert_wd;
191 logic alert_test_recov_prim_otp_alert_wd;
192 logic status_re;
193 logic status_vendor_test_error_qs;
194 logic status_creator_sw_cfg_error_qs;
195 logic status_owner_sw_cfg_error_qs;
196 logic status_rot_creator_auth_codesign_error_qs;
197 logic status_rot_creator_auth_state_error_qs;
198 logic status_hw_cfg0_error_qs;
199 logic status_hw_cfg1_error_qs;
200 logic status_secret0_error_qs;
201 logic status_secret1_error_qs;
202 logic status_secret2_error_qs;
203 logic status_life_cycle_error_qs;
204 logic status_dai_error_qs;
205 logic status_lci_error_qs;
206 logic status_timeout_error_qs;
207 logic status_lfsr_fsm_error_qs;
208 logic status_scrambling_fsm_error_qs;
209 logic status_key_deriv_fsm_error_qs;
210 logic status_bus_integ_error_qs;
211 logic status_dai_idle_qs;
212 logic status_check_pending_qs;
213 logic err_code_0_re;
214 logic [2:0] err_code_0_qs;
215 logic err_code_1_re;
216 logic [2:0] err_code_1_qs;
217 logic err_code_2_re;
218 logic [2:0] err_code_2_qs;
219 logic err_code_3_re;
220 logic [2:0] err_code_3_qs;
221 logic err_code_4_re;
222 logic [2:0] err_code_4_qs;
223 logic err_code_5_re;
224 logic [2:0] err_code_5_qs;
225 logic err_code_6_re;
226 logic [2:0] err_code_6_qs;
227 logic err_code_7_re;
228 logic [2:0] err_code_7_qs;
229 logic err_code_8_re;
230 logic [2:0] err_code_8_qs;
231 logic err_code_9_re;
232 logic [2:0] err_code_9_qs;
233 logic err_code_10_re;
234 logic [2:0] err_code_10_qs;
235 logic err_code_11_re;
236 logic [2:0] err_code_11_qs;
237 logic err_code_12_re;
238 logic [2:0] err_code_12_qs;
239 logic direct_access_regwen_re;
240 logic direct_access_regwen_we;
241 logic direct_access_regwen_qs;
242 logic direct_access_regwen_wd;
243 logic direct_access_cmd_we;
244 logic direct_access_cmd_rd_wd;
245 logic direct_access_cmd_wr_wd;
246 logic direct_access_cmd_digest_wd;
247 logic direct_access_address_we;
248 logic [10:0] direct_access_address_qs;
249 logic [10:0] direct_access_address_wd;
250 logic direct_access_wdata_0_we;
251 logic [31:0] direct_access_wdata_0_qs;
252 logic [31:0] direct_access_wdata_0_wd;
253 logic direct_access_wdata_1_we;
254 logic [31:0] direct_access_wdata_1_qs;
255 logic [31:0] direct_access_wdata_1_wd;
256 logic direct_access_rdata_0_re;
257 logic [31:0] direct_access_rdata_0_qs;
258 logic direct_access_rdata_1_re;
259 logic [31:0] direct_access_rdata_1_qs;
260 logic check_trigger_regwen_we;
261 logic check_trigger_regwen_qs;
262 logic check_trigger_regwen_wd;
263 logic check_trigger_we;
264 logic check_trigger_integrity_wd;
265 logic check_trigger_consistency_wd;
266 logic check_regwen_we;
267 logic check_regwen_qs;
268 logic check_regwen_wd;
269 logic check_timeout_we;
270 logic [31:0] check_timeout_qs;
271 logic [31:0] check_timeout_wd;
272 logic integrity_check_period_we;
273 logic [31:0] integrity_check_period_qs;
274 logic [31:0] integrity_check_period_wd;
275 logic consistency_check_period_we;
276 logic [31:0] consistency_check_period_qs;
277 logic [31:0] consistency_check_period_wd;
278 logic vendor_test_read_lock_we;
279 logic vendor_test_read_lock_qs;
280 logic vendor_test_read_lock_wd;
281 logic creator_sw_cfg_read_lock_we;
282 logic creator_sw_cfg_read_lock_qs;
283 logic creator_sw_cfg_read_lock_wd;
284 logic owner_sw_cfg_read_lock_we;
285 logic owner_sw_cfg_read_lock_qs;
286 logic owner_sw_cfg_read_lock_wd;
287 logic rot_creator_auth_codesign_read_lock_we;
288 logic rot_creator_auth_codesign_read_lock_qs;
289 logic rot_creator_auth_codesign_read_lock_wd;
290 logic rot_creator_auth_state_read_lock_we;
291 logic rot_creator_auth_state_read_lock_qs;
292 logic rot_creator_auth_state_read_lock_wd;
293 logic vendor_test_digest_0_re;
294 logic [31:0] vendor_test_digest_0_qs;
295 logic vendor_test_digest_1_re;
296 logic [31:0] vendor_test_digest_1_qs;
297 logic creator_sw_cfg_digest_0_re;
298 logic [31:0] creator_sw_cfg_digest_0_qs;
299 logic creator_sw_cfg_digest_1_re;
300 logic [31:0] creator_sw_cfg_digest_1_qs;
301 logic owner_sw_cfg_digest_0_re;
302 logic [31:0] owner_sw_cfg_digest_0_qs;
303 logic owner_sw_cfg_digest_1_re;
304 logic [31:0] owner_sw_cfg_digest_1_qs;
305 logic rot_creator_auth_codesign_digest_0_re;
306 logic [31:0] rot_creator_auth_codesign_digest_0_qs;
307 logic rot_creator_auth_codesign_digest_1_re;
308 logic [31:0] rot_creator_auth_codesign_digest_1_qs;
309 logic rot_creator_auth_state_digest_0_re;
310 logic [31:0] rot_creator_auth_state_digest_0_qs;
311 logic rot_creator_auth_state_digest_1_re;
312 logic [31:0] rot_creator_auth_state_digest_1_qs;
313 logic hw_cfg0_digest_0_re;
314 logic [31:0] hw_cfg0_digest_0_qs;
315 logic hw_cfg0_digest_1_re;
316 logic [31:0] hw_cfg0_digest_1_qs;
317 logic hw_cfg1_digest_0_re;
318 logic [31:0] hw_cfg1_digest_0_qs;
319 logic hw_cfg1_digest_1_re;
320 logic [31:0] hw_cfg1_digest_1_qs;
321 logic secret0_digest_0_re;
322 logic [31:0] secret0_digest_0_qs;
323 logic secret0_digest_1_re;
324 logic [31:0] secret0_digest_1_qs;
325 logic secret1_digest_0_re;
326 logic [31:0] secret1_digest_0_qs;
327 logic secret1_digest_1_re;
328 logic [31:0] secret1_digest_1_qs;
329 logic secret2_digest_0_re;
330 logic [31:0] secret2_digest_0_qs;
331 logic secret2_digest_1_re;
332 logic [31:0] secret2_digest_1_qs;
333
334 // Register instances
335 // R[intr_state]: V(False)
336 // F[otp_operation_done]: 0:0
337 prim_subreg #(
338 .DW (1),
339 .SwAccess(prim_subreg_pkg::SwAccessW1C),
340 .RESVAL (1'h0),
341 .Mubi (1'b0)
342 ) u_intr_state_otp_operation_done (
343 .clk_i (clk_i),
344 .rst_ni (rst_ni),
345
346 // from register interface
347 .we (intr_state_we),
348 .wd (intr_state_otp_operation_done_wd),
349
350 // from internal hardware
351 .de (hw2reg.intr_state.otp_operation_done.de),
352 .d (hw2reg.intr_state.otp_operation_done.d),
353
354 // to internal hardware
355 .qe (),
356 .q (reg2hw.intr_state.otp_operation_done.q),
357 .ds (),
358
359 // to register interface (read)
360 .qs (intr_state_otp_operation_done_qs)
361 );
362
363 // F[otp_error]: 1:1
364 prim_subreg #(
365 .DW (1),
366 .SwAccess(prim_subreg_pkg::SwAccessW1C),
367 .RESVAL (1'h0),
368 .Mubi (1'b0)
369 ) u_intr_state_otp_error (
370 .clk_i (clk_i),
371 .rst_ni (rst_ni),
372
373 // from register interface
374 .we (intr_state_we),
375 .wd (intr_state_otp_error_wd),
376
377 // from internal hardware
378 .de (hw2reg.intr_state.otp_error.de),
379 .d (hw2reg.intr_state.otp_error.d),
380
381 // to internal hardware
382 .qe (),
383 .q (reg2hw.intr_state.otp_error.q),
384 .ds (),
385
386 // to register interface (read)
387 .qs (intr_state_otp_error_qs)
388 );
389
390
391 // R[intr_enable]: V(False)
392 // F[otp_operation_done]: 0:0
393 prim_subreg #(
394 .DW (1),
395 .SwAccess(prim_subreg_pkg::SwAccessRW),
396 .RESVAL (1'h0),
397 .Mubi (1'b0)
398 ) u_intr_enable_otp_operation_done (
399 .clk_i (clk_i),
400 .rst_ni (rst_ni),
401
402 // from register interface
403 .we (intr_enable_we),
404 .wd (intr_enable_otp_operation_done_wd),
405
406 // from internal hardware
407 .de (1'b0),
408 .d ('0),
409
410 // to internal hardware
411 .qe (),
412 .q (reg2hw.intr_enable.otp_operation_done.q),
413 .ds (),
414
415 // to register interface (read)
416 .qs (intr_enable_otp_operation_done_qs)
417 );
418
419 // F[otp_error]: 1:1
420 prim_subreg #(
421 .DW (1),
422 .SwAccess(prim_subreg_pkg::SwAccessRW),
423 .RESVAL (1'h0),
424 .Mubi (1'b0)
425 ) u_intr_enable_otp_error (
426 .clk_i (clk_i),
427 .rst_ni (rst_ni),
428
429 // from register interface
430 .we (intr_enable_we),
431 .wd (intr_enable_otp_error_wd),
432
433 // from internal hardware
434 .de (1'b0),
435 .d ('0),
436
437 // to internal hardware
438 .qe (),
439 .q (reg2hw.intr_enable.otp_error.q),
440 .ds (),
441
442 // to register interface (read)
443 .qs (intr_enable_otp_error_qs)
444 );
445
446
447 // R[intr_test]: V(True)
448 logic intr_test_qe;
449 logic [1:0] intr_test_flds_we;
450 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T14 T15 T305
451 // F[otp_operation_done]: 0:0
452 prim_subreg_ext #(
453 .DW (1)
454 ) u_intr_test_otp_operation_done (
455 .re (1'b0),
456 .we (intr_test_we),
457 .wd (intr_test_otp_operation_done_wd),
458 .d ('0),
459 .qre (),
460 .qe (intr_test_flds_we[0]),
461 .q (reg2hw.intr_test.otp_operation_done.q),
462 .ds (),
463 .qs ()
464 );
465 1/1 assign reg2hw.intr_test.otp_operation_done.qe = intr_test_qe;
Tests: T14 T15 T305
466
467 // F[otp_error]: 1:1
468 prim_subreg_ext #(
469 .DW (1)
470 ) u_intr_test_otp_error (
471 .re (1'b0),
472 .we (intr_test_we),
473 .wd (intr_test_otp_error_wd),
474 .d ('0),
475 .qre (),
476 .qe (intr_test_flds_we[1]),
477 .q (reg2hw.intr_test.otp_error.q),
478 .ds (),
479 .qs ()
480 );
481 1/1 assign reg2hw.intr_test.otp_error.qe = intr_test_qe;
Tests: T14 T15 T305
482
483
484 // R[alert_test]: V(True)
485 logic alert_test_qe;
486 logic [4:0] alert_test_flds_we;
487 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T2 T17 T112
488 // F[fatal_macro_error]: 0:0
489 prim_subreg_ext #(
490 .DW (1)
491 ) u_alert_test_fatal_macro_error (
492 .re (1'b0),
493 .we (alert_test_we),
494 .wd (alert_test_fatal_macro_error_wd),
495 .d ('0),
496 .qre (),
497 .qe (alert_test_flds_we[0]),
498 .q (reg2hw.alert_test.fatal_macro_error.q),
499 .ds (),
500 .qs ()
501 );
502 1/1 assign reg2hw.alert_test.fatal_macro_error.qe = alert_test_qe;
Tests: T2 T17 T112
503
504 // F[fatal_check_error]: 1:1
505 prim_subreg_ext #(
506 .DW (1)
507 ) u_alert_test_fatal_check_error (
508 .re (1'b0),
509 .we (alert_test_we),
510 .wd (alert_test_fatal_check_error_wd),
511 .d ('0),
512 .qre (),
513 .qe (alert_test_flds_we[1]),
514 .q (reg2hw.alert_test.fatal_check_error.q),
515 .ds (),
516 .qs ()
517 );
518 1/1 assign reg2hw.alert_test.fatal_check_error.qe = alert_test_qe;
Tests: T2 T17 T112
519
520 // F[fatal_bus_integ_error]: 2:2
521 prim_subreg_ext #(
522 .DW (1)
523 ) u_alert_test_fatal_bus_integ_error (
524 .re (1'b0),
525 .we (alert_test_we),
526 .wd (alert_test_fatal_bus_integ_error_wd),
527 .d ('0),
528 .qre (),
529 .qe (alert_test_flds_we[2]),
530 .q (reg2hw.alert_test.fatal_bus_integ_error.q),
531 .ds (),
532 .qs ()
533 );
534 1/1 assign reg2hw.alert_test.fatal_bus_integ_error.qe = alert_test_qe;
Tests: T2 T17 T112
535
536 // F[fatal_prim_otp_alert]: 3:3
537 prim_subreg_ext #(
538 .DW (1)
539 ) u_alert_test_fatal_prim_otp_alert (
540 .re (1'b0),
541 .we (alert_test_we),
542 .wd (alert_test_fatal_prim_otp_alert_wd),
543 .d ('0),
544 .qre (),
545 .qe (alert_test_flds_we[3]),
546 .q (reg2hw.alert_test.fatal_prim_otp_alert.q),
547 .ds (),
548 .qs ()
549 );
550 1/1 assign reg2hw.alert_test.fatal_prim_otp_alert.qe = alert_test_qe;
Tests: T2 T17 T112
551
552 // F[recov_prim_otp_alert]: 4:4
553 prim_subreg_ext #(
554 .DW (1)
555 ) u_alert_test_recov_prim_otp_alert (
556 .re (1'b0),
557 .we (alert_test_we),
558 .wd (alert_test_recov_prim_otp_alert_wd),
559 .d ('0),
560 .qre (),
561 .qe (alert_test_flds_we[4]),
562 .q (reg2hw.alert_test.recov_prim_otp_alert.q),
563 .ds (),
564 .qs ()
565 );
566 1/1 assign reg2hw.alert_test.recov_prim_otp_alert.qe = alert_test_qe;
Tests: T2 T17 T112
567
568
569 // R[status]: V(True)
570 // F[vendor_test_error]: 0:0
571 prim_subreg_ext #(
572 .DW (1)
573 ) u_status_vendor_test_error (
574 .re (status_re),
575 .we (1'b0),
576 .wd ('0),
577 .d (hw2reg.status.vendor_test_error.d),
578 .qre (),
579 .qe (),
580 .q (),
581 .ds (),
582 .qs (status_vendor_test_error_qs)
583 );
584
585 // F[creator_sw_cfg_error]: 1:1
586 prim_subreg_ext #(
587 .DW (1)
588 ) u_status_creator_sw_cfg_error (
589 .re (status_re),
590 .we (1'b0),
591 .wd ('0),
592 .d (hw2reg.status.creator_sw_cfg_error.d),
593 .qre (),
594 .qe (),
595 .q (),
596 .ds (),
597 .qs (status_creator_sw_cfg_error_qs)
598 );
599
600 // F[owner_sw_cfg_error]: 2:2
601 prim_subreg_ext #(
602 .DW (1)
603 ) u_status_owner_sw_cfg_error (
604 .re (status_re),
605 .we (1'b0),
606 .wd ('0),
607 .d (hw2reg.status.owner_sw_cfg_error.d),
608 .qre (),
609 .qe (),
610 .q (),
611 .ds (),
612 .qs (status_owner_sw_cfg_error_qs)
613 );
614
615 // F[rot_creator_auth_codesign_error]: 3:3
616 prim_subreg_ext #(
617 .DW (1)
618 ) u_status_rot_creator_auth_codesign_error (
619 .re (status_re),
620 .we (1'b0),
621 .wd ('0),
622 .d (hw2reg.status.rot_creator_auth_codesign_error.d),
623 .qre (),
624 .qe (),
625 .q (),
626 .ds (),
627 .qs (status_rot_creator_auth_codesign_error_qs)
628 );
629
630 // F[rot_creator_auth_state_error]: 4:4
631 prim_subreg_ext #(
632 .DW (1)
633 ) u_status_rot_creator_auth_state_error (
634 .re (status_re),
635 .we (1'b0),
636 .wd ('0),
637 .d (hw2reg.status.rot_creator_auth_state_error.d),
638 .qre (),
639 .qe (),
640 .q (),
641 .ds (),
642 .qs (status_rot_creator_auth_state_error_qs)
643 );
644
645 // F[hw_cfg0_error]: 5:5
646 prim_subreg_ext #(
647 .DW (1)
648 ) u_status_hw_cfg0_error (
649 .re (status_re),
650 .we (1'b0),
651 .wd ('0),
652 .d (hw2reg.status.hw_cfg0_error.d),
653 .qre (),
654 .qe (),
655 .q (),
656 .ds (),
657 .qs (status_hw_cfg0_error_qs)
658 );
659
660 // F[hw_cfg1_error]: 6:6
661 prim_subreg_ext #(
662 .DW (1)
663 ) u_status_hw_cfg1_error (
664 .re (status_re),
665 .we (1'b0),
666 .wd ('0),
667 .d (hw2reg.status.hw_cfg1_error.d),
668 .qre (),
669 .qe (),
670 .q (),
671 .ds (),
672 .qs (status_hw_cfg1_error_qs)
673 );
674
675 // F[secret0_error]: 7:7
676 prim_subreg_ext #(
677 .DW (1)
678 ) u_status_secret0_error (
679 .re (status_re),
680 .we (1'b0),
681 .wd ('0),
682 .d (hw2reg.status.secret0_error.d),
683 .qre (),
684 .qe (),
685 .q (),
686 .ds (),
687 .qs (status_secret0_error_qs)
688 );
689
690 // F[secret1_error]: 8:8
691 prim_subreg_ext #(
692 .DW (1)
693 ) u_status_secret1_error (
694 .re (status_re),
695 .we (1'b0),
696 .wd ('0),
697 .d (hw2reg.status.secret1_error.d),
698 .qre (),
699 .qe (),
700 .q (),
701 .ds (),
702 .qs (status_secret1_error_qs)
703 );
704
705 // F[secret2_error]: 9:9
706 prim_subreg_ext #(
707 .DW (1)
708 ) u_status_secret2_error (
709 .re (status_re),
710 .we (1'b0),
711 .wd ('0),
712 .d (hw2reg.status.secret2_error.d),
713 .qre (),
714 .qe (),
715 .q (),
716 .ds (),
717 .qs (status_secret2_error_qs)
718 );
719
720 // F[life_cycle_error]: 10:10
721 prim_subreg_ext #(
722 .DW (1)
723 ) u_status_life_cycle_error (
724 .re (status_re),
725 .we (1'b0),
726 .wd ('0),
727 .d (hw2reg.status.life_cycle_error.d),
728 .qre (),
729 .qe (),
730 .q (),
731 .ds (),
732 .qs (status_life_cycle_error_qs)
733 );
734
735 // F[dai_error]: 11:11
736 prim_subreg_ext #(
737 .DW (1)
738 ) u_status_dai_error (
739 .re (status_re),
740 .we (1'b0),
741 .wd ('0),
742 .d (hw2reg.status.dai_error.d),
743 .qre (),
744 .qe (),
745 .q (),
746 .ds (),
747 .qs (status_dai_error_qs)
748 );
749
750 // F[lci_error]: 12:12
751 prim_subreg_ext #(
752 .DW (1)
753 ) u_status_lci_error (
754 .re (status_re),
755 .we (1'b0),
756 .wd ('0),
757 .d (hw2reg.status.lci_error.d),
758 .qre (),
759 .qe (),
760 .q (),
761 .ds (),
762 .qs (status_lci_error_qs)
763 );
764
765 // F[timeout_error]: 13:13
766 prim_subreg_ext #(
767 .DW (1)
768 ) u_status_timeout_error (
769 .re (status_re),
770 .we (1'b0),
771 .wd ('0),
772 .d (hw2reg.status.timeout_error.d),
773 .qre (),
774 .qe (),
775 .q (),
776 .ds (),
777 .qs (status_timeout_error_qs)
778 );
779
780 // F[lfsr_fsm_error]: 14:14
781 prim_subreg_ext #(
782 .DW (1)
783 ) u_status_lfsr_fsm_error (
784 .re (status_re),
785 .we (1'b0),
786 .wd ('0),
787 .d (hw2reg.status.lfsr_fsm_error.d),
788 .qre (),
789 .qe (),
790 .q (),
791 .ds (),
792 .qs (status_lfsr_fsm_error_qs)
793 );
794
795 // F[scrambling_fsm_error]: 15:15
796 prim_subreg_ext #(
797 .DW (1)
798 ) u_status_scrambling_fsm_error (
799 .re (status_re),
800 .we (1'b0),
801 .wd ('0),
802 .d (hw2reg.status.scrambling_fsm_error.d),
803 .qre (),
804 .qe (),
805 .q (),
806 .ds (),
807 .qs (status_scrambling_fsm_error_qs)
808 );
809
810 // F[key_deriv_fsm_error]: 16:16
811 prim_subreg_ext #(
812 .DW (1)
813 ) u_status_key_deriv_fsm_error (
814 .re (status_re),
815 .we (1'b0),
816 .wd ('0),
817 .d (hw2reg.status.key_deriv_fsm_error.d),
818 .qre (),
819 .qe (),
820 .q (),
821 .ds (),
822 .qs (status_key_deriv_fsm_error_qs)
823 );
824
825 // F[bus_integ_error]: 17:17
826 prim_subreg_ext #(
827 .DW (1)
828 ) u_status_bus_integ_error (
829 .re (status_re),
830 .we (1'b0),
831 .wd ('0),
832 .d (hw2reg.status.bus_integ_error.d),
833 .qre (),
834 .qe (),
835 .q (),
836 .ds (),
837 .qs (status_bus_integ_error_qs)
838 );
839
840 // F[dai_idle]: 18:18
841 prim_subreg_ext #(
842 .DW (1)
843 ) u_status_dai_idle (
844 .re (status_re),
845 .we (1'b0),
846 .wd ('0),
847 .d (hw2reg.status.dai_idle.d),
848 .qre (),
849 .qe (),
850 .q (),
851 .ds (),
852 .qs (status_dai_idle_qs)
853 );
854
855 // F[check_pending]: 19:19
856 prim_subreg_ext #(
857 .DW (1)
858 ) u_status_check_pending (
859 .re (status_re),
860 .we (1'b0),
861 .wd ('0),
862 .d (hw2reg.status.check_pending.d),
863 .qre (),
864 .qe (),
865 .q (),
866 .ds (),
867 .qs (status_check_pending_qs)
868 );
869
870
871 // Subregister 0 of Multireg err_code
872 // R[err_code_0]: V(True)
873 prim_subreg_ext #(
874 .DW (3)
875 ) u_err_code_0 (
876 .re (err_code_0_re),
877 .we (1'b0),
878 .wd ('0),
879 .d (hw2reg.err_code[0].d),
880 .qre (),
881 .qe (),
882 .q (),
883 .ds (),
884 .qs (err_code_0_qs)
885 );
886
887
888 // Subregister 1 of Multireg err_code
889 // R[err_code_1]: V(True)
890 prim_subreg_ext #(
891 .DW (3)
892 ) u_err_code_1 (
893 .re (err_code_1_re),
894 .we (1'b0),
895 .wd ('0),
896 .d (hw2reg.err_code[1].d),
897 .qre (),
898 .qe (),
899 .q (),
900 .ds (),
901 .qs (err_code_1_qs)
902 );
903
904
905 // Subregister 2 of Multireg err_code
906 // R[err_code_2]: V(True)
907 prim_subreg_ext #(
908 .DW (3)
909 ) u_err_code_2 (
910 .re (err_code_2_re),
911 .we (1'b0),
912 .wd ('0),
913 .d (hw2reg.err_code[2].d),
914 .qre (),
915 .qe (),
916 .q (),
917 .ds (),
918 .qs (err_code_2_qs)
919 );
920
921
922 // Subregister 3 of Multireg err_code
923 // R[err_code_3]: V(True)
924 prim_subreg_ext #(
925 .DW (3)
926 ) u_err_code_3 (
927 .re (err_code_3_re),
928 .we (1'b0),
929 .wd ('0),
930 .d (hw2reg.err_code[3].d),
931 .qre (),
932 .qe (),
933 .q (),
934 .ds (),
935 .qs (err_code_3_qs)
936 );
937
938
939 // Subregister 4 of Multireg err_code
940 // R[err_code_4]: V(True)
941 prim_subreg_ext #(
942 .DW (3)
943 ) u_err_code_4 (
944 .re (err_code_4_re),
945 .we (1'b0),
946 .wd ('0),
947 .d (hw2reg.err_code[4].d),
948 .qre (),
949 .qe (),
950 .q (),
951 .ds (),
952 .qs (err_code_4_qs)
953 );
954
955
956 // Subregister 5 of Multireg err_code
957 // R[err_code_5]: V(True)
958 prim_subreg_ext #(
959 .DW (3)
960 ) u_err_code_5 (
961 .re (err_code_5_re),
962 .we (1'b0),
963 .wd ('0),
964 .d (hw2reg.err_code[5].d),
965 .qre (),
966 .qe (),
967 .q (),
968 .ds (),
969 .qs (err_code_5_qs)
970 );
971
972
973 // Subregister 6 of Multireg err_code
974 // R[err_code_6]: V(True)
975 prim_subreg_ext #(
976 .DW (3)
977 ) u_err_code_6 (
978 .re (err_code_6_re),
979 .we (1'b0),
980 .wd ('0),
981 .d (hw2reg.err_code[6].d),
982 .qre (),
983 .qe (),
984 .q (),
985 .ds (),
986 .qs (err_code_6_qs)
987 );
988
989
990 // Subregister 7 of Multireg err_code
991 // R[err_code_7]: V(True)
992 prim_subreg_ext #(
993 .DW (3)
994 ) u_err_code_7 (
995 .re (err_code_7_re),
996 .we (1'b0),
997 .wd ('0),
998 .d (hw2reg.err_code[7].d),
999 .qre (),
1000 .qe (),
1001 .q (),
1002 .ds (),
1003 .qs (err_code_7_qs)
1004 );
1005
1006
1007 // Subregister 8 of Multireg err_code
1008 // R[err_code_8]: V(True)
1009 prim_subreg_ext #(
1010 .DW (3)
1011 ) u_err_code_8 (
1012 .re (err_code_8_re),
1013 .we (1'b0),
1014 .wd ('0),
1015 .d (hw2reg.err_code[8].d),
1016 .qre (),
1017 .qe (),
1018 .q (),
1019 .ds (),
1020 .qs (err_code_8_qs)
1021 );
1022
1023
1024 // Subregister 9 of Multireg err_code
1025 // R[err_code_9]: V(True)
1026 prim_subreg_ext #(
1027 .DW (3)
1028 ) u_err_code_9 (
1029 .re (err_code_9_re),
1030 .we (1'b0),
1031 .wd ('0),
1032 .d (hw2reg.err_code[9].d),
1033 .qre (),
1034 .qe (),
1035 .q (),
1036 .ds (),
1037 .qs (err_code_9_qs)
1038 );
1039
1040
1041 // Subregister 10 of Multireg err_code
1042 // R[err_code_10]: V(True)
1043 prim_subreg_ext #(
1044 .DW (3)
1045 ) u_err_code_10 (
1046 .re (err_code_10_re),
1047 .we (1'b0),
1048 .wd ('0),
1049 .d (hw2reg.err_code[10].d),
1050 .qre (),
1051 .qe (),
1052 .q (),
1053 .ds (),
1054 .qs (err_code_10_qs)
1055 );
1056
1057
1058 // Subregister 11 of Multireg err_code
1059 // R[err_code_11]: V(True)
1060 prim_subreg_ext #(
1061 .DW (3)
1062 ) u_err_code_11 (
1063 .re (err_code_11_re),
1064 .we (1'b0),
1065 .wd ('0),
1066 .d (hw2reg.err_code[11].d),
1067 .qre (),
1068 .qe (),
1069 .q (),
1070 .ds (),
1071 .qs (err_code_11_qs)
1072 );
1073
1074
1075 // Subregister 12 of Multireg err_code
1076 // R[err_code_12]: V(True)
1077 prim_subreg_ext #(
1078 .DW (3)
1079 ) u_err_code_12 (
1080 .re (err_code_12_re),
1081 .we (1'b0),
1082 .wd ('0),
1083 .d (hw2reg.err_code[12].d),
1084 .qre (),
1085 .qe (),
1086 .q (),
1087 .ds (),
1088 .qs (err_code_12_qs)
1089 );
1090
1091
1092 // R[direct_access_regwen]: V(True)
1093 logic direct_access_regwen_qe;
1094 logic [0:0] direct_access_regwen_flds_we;
1095 1/1 assign direct_access_regwen_qe = &direct_access_regwen_flds_we;
Tests: T14 T15 T16
1096 prim_subreg_ext #(
1097 .DW (1)
1098 ) u_direct_access_regwen (
1099 .re (direct_access_regwen_re),
1100 .we (direct_access_regwen_we),
1101 .wd (direct_access_regwen_wd),
1102 .d (hw2reg.direct_access_regwen.d),
1103 .qre (),
1104 .qe (direct_access_regwen_flds_we[0]),
1105 .q (reg2hw.direct_access_regwen.q),
1106 .ds (),
1107 .qs (direct_access_regwen_qs)
1108 );
1109 1/1 assign reg2hw.direct_access_regwen.qe = direct_access_regwen_qe;
Tests: T14 T15 T16
1110
1111
1112 // R[direct_access_cmd]: V(True)
1113 logic direct_access_cmd_qe;
1114 logic [2:0] direct_access_cmd_flds_we;
1115 1/1 assign direct_access_cmd_qe = &direct_access_cmd_flds_we;
Tests: T1 T3 T4
1116 // Create REGWEN-gated WE signal
1117 logic direct_access_cmd_gated_we;
1118 1/1 assign direct_access_cmd_gated_we = direct_access_cmd_we & direct_access_regwen_qs;
Tests: T1 T2 T3
1119 // F[rd]: 0:0
1120 prim_subreg_ext #(
1121 .DW (1)
1122 ) u_direct_access_cmd_rd (
1123 .re (1'b0),
1124 .we (direct_access_cmd_gated_we),
1125 .wd (direct_access_cmd_rd_wd),
1126 .d ('0),
1127 .qre (),
1128 .qe (direct_access_cmd_flds_we[0]),
1129 .q (reg2hw.direct_access_cmd.rd.q),
1130 .ds (),
1131 .qs ()
1132 );
1133 1/1 assign reg2hw.direct_access_cmd.rd.qe = direct_access_cmd_qe;
Tests: T1 T3 T4
1134
1135 // F[wr]: 1:1
1136 prim_subreg_ext #(
1137 .DW (1)
1138 ) u_direct_access_cmd_wr (
1139 .re (1'b0),
1140 .we (direct_access_cmd_gated_we),
1141 .wd (direct_access_cmd_wr_wd),
1142 .d ('0),
1143 .qre (),
1144 .qe (direct_access_cmd_flds_we[1]),
1145 .q (reg2hw.direct_access_cmd.wr.q),
1146 .ds (),
1147 .qs ()
1148 );
1149 1/1 assign reg2hw.direct_access_cmd.wr.qe = direct_access_cmd_qe;
Tests: T1 T3 T4
1150
1151 // F[digest]: 2:2
1152 prim_subreg_ext #(
1153 .DW (1)
1154 ) u_direct_access_cmd_digest (
1155 .re (1'b0),
1156 .we (direct_access_cmd_gated_we),
1157 .wd (direct_access_cmd_digest_wd),
1158 .d ('0),
1159 .qre (),
1160 .qe (direct_access_cmd_flds_we[2]),
1161 .q (reg2hw.direct_access_cmd.digest.q),
1162 .ds (),
1163 .qs ()
1164 );
1165 1/1 assign reg2hw.direct_access_cmd.digest.qe = direct_access_cmd_qe;
Tests: T1 T3 T4
1166
1167
1168 // R[direct_access_address]: V(False)
1169 // Create REGWEN-gated WE signal
1170 logic direct_access_address_gated_we;
1171 1/1 assign direct_access_address_gated_we = direct_access_address_we & direct_access_regwen_qs;
Tests: T1 T2 T3
1172 prim_subreg #(
1173 .DW (11),
1174 .SwAccess(prim_subreg_pkg::SwAccessRW),
1175 .RESVAL (11'h0),
1176 .Mubi (1'b0)
1177 ) u_direct_access_address (
1178 .clk_i (clk_i),
1179 .rst_ni (rst_ni),
1180
1181 // from register interface
1182 .we (direct_access_address_gated_we),
1183 .wd (direct_access_address_wd),
1184
1185 // from internal hardware
1186 .de (1'b0),
1187 .d ('0),
1188
1189 // to internal hardware
1190 .qe (),
1191 .q (reg2hw.direct_access_address.q),
1192 .ds (),
1193
1194 // to register interface (read)
1195 .qs (direct_access_address_qs)
1196 );
1197
1198
1199 // Subregister 0 of Multireg direct_access_wdata
1200 // R[direct_access_wdata_0]: V(False)
1201 // Create REGWEN-gated WE signal
1202 logic direct_access_wdata_0_gated_we;
1203 1/1 assign direct_access_wdata_0_gated_we = direct_access_wdata_0_we & direct_access_regwen_qs;
Tests: T1 T2 T3
1204 prim_subreg #(
1205 .DW (32),
1206 .SwAccess(prim_subreg_pkg::SwAccessRW),
1207 .RESVAL (32'h0),
1208 .Mubi (1'b0)
1209 ) u_direct_access_wdata_0 (
1210 .clk_i (clk_i),
1211 .rst_ni (rst_ni),
1212
1213 // from register interface
1214 .we (direct_access_wdata_0_gated_we),
1215 .wd (direct_access_wdata_0_wd),
1216
1217 // from internal hardware
1218 .de (1'b0),
1219 .d ('0),
1220
1221 // to internal hardware
1222 .qe (),
1223 .q (reg2hw.direct_access_wdata[0].q),
1224 .ds (),
1225
1226 // to register interface (read)
1227 .qs (direct_access_wdata_0_qs)
1228 );
1229
1230
1231 // Subregister 1 of Multireg direct_access_wdata
1232 // R[direct_access_wdata_1]: V(False)
1233 // Create REGWEN-gated WE signal
1234 logic direct_access_wdata_1_gated_we;
1235 1/1 assign direct_access_wdata_1_gated_we = direct_access_wdata_1_we & direct_access_regwen_qs;
Tests: T1 T2 T3
1236 prim_subreg #(
1237 .DW (32),
1238 .SwAccess(prim_subreg_pkg::SwAccessRW),
1239 .RESVAL (32'h0),
1240 .Mubi (1'b0)
1241 ) u_direct_access_wdata_1 (
1242 .clk_i (clk_i),
1243 .rst_ni (rst_ni),
1244
1245 // from register interface
1246 .we (direct_access_wdata_1_gated_we),
1247 .wd (direct_access_wdata_1_wd),
1248
1249 // from internal hardware
1250 .de (1'b0),
1251 .d ('0),
1252
1253 // to internal hardware
1254 .qe (),
1255 .q (reg2hw.direct_access_wdata[1].q),
1256 .ds (),
1257
1258 // to register interface (read)
1259 .qs (direct_access_wdata_1_qs)
1260 );
1261
1262
1263 // Subregister 0 of Multireg direct_access_rdata
1264 // R[direct_access_rdata_0]: V(True)
1265 prim_subreg_ext #(
1266 .DW (32)
1267 ) u_direct_access_rdata_0 (
1268 .re (direct_access_rdata_0_re),
1269 .we (1'b0),
1270 .wd ('0),
1271 .d (hw2reg.direct_access_rdata[0].d),
1272 .qre (),
1273 .qe (),
1274 .q (),
1275 .ds (),
1276 .qs (direct_access_rdata_0_qs)
1277 );
1278
1279
1280 // Subregister 1 of Multireg direct_access_rdata
1281 // R[direct_access_rdata_1]: V(True)
1282 prim_subreg_ext #(
1283 .DW (32)
1284 ) u_direct_access_rdata_1 (
1285 .re (direct_access_rdata_1_re),
1286 .we (1'b0),
1287 .wd ('0),
1288 .d (hw2reg.direct_access_rdata[1].d),
1289 .qre (),
1290 .qe (),
1291 .q (),
1292 .ds (),
1293 .qs (direct_access_rdata_1_qs)
1294 );
1295
1296
1297 // R[check_trigger_regwen]: V(False)
1298 prim_subreg #(
1299 .DW (1),
1300 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1301 .RESVAL (1'h1),
1302 .Mubi (1'b0)
1303 ) u_check_trigger_regwen (
1304 .clk_i (clk_i),
1305 .rst_ni (rst_ni),
1306
1307 // from register interface
1308 .we (check_trigger_regwen_we),
1309 .wd (check_trigger_regwen_wd),
1310
1311 // from internal hardware
1312 .de (1'b0),
1313 .d ('0),
1314
1315 // to internal hardware
1316 .qe (),
1317 .q (),
1318 .ds (),
1319
1320 // to register interface (read)
1321 .qs (check_trigger_regwen_qs)
1322 );
1323
1324
1325 // R[check_trigger]: V(True)
1326 logic check_trigger_qe;
1327 logic [1:0] check_trigger_flds_we;
1328 1/1 assign check_trigger_qe = &check_trigger_flds_we;
Tests: T3 T5 T8
1329 // Create REGWEN-gated WE signal
1330 logic check_trigger_gated_we;
1331 1/1 assign check_trigger_gated_we = check_trigger_we & check_trigger_regwen_qs;
Tests: T1 T2 T3
1332 // F[integrity]: 0:0
1333 prim_subreg_ext #(
1334 .DW (1)
1335 ) u_check_trigger_integrity (
1336 .re (1'b0),
1337 .we (check_trigger_gated_we),
1338 .wd (check_trigger_integrity_wd),
1339 .d ('0),
1340 .qre (),
1341 .qe (check_trigger_flds_we[0]),
1342 .q (reg2hw.check_trigger.integrity.q),
1343 .ds (),
1344 .qs ()
1345 );
1346 1/1 assign reg2hw.check_trigger.integrity.qe = check_trigger_qe;
Tests: T3 T5 T8
1347
1348 // F[consistency]: 1:1
1349 prim_subreg_ext #(
1350 .DW (1)
1351 ) u_check_trigger_consistency (
1352 .re (1'b0),
1353 .we (check_trigger_gated_we),
1354 .wd (check_trigger_consistency_wd),
1355 .d ('0),
1356 .qre (),
1357 .qe (check_trigger_flds_we[1]),
1358 .q (reg2hw.check_trigger.consistency.q),
1359 .ds (),
1360 .qs ()
1361 );
1362 1/1 assign reg2hw.check_trigger.consistency.qe = check_trigger_qe;
Tests: T3 T5 T8
1363
1364
1365 // R[check_regwen]: V(False)
1366 prim_subreg #(
1367 .DW (1),
1368 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1369 .RESVAL (1'h1),
1370 .Mubi (1'b0)
1371 ) u_check_regwen (
1372 .clk_i (clk_i),
1373 .rst_ni (rst_ni),
1374
1375 // from register interface
1376 .we (check_regwen_we),
1377 .wd (check_regwen_wd),
1378
1379 // from internal hardware
1380 .de (1'b0),
1381 .d ('0),
1382
1383 // to internal hardware
1384 .qe (),
1385 .q (),
1386 .ds (),
1387
1388 // to register interface (read)
1389 .qs (check_regwen_qs)
1390 );
1391
1392
1393 // R[check_timeout]: V(False)
1394 // Create REGWEN-gated WE signal
1395 logic check_timeout_gated_we;
1396 1/1 assign check_timeout_gated_we = check_timeout_we & check_regwen_qs;
Tests: T1 T2 T3
1397 prim_subreg #(
1398 .DW (32),
1399 .SwAccess(prim_subreg_pkg::SwAccessRW),
1400 .RESVAL (32'h0),
1401 .Mubi (1'b0)
1402 ) u_check_timeout (
1403 .clk_i (clk_i),
1404 .rst_ni (rst_ni),
1405
1406 // from register interface
1407 .we (check_timeout_gated_we),
1408 .wd (check_timeout_wd),
1409
1410 // from internal hardware
1411 .de (1'b0),
1412 .d ('0),
1413
1414 // to internal hardware
1415 .qe (),
1416 .q (reg2hw.check_timeout.q),
1417 .ds (),
1418
1419 // to register interface (read)
1420 .qs (check_timeout_qs)
1421 );
1422
1423
1424 // R[integrity_check_period]: V(False)
1425 // Create REGWEN-gated WE signal
1426 logic integrity_check_period_gated_we;
1427 1/1 assign integrity_check_period_gated_we = integrity_check_period_we & check_regwen_qs;
Tests: T1 T2 T3
1428 prim_subreg #(
1429 .DW (32),
1430 .SwAccess(prim_subreg_pkg::SwAccessRW),
1431 .RESVAL (32'h0),
1432 .Mubi (1'b0)
1433 ) u_integrity_check_period (
1434 .clk_i (clk_i),
1435 .rst_ni (rst_ni),
1436
1437 // from register interface
1438 .we (integrity_check_period_gated_we),
1439 .wd (integrity_check_period_wd),
1440
1441 // from internal hardware
1442 .de (1'b0),
1443 .d ('0),
1444
1445 // to internal hardware
1446 .qe (),
1447 .q (reg2hw.integrity_check_period.q),
1448 .ds (),
1449
1450 // to register interface (read)
1451 .qs (integrity_check_period_qs)
1452 );
1453
1454
1455 // R[consistency_check_period]: V(False)
1456 // Create REGWEN-gated WE signal
1457 logic consistency_check_period_gated_we;
1458 1/1 assign consistency_check_period_gated_we = consistency_check_period_we & check_regwen_qs;
Tests: T1 T2 T3
1459 prim_subreg #(
1460 .DW (32),
1461 .SwAccess(prim_subreg_pkg::SwAccessRW),
1462 .RESVAL (32'h0),
1463 .Mubi (1'b0)
1464 ) u_consistency_check_period (
1465 .clk_i (clk_i),
1466 .rst_ni (rst_ni),
1467
1468 // from register interface
1469 .we (consistency_check_period_gated_we),
1470 .wd (consistency_check_period_wd),
1471
1472 // from internal hardware
1473 .de (1'b0),
1474 .d ('0),
1475
1476 // to internal hardware
1477 .qe (),
1478 .q (reg2hw.consistency_check_period.q),
1479 .ds (),
1480
1481 // to register interface (read)
1482 .qs (consistency_check_period_qs)
1483 );
1484
1485
1486 // R[vendor_test_read_lock]: V(False)
1487 // Create REGWEN-gated WE signal
1488 logic vendor_test_read_lock_gated_we;
1489 1/1 assign vendor_test_read_lock_gated_we = vendor_test_read_lock_we & direct_access_regwen_qs;
Tests: T1 T2 T3
1490 prim_subreg #(
1491 .DW (1),
1492 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1493 .RESVAL (1'h1),
1494 .Mubi (1'b0)
1495 ) u_vendor_test_read_lock (
1496 .clk_i (clk_i),
1497 .rst_ni (rst_ni),
1498
1499 // from register interface
1500 .we (vendor_test_read_lock_gated_we),
1501 .wd (vendor_test_read_lock_wd),
1502
1503 // from internal hardware
1504 .de (1'b0),
1505 .d ('0),
1506
1507 // to internal hardware
1508 .qe (),
1509 .q (reg2hw.vendor_test_read_lock.q),
1510 .ds (),
1511
1512 // to register interface (read)
1513 .qs (vendor_test_read_lock_qs)
1514 );
1515
1516
1517 // R[creator_sw_cfg_read_lock]: V(False)
1518 // Create REGWEN-gated WE signal
1519 logic creator_sw_cfg_read_lock_gated_we;
1520 1/1 assign creator_sw_cfg_read_lock_gated_we = creator_sw_cfg_read_lock_we & direct_access_regwen_qs;
Tests: T1 T2 T3
1521 prim_subreg #(
1522 .DW (1),
1523 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1524 .RESVAL (1'h1),
1525 .Mubi (1'b0)
1526 ) u_creator_sw_cfg_read_lock (
1527 .clk_i (clk_i),
1528 .rst_ni (rst_ni),
1529
1530 // from register interface
1531 .we (creator_sw_cfg_read_lock_gated_we),
1532 .wd (creator_sw_cfg_read_lock_wd),
1533
1534 // from internal hardware
1535 .de (1'b0),
1536 .d ('0),
1537
1538 // to internal hardware
1539 .qe (),
1540 .q (reg2hw.creator_sw_cfg_read_lock.q),
1541 .ds (),
1542
1543 // to register interface (read)
1544 .qs (creator_sw_cfg_read_lock_qs)
1545 );
1546
1547
1548 // R[owner_sw_cfg_read_lock]: V(False)
1549 // Create REGWEN-gated WE signal
1550 logic owner_sw_cfg_read_lock_gated_we;
1551 1/1 assign owner_sw_cfg_read_lock_gated_we = owner_sw_cfg_read_lock_we & direct_access_regwen_qs;
Tests: T1 T2 T3
1552 prim_subreg #(
1553 .DW (1),
1554 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1555 .RESVAL (1'h1),
1556 .Mubi (1'b0)
1557 ) u_owner_sw_cfg_read_lock (
1558 .clk_i (clk_i),
1559 .rst_ni (rst_ni),
1560
1561 // from register interface
1562 .we (owner_sw_cfg_read_lock_gated_we),
1563 .wd (owner_sw_cfg_read_lock_wd),
1564
1565 // from internal hardware
1566 .de (1'b0),
1567 .d ('0),
1568
1569 // to internal hardware
1570 .qe (),
1571 .q (reg2hw.owner_sw_cfg_read_lock.q),
1572 .ds (),
1573
1574 // to register interface (read)
1575 .qs (owner_sw_cfg_read_lock_qs)
1576 );
1577
1578
1579 // R[rot_creator_auth_codesign_read_lock]: V(False)
1580 // Create REGWEN-gated WE signal
1581 logic rot_creator_auth_codesign_read_lock_gated_we;
1582 1/1 assign rot_creator_auth_codesign_read_lock_gated_we =
Tests: T1 T2 T3
1583 rot_creator_auth_codesign_read_lock_we & direct_access_regwen_qs;
1584 prim_subreg #(
1585 .DW (1),
1586 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1587 .RESVAL (1'h1),
1588 .Mubi (1'b0)
1589 ) u_rot_creator_auth_codesign_read_lock (
1590 .clk_i (clk_i),
1591 .rst_ni (rst_ni),
1592
1593 // from register interface
1594 .we (rot_creator_auth_codesign_read_lock_gated_we),
1595 .wd (rot_creator_auth_codesign_read_lock_wd),
1596
1597 // from internal hardware
1598 .de (1'b0),
1599 .d ('0),
1600
1601 // to internal hardware
1602 .qe (),
1603 .q (reg2hw.rot_creator_auth_codesign_read_lock.q),
1604 .ds (),
1605
1606 // to register interface (read)
1607 .qs (rot_creator_auth_codesign_read_lock_qs)
1608 );
1609
1610
1611 // R[rot_creator_auth_state_read_lock]: V(False)
1612 // Create REGWEN-gated WE signal
1613 logic rot_creator_auth_state_read_lock_gated_we;
1614 1/1 assign rot_creator_auth_state_read_lock_gated_we =
Tests: T1 T2 T3
1615 rot_creator_auth_state_read_lock_we & direct_access_regwen_qs;
1616 prim_subreg #(
1617 .DW (1),
1618 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1619 .RESVAL (1'h1),
1620 .Mubi (1'b0)
1621 ) u_rot_creator_auth_state_read_lock (
1622 .clk_i (clk_i),
1623 .rst_ni (rst_ni),
1624
1625 // from register interface
1626 .we (rot_creator_auth_state_read_lock_gated_we),
1627 .wd (rot_creator_auth_state_read_lock_wd),
1628
1629 // from internal hardware
1630 .de (1'b0),
1631 .d ('0),
1632
1633 // to internal hardware
1634 .qe (),
1635 .q (reg2hw.rot_creator_auth_state_read_lock.q),
1636 .ds (),
1637
1638 // to register interface (read)
1639 .qs (rot_creator_auth_state_read_lock_qs)
1640 );
1641
1642
1643 // Subregister 0 of Multireg vendor_test_digest
1644 // R[vendor_test_digest_0]: V(True)
1645 prim_subreg_ext #(
1646 .DW (32)
1647 ) u_vendor_test_digest_0 (
1648 .re (vendor_test_digest_0_re),
1649 .we (1'b0),
1650 .wd ('0),
1651 .d (hw2reg.vendor_test_digest[0].d),
1652 .qre (),
1653 .qe (),
1654 .q (),
1655 .ds (),
1656 .qs (vendor_test_digest_0_qs)
1657 );
1658
1659
1660 // Subregister 1 of Multireg vendor_test_digest
1661 // R[vendor_test_digest_1]: V(True)
1662 prim_subreg_ext #(
1663 .DW (32)
1664 ) u_vendor_test_digest_1 (
1665 .re (vendor_test_digest_1_re),
1666 .we (1'b0),
1667 .wd ('0),
1668 .d (hw2reg.vendor_test_digest[1].d),
1669 .qre (),
1670 .qe (),
1671 .q (),
1672 .ds (),
1673 .qs (vendor_test_digest_1_qs)
1674 );
1675
1676
1677 // Subregister 0 of Multireg creator_sw_cfg_digest
1678 // R[creator_sw_cfg_digest_0]: V(True)
1679 prim_subreg_ext #(
1680 .DW (32)
1681 ) u_creator_sw_cfg_digest_0 (
1682 .re (creator_sw_cfg_digest_0_re),
1683 .we (1'b0),
1684 .wd ('0),
1685 .d (hw2reg.creator_sw_cfg_digest[0].d),
1686 .qre (),
1687 .qe (),
1688 .q (),
1689 .ds (),
1690 .qs (creator_sw_cfg_digest_0_qs)
1691 );
1692
1693
1694 // Subregister 1 of Multireg creator_sw_cfg_digest
1695 // R[creator_sw_cfg_digest_1]: V(True)
1696 prim_subreg_ext #(
1697 .DW (32)
1698 ) u_creator_sw_cfg_digest_1 (
1699 .re (creator_sw_cfg_digest_1_re),
1700 .we (1'b0),
1701 .wd ('0),
1702 .d (hw2reg.creator_sw_cfg_digest[1].d),
1703 .qre (),
1704 .qe (),
1705 .q (),
1706 .ds (),
1707 .qs (creator_sw_cfg_digest_1_qs)
1708 );
1709
1710
1711 // Subregister 0 of Multireg owner_sw_cfg_digest
1712 // R[owner_sw_cfg_digest_0]: V(True)
1713 prim_subreg_ext #(
1714 .DW (32)
1715 ) u_owner_sw_cfg_digest_0 (
1716 .re (owner_sw_cfg_digest_0_re),
1717 .we (1'b0),
1718 .wd ('0),
1719 .d (hw2reg.owner_sw_cfg_digest[0].d),
1720 .qre (),
1721 .qe (),
1722 .q (),
1723 .ds (),
1724 .qs (owner_sw_cfg_digest_0_qs)
1725 );
1726
1727
1728 // Subregister 1 of Multireg owner_sw_cfg_digest
1729 // R[owner_sw_cfg_digest_1]: V(True)
1730 prim_subreg_ext #(
1731 .DW (32)
1732 ) u_owner_sw_cfg_digest_1 (
1733 .re (owner_sw_cfg_digest_1_re),
1734 .we (1'b0),
1735 .wd ('0),
1736 .d (hw2reg.owner_sw_cfg_digest[1].d),
1737 .qre (),
1738 .qe (),
1739 .q (),
1740 .ds (),
1741 .qs (owner_sw_cfg_digest_1_qs)
1742 );
1743
1744
1745 // Subregister 0 of Multireg rot_creator_auth_codesign_digest
1746 // R[rot_creator_auth_codesign_digest_0]: V(True)
1747 prim_subreg_ext #(
1748 .DW (32)
1749 ) u_rot_creator_auth_codesign_digest_0 (
1750 .re (rot_creator_auth_codesign_digest_0_re),
1751 .we (1'b0),
1752 .wd ('0),
1753 .d (hw2reg.rot_creator_auth_codesign_digest[0].d),
1754 .qre (),
1755 .qe (),
1756 .q (),
1757 .ds (),
1758 .qs (rot_creator_auth_codesign_digest_0_qs)
1759 );
1760
1761
1762 // Subregister 1 of Multireg rot_creator_auth_codesign_digest
1763 // R[rot_creator_auth_codesign_digest_1]: V(True)
1764 prim_subreg_ext #(
1765 .DW (32)
1766 ) u_rot_creator_auth_codesign_digest_1 (
1767 .re (rot_creator_auth_codesign_digest_1_re),
1768 .we (1'b0),
1769 .wd ('0),
1770 .d (hw2reg.rot_creator_auth_codesign_digest[1].d),
1771 .qre (),
1772 .qe (),
1773 .q (),
1774 .ds (),
1775 .qs (rot_creator_auth_codesign_digest_1_qs)
1776 );
1777
1778
1779 // Subregister 0 of Multireg rot_creator_auth_state_digest
1780 // R[rot_creator_auth_state_digest_0]: V(True)
1781 prim_subreg_ext #(
1782 .DW (32)
1783 ) u_rot_creator_auth_state_digest_0 (
1784 .re (rot_creator_auth_state_digest_0_re),
1785 .we (1'b0),
1786 .wd ('0),
1787 .d (hw2reg.rot_creator_auth_state_digest[0].d),
1788 .qre (),
1789 .qe (),
1790 .q (),
1791 .ds (),
1792 .qs (rot_creator_auth_state_digest_0_qs)
1793 );
1794
1795
1796 // Subregister 1 of Multireg rot_creator_auth_state_digest
1797 // R[rot_creator_auth_state_digest_1]: V(True)
1798 prim_subreg_ext #(
1799 .DW (32)
1800 ) u_rot_creator_auth_state_digest_1 (
1801 .re (rot_creator_auth_state_digest_1_re),
1802 .we (1'b0),
1803 .wd ('0),
1804 .d (hw2reg.rot_creator_auth_state_digest[1].d),
1805 .qre (),
1806 .qe (),
1807 .q (),
1808 .ds (),
1809 .qs (rot_creator_auth_state_digest_1_qs)
1810 );
1811
1812
1813 // Subregister 0 of Multireg hw_cfg0_digest
1814 // R[hw_cfg0_digest_0]: V(True)
1815 prim_subreg_ext #(
1816 .DW (32)
1817 ) u_hw_cfg0_digest_0 (
1818 .re (hw_cfg0_digest_0_re),
1819 .we (1'b0),
1820 .wd ('0),
1821 .d (hw2reg.hw_cfg0_digest[0].d),
1822 .qre (),
1823 .qe (),
1824 .q (),
1825 .ds (),
1826 .qs (hw_cfg0_digest_0_qs)
1827 );
1828
1829
1830 // Subregister 1 of Multireg hw_cfg0_digest
1831 // R[hw_cfg0_digest_1]: V(True)
1832 prim_subreg_ext #(
1833 .DW (32)
1834 ) u_hw_cfg0_digest_1 (
1835 .re (hw_cfg0_digest_1_re),
1836 .we (1'b0),
1837 .wd ('0),
1838 .d (hw2reg.hw_cfg0_digest[1].d),
1839 .qre (),
1840 .qe (),
1841 .q (),
1842 .ds (),
1843 .qs (hw_cfg0_digest_1_qs)
1844 );
1845
1846
1847 // Subregister 0 of Multireg hw_cfg1_digest
1848 // R[hw_cfg1_digest_0]: V(True)
1849 prim_subreg_ext #(
1850 .DW (32)
1851 ) u_hw_cfg1_digest_0 (
1852 .re (hw_cfg1_digest_0_re),
1853 .we (1'b0),
1854 .wd ('0),
1855 .d (hw2reg.hw_cfg1_digest[0].d),
1856 .qre (),
1857 .qe (),
1858 .q (),
1859 .ds (),
1860 .qs (hw_cfg1_digest_0_qs)
1861 );
1862
1863
1864 // Subregister 1 of Multireg hw_cfg1_digest
1865 // R[hw_cfg1_digest_1]: V(True)
1866 prim_subreg_ext #(
1867 .DW (32)
1868 ) u_hw_cfg1_digest_1 (
1869 .re (hw_cfg1_digest_1_re),
1870 .we (1'b0),
1871 .wd ('0),
1872 .d (hw2reg.hw_cfg1_digest[1].d),
1873 .qre (),
1874 .qe (),
1875 .q (),
1876 .ds (),
1877 .qs (hw_cfg1_digest_1_qs)
1878 );
1879
1880
1881 // Subregister 0 of Multireg secret0_digest
1882 // R[secret0_digest_0]: V(True)
1883 prim_subreg_ext #(
1884 .DW (32)
1885 ) u_secret0_digest_0 (
1886 .re (secret0_digest_0_re),
1887 .we (1'b0),
1888 .wd ('0),
1889 .d (hw2reg.secret0_digest[0].d),
1890 .qre (),
1891 .qe (),
1892 .q (),
1893 .ds (),
1894 .qs (secret0_digest_0_qs)
1895 );
1896
1897
1898 // Subregister 1 of Multireg secret0_digest
1899 // R[secret0_digest_1]: V(True)
1900 prim_subreg_ext #(
1901 .DW (32)
1902 ) u_secret0_digest_1 (
1903 .re (secret0_digest_1_re),
1904 .we (1'b0),
1905 .wd ('0),
1906 .d (hw2reg.secret0_digest[1].d),
1907 .qre (),
1908 .qe (),
1909 .q (),
1910 .ds (),
1911 .qs (secret0_digest_1_qs)
1912 );
1913
1914
1915 // Subregister 0 of Multireg secret1_digest
1916 // R[secret1_digest_0]: V(True)
1917 prim_subreg_ext #(
1918 .DW (32)
1919 ) u_secret1_digest_0 (
1920 .re (secret1_digest_0_re),
1921 .we (1'b0),
1922 .wd ('0),
1923 .d (hw2reg.secret1_digest[0].d),
1924 .qre (),
1925 .qe (),
1926 .q (),
1927 .ds (),
1928 .qs (secret1_digest_0_qs)
1929 );
1930
1931
1932 // Subregister 1 of Multireg secret1_digest
1933 // R[secret1_digest_1]: V(True)
1934 prim_subreg_ext #(
1935 .DW (32)
1936 ) u_secret1_digest_1 (
1937 .re (secret1_digest_1_re),
1938 .we (1'b0),
1939 .wd ('0),
1940 .d (hw2reg.secret1_digest[1].d),
1941 .qre (),
1942 .qe (),
1943 .q (),
1944 .ds (),
1945 .qs (secret1_digest_1_qs)
1946 );
1947
1948
1949 // Subregister 0 of Multireg secret2_digest
1950 // R[secret2_digest_0]: V(True)
1951 prim_subreg_ext #(
1952 .DW (32)
1953 ) u_secret2_digest_0 (
1954 .re (secret2_digest_0_re),
1955 .we (1'b0),
1956 .wd ('0),
1957 .d (hw2reg.secret2_digest[0].d),
1958 .qre (),
1959 .qe (),
1960 .q (),
1961 .ds (),
1962 .qs (secret2_digest_0_qs)
1963 );
1964
1965
1966 // Subregister 1 of Multireg secret2_digest
1967 // R[secret2_digest_1]: V(True)
1968 prim_subreg_ext #(
1969 .DW (32)
1970 ) u_secret2_digest_1 (
1971 .re (secret2_digest_1_re),
1972 .we (1'b0),
1973 .wd ('0),
1974 .d (hw2reg.secret2_digest[1].d),
1975 .qre (),
1976 .qe (),
1977 .q (),
1978 .ds (),
1979 .qs (secret2_digest_1_qs)
1980 );
1981
1982
1983
1984 logic [55:0] addr_hit;
1985 always_comb begin
1986 1/1 addr_hit = '0;
Tests: T1 T2 T3
1987 1/1 addr_hit[ 0] = (reg_addr == OTP_CTRL_INTR_STATE_OFFSET);
Tests: T1 T2 T3
1988 1/1 addr_hit[ 1] = (reg_addr == OTP_CTRL_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
1989 1/1 addr_hit[ 2] = (reg_addr == OTP_CTRL_INTR_TEST_OFFSET);
Tests: T1 T2 T3
1990 1/1 addr_hit[ 3] = (reg_addr == OTP_CTRL_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
1991 1/1 addr_hit[ 4] = (reg_addr == OTP_CTRL_STATUS_OFFSET);
Tests: T1 T2 T3
1992 1/1 addr_hit[ 5] = (reg_addr == OTP_CTRL_ERR_CODE_0_OFFSET);
Tests: T1 T2 T3
1993 1/1 addr_hit[ 6] = (reg_addr == OTP_CTRL_ERR_CODE_1_OFFSET);
Tests: T1 T2 T3
1994 1/1 addr_hit[ 7] = (reg_addr == OTP_CTRL_ERR_CODE_2_OFFSET);
Tests: T1 T2 T3
1995 1/1 addr_hit[ 8] = (reg_addr == OTP_CTRL_ERR_CODE_3_OFFSET);
Tests: T1 T2 T3
1996 1/1 addr_hit[ 9] = (reg_addr == OTP_CTRL_ERR_CODE_4_OFFSET);
Tests: T1 T2 T3
1997 1/1 addr_hit[10] = (reg_addr == OTP_CTRL_ERR_CODE_5_OFFSET);
Tests: T1 T2 T3
1998 1/1 addr_hit[11] = (reg_addr == OTP_CTRL_ERR_CODE_6_OFFSET);
Tests: T1 T2 T3
1999 1/1 addr_hit[12] = (reg_addr == OTP_CTRL_ERR_CODE_7_OFFSET);
Tests: T1 T2 T3
2000 1/1 addr_hit[13] = (reg_addr == OTP_CTRL_ERR_CODE_8_OFFSET);
Tests: T1 T2 T3
2001 1/1 addr_hit[14] = (reg_addr == OTP_CTRL_ERR_CODE_9_OFFSET);
Tests: T1 T2 T3
2002 1/1 addr_hit[15] = (reg_addr == OTP_CTRL_ERR_CODE_10_OFFSET);
Tests: T1 T2 T3
2003 1/1 addr_hit[16] = (reg_addr == OTP_CTRL_ERR_CODE_11_OFFSET);
Tests: T1 T2 T3
2004 1/1 addr_hit[17] = (reg_addr == OTP_CTRL_ERR_CODE_12_OFFSET);
Tests: T1 T2 T3
2005 1/1 addr_hit[18] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET);
Tests: T1 T2 T3
2006 1/1 addr_hit[19] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET);
Tests: T1 T2 T3
2007 1/1 addr_hit[20] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET);
Tests: T1 T2 T3
2008 1/1 addr_hit[21] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET);
Tests: T1 T2 T3
2009 1/1 addr_hit[22] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET);
Tests: T1 T2 T3
2010 1/1 addr_hit[23] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET);
Tests: T1 T2 T3
2011 1/1 addr_hit[24] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET);
Tests: T1 T2 T3
2012 1/1 addr_hit[25] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET);
Tests: T1 T2 T3
2013 1/1 addr_hit[26] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_OFFSET);
Tests: T1 T2 T3
2014 1/1 addr_hit[27] = (reg_addr == OTP_CTRL_CHECK_REGWEN_OFFSET);
Tests: T1 T2 T3
2015 1/1 addr_hit[28] = (reg_addr == OTP_CTRL_CHECK_TIMEOUT_OFFSET);
Tests: T1 T2 T3
2016 1/1 addr_hit[29] = (reg_addr == OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET);
Tests: T1 T2 T3
2017 1/1 addr_hit[30] = (reg_addr == OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET);
Tests: T1 T2 T3
2018 1/1 addr_hit[31] = (reg_addr == OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET);
Tests: T1 T2 T3
2019 1/1 addr_hit[32] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET);
Tests: T1 T2 T3
2020 1/1 addr_hit[33] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET);
Tests: T1 T2 T3
2021 1/1 addr_hit[34] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK_OFFSET);
Tests: T1 T2 T3
2022 1/1 addr_hit[35] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_STATE_READ_LOCK_OFFSET);
Tests: T1 T2 T3
2023 1/1 addr_hit[36] = (reg_addr == OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET);
Tests: T1 T2 T3
2024 1/1 addr_hit[37] = (reg_addr == OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET);
Tests: T1 T2 T3
2025 1/1 addr_hit[38] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET);
Tests: T1 T2 T3
2026 1/1 addr_hit[39] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET);
Tests: T1 T2 T3
2027 1/1 addr_hit[40] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET);
Tests: T1 T2 T3
2028 1/1 addr_hit[41] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET);
Tests: T1 T2 T3
2029 1/1 addr_hit[42] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0_OFFSET);
Tests: T1 T2 T3
2030 1/1 addr_hit[43] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_1_OFFSET);
Tests: T1 T2 T3
2031 1/1 addr_hit[44] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0_OFFSET);
Tests: T1 T2 T3
2032 1/1 addr_hit[45] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_1_OFFSET);
Tests: T1 T2 T3
2033 1/1 addr_hit[46] = (reg_addr == OTP_CTRL_HW_CFG0_DIGEST_0_OFFSET);
Tests: T1 T2 T3
2034 1/1 addr_hit[47] = (reg_addr == OTP_CTRL_HW_CFG0_DIGEST_1_OFFSET);
Tests: T1 T2 T3
2035 1/1 addr_hit[48] = (reg_addr == OTP_CTRL_HW_CFG1_DIGEST_0_OFFSET);
Tests: T1 T2 T3
2036 1/1 addr_hit[49] = (reg_addr == OTP_CTRL_HW_CFG1_DIGEST_1_OFFSET);
Tests: T1 T2 T3
2037 1/1 addr_hit[50] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_0_OFFSET);
Tests: T1 T2 T3
2038 1/1 addr_hit[51] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_1_OFFSET);
Tests: T1 T2 T3
2039 1/1 addr_hit[52] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_0_OFFSET);
Tests: T1 T2 T3
2040 1/1 addr_hit[53] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_1_OFFSET);
Tests: T1 T2 T3
2041 1/1 addr_hit[54] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_0_OFFSET);
Tests: T1 T2 T3
2042 1/1 addr_hit[55] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_1_OFFSET);
Tests: T1 T2 T3
2043 end
2044
2045 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
2046
2047 // Check sub-word write is permitted
2048 always_comb begin
2049 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
2050 ((addr_hit[ 0] & (|(OTP_CTRL_CORE_PERMIT[ 0] & ~reg_be))) |
2051 (addr_hit[ 1] & (|(OTP_CTRL_CORE_PERMIT[ 1] & ~reg_be))) |
2052 (addr_hit[ 2] & (|(OTP_CTRL_CORE_PERMIT[ 2] & ~reg_be))) |
2053 (addr_hit[ 3] & (|(OTP_CTRL_CORE_PERMIT[ 3] & ~reg_be))) |
2054 (addr_hit[ 4] & (|(OTP_CTRL_CORE_PERMIT[ 4] & ~reg_be))) |
2055 (addr_hit[ 5] & (|(OTP_CTRL_CORE_PERMIT[ 5] & ~reg_be))) |
2056 (addr_hit[ 6] & (|(OTP_CTRL_CORE_PERMIT[ 6] & ~reg_be))) |
2057 (addr_hit[ 7] & (|(OTP_CTRL_CORE_PERMIT[ 7] & ~reg_be))) |
2058 (addr_hit[ 8] & (|(OTP_CTRL_CORE_PERMIT[ 8] & ~reg_be))) |
2059 (addr_hit[ 9] & (|(OTP_CTRL_CORE_PERMIT[ 9] & ~reg_be))) |
2060 (addr_hit[10] & (|(OTP_CTRL_CORE_PERMIT[10] & ~reg_be))) |
2061 (addr_hit[11] & (|(OTP_CTRL_CORE_PERMIT[11] & ~reg_be))) |
2062 (addr_hit[12] & (|(OTP_CTRL_CORE_PERMIT[12] & ~reg_be))) |
2063 (addr_hit[13] & (|(OTP_CTRL_CORE_PERMIT[13] & ~reg_be))) |
2064 (addr_hit[14] & (|(OTP_CTRL_CORE_PERMIT[14] & ~reg_be))) |
2065 (addr_hit[15] & (|(OTP_CTRL_CORE_PERMIT[15] & ~reg_be))) |
2066 (addr_hit[16] & (|(OTP_CTRL_CORE_PERMIT[16] & ~reg_be))) |
2067 (addr_hit[17] & (|(OTP_CTRL_CORE_PERMIT[17] & ~reg_be))) |
2068 (addr_hit[18] & (|(OTP_CTRL_CORE_PERMIT[18] & ~reg_be))) |
2069 (addr_hit[19] & (|(OTP_CTRL_CORE_PERMIT[19] & ~reg_be))) |
2070 (addr_hit[20] & (|(OTP_CTRL_CORE_PERMIT[20] & ~reg_be))) |
2071 (addr_hit[21] & (|(OTP_CTRL_CORE_PERMIT[21] & ~reg_be))) |
2072 (addr_hit[22] & (|(OTP_CTRL_CORE_PERMIT[22] & ~reg_be))) |
2073 (addr_hit[23] & (|(OTP_CTRL_CORE_PERMIT[23] & ~reg_be))) |
2074 (addr_hit[24] & (|(OTP_CTRL_CORE_PERMIT[24] & ~reg_be))) |
2075 (addr_hit[25] & (|(OTP_CTRL_CORE_PERMIT[25] & ~reg_be))) |
2076 (addr_hit[26] & (|(OTP_CTRL_CORE_PERMIT[26] & ~reg_be))) |
2077 (addr_hit[27] & (|(OTP_CTRL_CORE_PERMIT[27] & ~reg_be))) |
2078 (addr_hit[28] & (|(OTP_CTRL_CORE_PERMIT[28] & ~reg_be))) |
2079 (addr_hit[29] & (|(OTP_CTRL_CORE_PERMIT[29] & ~reg_be))) |
2080 (addr_hit[30] & (|(OTP_CTRL_CORE_PERMIT[30] & ~reg_be))) |
2081 (addr_hit[31] & (|(OTP_CTRL_CORE_PERMIT[31] & ~reg_be))) |
2082 (addr_hit[32] & (|(OTP_CTRL_CORE_PERMIT[32] & ~reg_be))) |
2083 (addr_hit[33] & (|(OTP_CTRL_CORE_PERMIT[33] & ~reg_be))) |
2084 (addr_hit[34] & (|(OTP_CTRL_CORE_PERMIT[34] & ~reg_be))) |
2085 (addr_hit[35] & (|(OTP_CTRL_CORE_PERMIT[35] & ~reg_be))) |
2086 (addr_hit[36] & (|(OTP_CTRL_CORE_PERMIT[36] & ~reg_be))) |
2087 (addr_hit[37] & (|(OTP_CTRL_CORE_PERMIT[37] & ~reg_be))) |
2088 (addr_hit[38] & (|(OTP_CTRL_CORE_PERMIT[38] & ~reg_be))) |
2089 (addr_hit[39] & (|(OTP_CTRL_CORE_PERMIT[39] & ~reg_be))) |
2090 (addr_hit[40] & (|(OTP_CTRL_CORE_PERMIT[40] & ~reg_be))) |
2091 (addr_hit[41] & (|(OTP_CTRL_CORE_PERMIT[41] & ~reg_be))) |
2092 (addr_hit[42] & (|(OTP_CTRL_CORE_PERMIT[42] & ~reg_be))) |
2093 (addr_hit[43] & (|(OTP_CTRL_CORE_PERMIT[43] & ~reg_be))) |
2094 (addr_hit[44] & (|(OTP_CTRL_CORE_PERMIT[44] & ~reg_be))) |
2095 (addr_hit[45] & (|(OTP_CTRL_CORE_PERMIT[45] & ~reg_be))) |
2096 (addr_hit[46] & (|(OTP_CTRL_CORE_PERMIT[46] & ~reg_be))) |
2097 (addr_hit[47] & (|(OTP_CTRL_CORE_PERMIT[47] & ~reg_be))) |
2098 (addr_hit[48] & (|(OTP_CTRL_CORE_PERMIT[48] & ~reg_be))) |
2099 (addr_hit[49] & (|(OTP_CTRL_CORE_PERMIT[49] & ~reg_be))) |
2100 (addr_hit[50] & (|(OTP_CTRL_CORE_PERMIT[50] & ~reg_be))) |
2101 (addr_hit[51] & (|(OTP_CTRL_CORE_PERMIT[51] & ~reg_be))) |
2102 (addr_hit[52] & (|(OTP_CTRL_CORE_PERMIT[52] & ~reg_be))) |
2103 (addr_hit[53] & (|(OTP_CTRL_CORE_PERMIT[53] & ~reg_be))) |
2104 (addr_hit[54] & (|(OTP_CTRL_CORE_PERMIT[54] & ~reg_be))) |
2105 (addr_hit[55] & (|(OTP_CTRL_CORE_PERMIT[55] & ~reg_be)))));
2106 end
2107
2108 // Generate write-enables
2109 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
2110
2111 1/1 assign intr_state_otp_operation_done_wd = reg_wdata[0];
Tests: T1 T2 T3
2112
2113 1/1 assign intr_state_otp_error_wd = reg_wdata[1];
Tests: T1 T2 T3
2114 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
2115
2116 1/1 assign intr_enable_otp_operation_done_wd = reg_wdata[0];
Tests: T1 T2 T3
2117
2118 1/1 assign intr_enable_otp_error_wd = reg_wdata[1];
Tests: T1 T2 T3
2119 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
2120
2121 1/1 assign intr_test_otp_operation_done_wd = reg_wdata[0];
Tests: T1 T2 T3
2122
2123 1/1 assign intr_test_otp_error_wd = reg_wdata[1];
Tests: T1 T2 T3
2124 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
2125
2126 1/1 assign alert_test_fatal_macro_error_wd = reg_wdata[0];
Tests: T1 T2 T3
2127
2128 1/1 assign alert_test_fatal_check_error_wd = reg_wdata[1];
Tests: T1 T2 T3
2129
2130 1/1 assign alert_test_fatal_bus_integ_error_wd = reg_wdata[2];
Tests: T1 T2 T3
2131
2132 1/1 assign alert_test_fatal_prim_otp_alert_wd = reg_wdata[3];
Tests: T1 T2 T3
2133
2134 1/1 assign alert_test_recov_prim_otp_alert_wd = reg_wdata[4];
Tests: T1 T2 T3
2135 1/1 assign status_re = addr_hit[4] & reg_re & !reg_error;
Tests: T1 T2 T3
2136 1/1 assign err_code_0_re = addr_hit[5] & reg_re & !reg_error;
Tests: T1 T2 T3
2137 1/1 assign err_code_1_re = addr_hit[6] & reg_re & !reg_error;
Tests: T1 T2 T3
2138 1/1 assign err_code_2_re = addr_hit[7] & reg_re & !reg_error;
Tests: T1 T2 T3
2139 1/1 assign err_code_3_re = addr_hit[8] & reg_re & !reg_error;
Tests: T1 T2 T3
2140 1/1 assign err_code_4_re = addr_hit[9] & reg_re & !reg_error;
Tests: T1 T2 T3
2141 1/1 assign err_code_5_re = addr_hit[10] & reg_re & !reg_error;
Tests: T1 T2 T3
2142 1/1 assign err_code_6_re = addr_hit[11] & reg_re & !reg_error;
Tests: T1 T2 T3
2143 1/1 assign err_code_7_re = addr_hit[12] & reg_re & !reg_error;
Tests: T1 T2 T3
2144 1/1 assign err_code_8_re = addr_hit[13] & reg_re & !reg_error;
Tests: T1 T2 T3
2145 1/1 assign err_code_9_re = addr_hit[14] & reg_re & !reg_error;
Tests: T1 T2 T3
2146 1/1 assign err_code_10_re = addr_hit[15] & reg_re & !reg_error;
Tests: T1 T2 T3
2147 1/1 assign err_code_11_re = addr_hit[16] & reg_re & !reg_error;
Tests: T1 T2 T3
2148 1/1 assign err_code_12_re = addr_hit[17] & reg_re & !reg_error;
Tests: T1 T2 T3
2149 1/1 assign direct_access_regwen_re = addr_hit[18] & reg_re & !reg_error;
Tests: T1 T2 T3
2150 1/1 assign direct_access_regwen_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
2151
2152 1/1 assign direct_access_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
2153 1/1 assign direct_access_cmd_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
2154
2155 1/1 assign direct_access_cmd_rd_wd = reg_wdata[0];
Tests: T1 T2 T3
2156
2157 1/1 assign direct_access_cmd_wr_wd = reg_wdata[1];
Tests: T1 T2 T3
2158
2159 1/1 assign direct_access_cmd_digest_wd = reg_wdata[2];
Tests: T1 T2 T3
2160 1/1 assign direct_access_address_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
2161
2162 1/1 assign direct_access_address_wd = reg_wdata[10:0];
Tests: T1 T2 T3
2163 1/1 assign direct_access_wdata_0_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
2164
2165 1/1 assign direct_access_wdata_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2166 1/1 assign direct_access_wdata_1_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T3
2167
2168 1/1 assign direct_access_wdata_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2169 1/1 assign direct_access_rdata_0_re = addr_hit[23] & reg_re & !reg_error;
Tests: T1 T2 T3
2170 1/1 assign direct_access_rdata_1_re = addr_hit[24] & reg_re & !reg_error;
Tests: T1 T2 T3
2171 1/1 assign check_trigger_regwen_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
2172
2173 1/1 assign check_trigger_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
2174 1/1 assign check_trigger_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
2175
2176 1/1 assign check_trigger_integrity_wd = reg_wdata[0];
Tests: T1 T2 T3
2177
2178 1/1 assign check_trigger_consistency_wd = reg_wdata[1];
Tests: T1 T2 T3
2179 1/1 assign check_regwen_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T3
2180
2181 1/1 assign check_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
2182 1/1 assign check_timeout_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T2 T3
2183
2184 1/1 assign check_timeout_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2185 1/1 assign integrity_check_period_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T2 T3
2186
2187 1/1 assign integrity_check_period_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2188 1/1 assign consistency_check_period_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T2 T3
2189
2190 1/1 assign consistency_check_period_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2191 1/1 assign vendor_test_read_lock_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T2 T3
2192
2193 1/1 assign vendor_test_read_lock_wd = reg_wdata[0];
Tests: T1 T2 T3
2194 1/1 assign creator_sw_cfg_read_lock_we = addr_hit[32] & reg_we & !reg_error;
Tests: T1 T2 T3
2195
2196 1/1 assign creator_sw_cfg_read_lock_wd = reg_wdata[0];
Tests: T1 T2 T3
2197 1/1 assign owner_sw_cfg_read_lock_we = addr_hit[33] & reg_we & !reg_error;
Tests: T1 T2 T3
2198
2199 1/1 assign owner_sw_cfg_read_lock_wd = reg_wdata[0];
Tests: T1 T2 T3
2200 1/1 assign rot_creator_auth_codesign_read_lock_we = addr_hit[34] & reg_we & !reg_error;
Tests: T1 T2 T3
2201
2202 1/1 assign rot_creator_auth_codesign_read_lock_wd = reg_wdata[0];
Tests: T1 T2 T3
2203 1/1 assign rot_creator_auth_state_read_lock_we = addr_hit[35] & reg_we & !reg_error;
Tests: T1 T2 T3
2204
2205 1/1 assign rot_creator_auth_state_read_lock_wd = reg_wdata[0];
Tests: T1 T2 T3
2206 1/1 assign vendor_test_digest_0_re = addr_hit[36] & reg_re & !reg_error;
Tests: T1 T2 T3
2207 1/1 assign vendor_test_digest_1_re = addr_hit[37] & reg_re & !reg_error;
Tests: T1 T2 T3
2208 1/1 assign creator_sw_cfg_digest_0_re = addr_hit[38] & reg_re & !reg_error;
Tests: T1 T2 T3
2209 1/1 assign creator_sw_cfg_digest_1_re = addr_hit[39] & reg_re & !reg_error;
Tests: T1 T2 T3
2210 1/1 assign owner_sw_cfg_digest_0_re = addr_hit[40] & reg_re & !reg_error;
Tests: T1 T2 T3
2211 1/1 assign owner_sw_cfg_digest_1_re = addr_hit[41] & reg_re & !reg_error;
Tests: T1 T2 T3
2212 1/1 assign rot_creator_auth_codesign_digest_0_re = addr_hit[42] & reg_re & !reg_error;
Tests: T1 T2 T3
2213 1/1 assign rot_creator_auth_codesign_digest_1_re = addr_hit[43] & reg_re & !reg_error;
Tests: T1 T2 T3
2214 1/1 assign rot_creator_auth_state_digest_0_re = addr_hit[44] & reg_re & !reg_error;
Tests: T1 T2 T3
2215 1/1 assign rot_creator_auth_state_digest_1_re = addr_hit[45] & reg_re & !reg_error;
Tests: T1 T2 T3
2216 1/1 assign hw_cfg0_digest_0_re = addr_hit[46] & reg_re & !reg_error;
Tests: T1 T2 T3
2217 1/1 assign hw_cfg0_digest_1_re = addr_hit[47] & reg_re & !reg_error;
Tests: T1 T2 T3
2218 1/1 assign hw_cfg1_digest_0_re = addr_hit[48] & reg_re & !reg_error;
Tests: T1 T2 T3
2219 1/1 assign hw_cfg1_digest_1_re = addr_hit[49] & reg_re & !reg_error;
Tests: T1 T2 T3
2220 1/1 assign secret0_digest_0_re = addr_hit[50] & reg_re & !reg_error;
Tests: T1 T2 T3
2221 1/1 assign secret0_digest_1_re = addr_hit[51] & reg_re & !reg_error;
Tests: T1 T2 T3
2222 1/1 assign secret1_digest_0_re = addr_hit[52] & reg_re & !reg_error;
Tests: T1 T2 T3
2223 1/1 assign secret1_digest_1_re = addr_hit[53] & reg_re & !reg_error;
Tests: T1 T2 T3
2224 1/1 assign secret2_digest_0_re = addr_hit[54] & reg_re & !reg_error;
Tests: T1 T2 T3
2225 1/1 assign secret2_digest_1_re = addr_hit[55] & reg_re & !reg_error;
Tests: T1 T2 T3
2226
2227 // Assign write-enables to checker logic vector.
2228 always_comb begin
2229 1/1 reg_we_check = '0;
Tests: T1 T2 T3
2230 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T3
2231 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T3
2232 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T3
2233 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T2 T3
2234 1/1 reg_we_check[4] = 1'b0;
Tests: T1 T2 T3
2235 1/1 reg_we_check[5] = 1'b0;
Tests: T1 T2 T3
2236 1/1 reg_we_check[6] = 1'b0;
Tests: T1 T2 T3
2237 1/1 reg_we_check[7] = 1'b0;
Tests: T1 T2 T3
2238 1/1 reg_we_check[8] = 1'b0;
Tests: T1 T2 T3
2239 1/1 reg_we_check[9] = 1'b0;
Tests: T1 T2 T3
2240 1/1 reg_we_check[10] = 1'b0;
Tests: T1 T2 T3
2241 1/1 reg_we_check[11] = 1'b0;
Tests: T1 T2 T3
2242 1/1 reg_we_check[12] = 1'b0;
Tests: T1 T2 T3
2243 1/1 reg_we_check[13] = 1'b0;
Tests: T1 T2 T3
2244 1/1 reg_we_check[14] = 1'b0;
Tests: T1 T2 T3
2245 1/1 reg_we_check[15] = 1'b0;
Tests: T1 T2 T3
2246 1/1 reg_we_check[16] = 1'b0;
Tests: T1 T2 T3
2247 1/1 reg_we_check[17] = 1'b0;
Tests: T1 T2 T3
2248 1/1 reg_we_check[18] = direct_access_regwen_we;
Tests: T1 T2 T3
2249 1/1 reg_we_check[19] = direct_access_cmd_gated_we;
Tests: T1 T2 T3
2250 1/1 reg_we_check[20] = direct_access_address_gated_we;
Tests: T1 T2 T3
2251 1/1 reg_we_check[21] = direct_access_wdata_0_gated_we;
Tests: T1 T2 T3
2252 1/1 reg_we_check[22] = direct_access_wdata_1_gated_we;
Tests: T1 T2 T3
2253 1/1 reg_we_check[23] = 1'b0;
Tests: T1 T2 T3
2254 1/1 reg_we_check[24] = 1'b0;
Tests: T1 T2 T3
2255 1/1 reg_we_check[25] = check_trigger_regwen_we;
Tests: T1 T2 T3
2256 1/1 reg_we_check[26] = check_trigger_gated_we;
Tests: T1 T2 T3
2257 1/1 reg_we_check[27] = check_regwen_we;
Tests: T1 T2 T3
2258 1/1 reg_we_check[28] = check_timeout_gated_we;
Tests: T1 T2 T3
2259 1/1 reg_we_check[29] = integrity_check_period_gated_we;
Tests: T1 T2 T3
2260 1/1 reg_we_check[30] = consistency_check_period_gated_we;
Tests: T1 T2 T3
2261 1/1 reg_we_check[31] = vendor_test_read_lock_gated_we;
Tests: T1 T2 T3
2262 1/1 reg_we_check[32] = creator_sw_cfg_read_lock_gated_we;
Tests: T1 T2 T3
2263 1/1 reg_we_check[33] = owner_sw_cfg_read_lock_gated_we;
Tests: T1 T2 T3
2264 1/1 reg_we_check[34] = rot_creator_auth_codesign_read_lock_gated_we;
Tests: T1 T2 T3
2265 1/1 reg_we_check[35] = rot_creator_auth_state_read_lock_gated_we;
Tests: T1 T2 T3
2266 1/1 reg_we_check[36] = 1'b0;
Tests: T1 T2 T3
2267 1/1 reg_we_check[37] = 1'b0;
Tests: T1 T2 T3
2268 1/1 reg_we_check[38] = 1'b0;
Tests: T1 T2 T3
2269 1/1 reg_we_check[39] = 1'b0;
Tests: T1 T2 T3
2270 1/1 reg_we_check[40] = 1'b0;
Tests: T1 T2 T3
2271 1/1 reg_we_check[41] = 1'b0;
Tests: T1 T2 T3
2272 1/1 reg_we_check[42] = 1'b0;
Tests: T1 T2 T3
2273 1/1 reg_we_check[43] = 1'b0;
Tests: T1 T2 T3
2274 1/1 reg_we_check[44] = 1'b0;
Tests: T1 T2 T3
2275 1/1 reg_we_check[45] = 1'b0;
Tests: T1 T2 T3
2276 1/1 reg_we_check[46] = 1'b0;
Tests: T1 T2 T3
2277 1/1 reg_we_check[47] = 1'b0;
Tests: T1 T2 T3
2278 1/1 reg_we_check[48] = 1'b0;
Tests: T1 T2 T3
2279 1/1 reg_we_check[49] = 1'b0;
Tests: T1 T2 T3
2280 1/1 reg_we_check[50] = 1'b0;
Tests: T1 T2 T3
2281 1/1 reg_we_check[51] = 1'b0;
Tests: T1 T2 T3
2282 1/1 reg_we_check[52] = 1'b0;
Tests: T1 T2 T3
2283 1/1 reg_we_check[53] = 1'b0;
Tests: T1 T2 T3
2284 1/1 reg_we_check[54] = 1'b0;
Tests: T1 T2 T3
2285 1/1 reg_we_check[55] = 1'b0;
Tests: T1 T2 T3
2286 end
2287
2288 // Read data return
2289 always_comb begin
2290 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
2291 1/1 unique case (1'b1)
Tests: T1 T2 T3
2292 addr_hit[0]: begin
2293 1/1 reg_rdata_next[0] = intr_state_otp_operation_done_qs;
Tests: T1 T2 T3
2294 1/1 reg_rdata_next[1] = intr_state_otp_error_qs;
Tests: T1 T2 T3
2295 end
2296
2297 addr_hit[1]: begin
2298 1/1 reg_rdata_next[0] = intr_enable_otp_operation_done_qs;
Tests: T1 T2 T3
2299 1/1 reg_rdata_next[1] = intr_enable_otp_error_qs;
Tests: T1 T2 T3
2300 end
2301
2302 addr_hit[2]: begin
2303 1/1 reg_rdata_next[0] = '0;
Tests: T2 T3 T5
2304 1/1 reg_rdata_next[1] = '0;
Tests: T2 T3 T5
2305 end
2306
2307 addr_hit[3]: begin
2308 1/1 reg_rdata_next[0] = '0;
Tests: T2 T3 T5
2309 1/1 reg_rdata_next[1] = '0;
Tests: T2 T3 T5
2310 1/1 reg_rdata_next[2] = '0;
Tests: T2 T3 T5
2311 1/1 reg_rdata_next[3] = '0;
Tests: T2 T3 T5
2312 1/1 reg_rdata_next[4] = '0;
Tests: T2 T3 T5
2313 end
2314
2315 addr_hit[4]: begin
2316 1/1 reg_rdata_next[0] = status_vendor_test_error_qs;
Tests: T1 T2 T3
2317 1/1 reg_rdata_next[1] = status_creator_sw_cfg_error_qs;
Tests: T1 T2 T3
2318 1/1 reg_rdata_next[2] = status_owner_sw_cfg_error_qs;
Tests: T1 T2 T3
2319 1/1 reg_rdata_next[3] = status_rot_creator_auth_codesign_error_qs;
Tests: T1 T2 T3
2320 1/1 reg_rdata_next[4] = status_rot_creator_auth_state_error_qs;
Tests: T1 T2 T3
2321 1/1 reg_rdata_next[5] = status_hw_cfg0_error_qs;
Tests: T1 T2 T3
2322 1/1 reg_rdata_next[6] = status_hw_cfg1_error_qs;
Tests: T1 T2 T3
2323 1/1 reg_rdata_next[7] = status_secret0_error_qs;
Tests: T1 T2 T3
2324 1/1 reg_rdata_next[8] = status_secret1_error_qs;
Tests: T1 T2 T3
2325 1/1 reg_rdata_next[9] = status_secret2_error_qs;
Tests: T1 T2 T3
2326 1/1 reg_rdata_next[10] = status_life_cycle_error_qs;
Tests: T1 T2 T3
2327 1/1 reg_rdata_next[11] = status_dai_error_qs;
Tests: T1 T2 T3
2328 1/1 reg_rdata_next[12] = status_lci_error_qs;
Tests: T1 T2 T3
2329 1/1 reg_rdata_next[13] = status_timeout_error_qs;
Tests: T1 T2 T3
2330 1/1 reg_rdata_next[14] = status_lfsr_fsm_error_qs;
Tests: T1 T2 T3
2331 1/1 reg_rdata_next[15] = status_scrambling_fsm_error_qs;
Tests: T1 T2 T3
2332 1/1 reg_rdata_next[16] = status_key_deriv_fsm_error_qs;
Tests: T1 T2 T3
2333 1/1 reg_rdata_next[17] = status_bus_integ_error_qs;
Tests: T1 T2 T3
2334 1/1 reg_rdata_next[18] = status_dai_idle_qs;
Tests: T1 T2 T3
2335 1/1 reg_rdata_next[19] = status_check_pending_qs;
Tests: T1 T2 T3
2336 end
2337
2338 addr_hit[5]: begin
2339 1/1 reg_rdata_next[2:0] = err_code_0_qs;
Tests: T2 T3 T4
2340 end
2341
2342 addr_hit[6]: begin
2343 1/1 reg_rdata_next[2:0] = err_code_1_qs;
Tests: T2 T3 T4
2344 end
2345
2346 addr_hit[7]: begin
2347 1/1 reg_rdata_next[2:0] = err_code_2_qs;
Tests: T2 T3 T4
2348 end
2349
2350 addr_hit[8]: begin
2351 1/1 reg_rdata_next[2:0] = err_code_3_qs;
Tests: T2 T3 T5
2352 end
2353
2354 addr_hit[9]: begin
2355 1/1 reg_rdata_next[2:0] = err_code_4_qs;
Tests: T2 T3 T4
2356 end
2357
2358 addr_hit[10]: begin
2359 1/1 reg_rdata_next[2:0] = err_code_5_qs;
Tests: T2 T3 T4
2360 end
2361
2362 addr_hit[11]: begin
2363 1/1 reg_rdata_next[2:0] = err_code_6_qs;
Tests: T2 T3 T4
2364 end
2365
2366 addr_hit[12]: begin
2367 1/1 reg_rdata_next[2:0] = err_code_7_qs;
Tests: T2 T3 T4
2368 end
2369
2370 addr_hit[13]: begin
2371 1/1 reg_rdata_next[2:0] = err_code_8_qs;
Tests: T2 T3 T4
2372 end
2373
2374 addr_hit[14]: begin
2375 1/1 reg_rdata_next[2:0] = err_code_9_qs;
Tests: T2 T3 T4
2376 end
2377
2378 addr_hit[15]: begin
2379 1/1 reg_rdata_next[2:0] = err_code_10_qs;
Tests: T2 T3 T5
2380 end
2381
2382 addr_hit[16]: begin
2383 1/1 reg_rdata_next[2:0] = err_code_11_qs;
Tests: T2 T3 T4
2384 end
2385
2386 addr_hit[17]: begin
2387 1/1 reg_rdata_next[2:0] = err_code_12_qs;
Tests: T2 T3 T5
2388 end
2389
2390 addr_hit[18]: begin
2391 1/1 reg_rdata_next[0] = direct_access_regwen_qs;
Tests: T2 T3 T4
2392 end
2393
2394 addr_hit[19]: begin
2395 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
2396 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
2397 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T3
2398 end
2399
2400 addr_hit[20]: begin
2401 1/1 reg_rdata_next[10:0] = direct_access_address_qs;
Tests: T1 T2 T3
2402 end
2403
2404 addr_hit[21]: begin
2405 1/1 reg_rdata_next[31:0] = direct_access_wdata_0_qs;
Tests: T1 T2 T3
2406 end
2407
2408 addr_hit[22]: begin
2409 1/1 reg_rdata_next[31:0] = direct_access_wdata_1_qs;
Tests: T2 T3 T4
2410 end
2411
2412 addr_hit[23]: begin
2413 1/1 reg_rdata_next[31:0] = direct_access_rdata_0_qs;
Tests: T1 T2 T3
2414 end
2415
2416 addr_hit[24]: begin
2417 1/1 reg_rdata_next[31:0] = direct_access_rdata_1_qs;
Tests: T2 T3 T4
2418 end
2419
2420 addr_hit[25]: begin
2421 1/1 reg_rdata_next[0] = check_trigger_regwen_qs;
Tests: T2 T3 T4
2422 end
2423
2424 addr_hit[26]: begin
2425 1/1 reg_rdata_next[0] = '0;
Tests: T2 T3 T5
2426 1/1 reg_rdata_next[1] = '0;
Tests: T2 T3 T5
2427 end
2428
2429 addr_hit[27]: begin
2430 1/1 reg_rdata_next[0] = check_regwen_qs;
Tests: T2 T3 T4
2431 end
2432
2433 addr_hit[28]: begin
2434 1/1 reg_rdata_next[31:0] = check_timeout_qs;
Tests: T2 T3 T4
2435 end
2436
2437 addr_hit[29]: begin
2438 1/1 reg_rdata_next[31:0] = integrity_check_period_qs;
Tests: T1 T2 T3
2439 end
2440
2441 addr_hit[30]: begin
2442 1/1 reg_rdata_next[31:0] = consistency_check_period_qs;
Tests: T2 T3 T4
2443 end
2444
2445 addr_hit[31]: begin
2446 1/1 reg_rdata_next[0] = vendor_test_read_lock_qs;
Tests: T2 T3 T4
2447 end
2448
2449 addr_hit[32]: begin
2450 1/1 reg_rdata_next[0] = creator_sw_cfg_read_lock_qs;
Tests: T2 T3 T4
2451 end
2452
2453 addr_hit[33]: begin
2454 1/1 reg_rdata_next[0] = owner_sw_cfg_read_lock_qs;
Tests: T2 T3 T4
2455 end
2456
2457 addr_hit[34]: begin
2458 1/1 reg_rdata_next[0] = rot_creator_auth_codesign_read_lock_qs;
Tests: T2 T3 T4
2459 end
2460
2461 addr_hit[35]: begin
2462 1/1 reg_rdata_next[0] = rot_creator_auth_state_read_lock_qs;
Tests: T2 T3 T4
2463 end
2464
2465 addr_hit[36]: begin
2466 1/1 reg_rdata_next[31:0] = vendor_test_digest_0_qs;
Tests: T2 T3 T4
2467 end
2468
2469 addr_hit[37]: begin
2470 1/1 reg_rdata_next[31:0] = vendor_test_digest_1_qs;
Tests: T2 T3 T4
2471 end
2472
2473 addr_hit[38]: begin
2474 1/1 reg_rdata_next[31:0] = creator_sw_cfg_digest_0_qs;
Tests: T2 T3 T4
2475 end
2476
2477 addr_hit[39]: begin
2478 1/1 reg_rdata_next[31:0] = creator_sw_cfg_digest_1_qs;
Tests: T2 T3 T4
2479 end
2480
2481 addr_hit[40]: begin
2482 1/1 reg_rdata_next[31:0] = owner_sw_cfg_digest_0_qs;
Tests: T2 T3 T5
2483 end
2484
2485 addr_hit[41]: begin
2486 1/1 reg_rdata_next[31:0] = owner_sw_cfg_digest_1_qs;
Tests: T2 T3 T5
2487 end
2488
2489 addr_hit[42]: begin
2490 1/1 reg_rdata_next[31:0] = rot_creator_auth_codesign_digest_0_qs;
Tests: T2 T3 T4
2491 end
2492
2493 addr_hit[43]: begin
2494 1/1 reg_rdata_next[31:0] = rot_creator_auth_codesign_digest_1_qs;
Tests: T2 T3 T4
2495 end
2496
2497 addr_hit[44]: begin
2498 1/1 reg_rdata_next[31:0] = rot_creator_auth_state_digest_0_qs;
Tests: T2 T3 T4
2499 end
2500
2501 addr_hit[45]: begin
2502 1/1 reg_rdata_next[31:0] = rot_creator_auth_state_digest_1_qs;
Tests: T2 T3 T4
2503 end
2504
2505 addr_hit[46]: begin
2506 1/1 reg_rdata_next[31:0] = hw_cfg0_digest_0_qs;
Tests: T2 T3 T4
2507 end
2508
2509 addr_hit[47]: begin
2510 1/1 reg_rdata_next[31:0] = hw_cfg0_digest_1_qs;
Tests: T2 T3 T4
2511 end
2512
2513 addr_hit[48]: begin
2514 1/1 reg_rdata_next[31:0] = hw_cfg1_digest_0_qs;
Tests: T2 T3 T5
2515 end
2516
2517 addr_hit[49]: begin
2518 1/1 reg_rdata_next[31:0] = hw_cfg1_digest_1_qs;
Tests: T2 T3 T5
2519 end
2520
2521 addr_hit[50]: begin
2522 1/1 reg_rdata_next[31:0] = secret0_digest_0_qs;
Tests: T2 T3 T4
2523 end
2524
2525 addr_hit[51]: begin
2526 1/1 reg_rdata_next[31:0] = secret0_digest_1_qs;
Tests: T2 T3 T5
2527 end
2528
2529 addr_hit[52]: begin
2530 1/1 reg_rdata_next[31:0] = secret1_digest_0_qs;
Tests: T2 T3 T5
2531 end
2532
2533 addr_hit[53]: begin
2534 1/1 reg_rdata_next[31:0] = secret1_digest_1_qs;
Tests: T2 T3 T4
2535 end
2536
2537 addr_hit[54]: begin
2538 1/1 reg_rdata_next[31:0] = secret2_digest_0_qs;
Tests: T2 T3 T5
2539 end
2540
2541 addr_hit[55]: begin
2542 1/1 reg_rdata_next[31:0] = secret2_digest_1_qs;
Tests: T2 T3 T5
2543 end
2544
2545 default: begin
2546 reg_rdata_next = '1;
2547 end
2548 endcase
2549 end
2550
2551 // shadow busy
2552 logic shadow_busy;
2553 assign shadow_busy = 1'b0;
2554
2555 // register busy
2556 unreachable assign reg_busy = shadow_busy;
2557
2558 // Unused signal tieoff
2559
2560 // wdata / byte enable are not always fully used
2561 // add a blanket unused statement to handle lint waivers
2562 logic unused_wdata;
2563 logic unused_be;
2564 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
2565 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3