Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
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Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv


Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
keymgr_rd_en 2 0 2 100.00 100 1 1 2
secret2_lock 2 0 2 100.00 100 1 1 2


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
keymgr_output_conditions 4 0 4 100.00 100 1 1 0


Summary for Variable keymgr_rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for keymgr_rd_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3524 1 T2 1 T3 2 T5 1
auto[1] 2463 1 T4 2 T6 2 T7 3


Summary for Variable secret2_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret2_lock

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4113 1 T2 1 T3 2 T4 2
auto[1] 1874 1 T6 1 T7 1 T73 2


Summary for Cross keymgr_output_conditions

Samples crossed: keymgr_rd_en secret2_lock
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for keymgr_output_conditions

Bins
keymgr_rd_en   secret2_lock   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 2422 1 T2 1 T3 2 T5 1
auto[0] auto[1] 1102 1 T7 1 T73 2 T17 4
auto[1] auto[0] 1691 1 T4 2 T6 1 T7 3
auto[1] auto[1] 772 1 T6 1 T17 2 T26 1