8d5fa645a8d5fa645a| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |
| V2 | perf | pattgen_perf | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 5 | 5 | 100.00 |
| pattgen_csr_rw | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 5 | 5 | 100.00 |
| pattgen_csr_rw | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |
| V2S | tl_intg_err | pattgen_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 42 | 50 | 84.00 |
| V3 | TOTAL | 42 | 50 | 84.00 | |
| Unmapped tests | pattgen_mem_walk | 5 | 5 | 100.00 | |
| pattgen_mem_partial_access | 5 | 5 | 100.00 | ||
| TOTAL | 517 | 525 | 98.48 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 2 | 100.00 |
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 1 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 84.81 | 98.40 | 97.56 | 99.16 | 85.02 | 75.99 | -- | 99.38 | 90.34 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 8 failures:
16.pattgen_stress_all_with_rand_reset.1442259225
Line 367, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 11766489376 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
23.pattgen_stress_all_with_rand_reset.2731161311
Line 683, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 61156394980 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 6 more failures.