PATTGEN Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2359737659

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 5.000s 212.644us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 2.000s 173.266us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 13.372us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 6.000s 549.910us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 2.000s 18.283us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 4.000s 102.188us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 13.372us 20 20 100.00
pattgen_csr_aliasing 2.000s 18.283us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.633m 7.892ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.333m 20.179ms 50 50 100.00
V2 error pattgen_error 3.000s 26.561us 50 50 100.00
V2 stress_all pattgen_stress_all 3.583m 5.540ms 50 50 100.00
V2 alert_test pattgen_alert_test 4.000s 51.344us 50 50 100.00
V2 intr_test pattgen_intr_test 4.000s 33.077us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 6.000s 479.325us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 6.000s 479.325us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 2.000s 173.266us 5 5 100.00
pattgen_csr_rw 3.000s 13.372us 20 20 100.00
pattgen_csr_aliasing 2.000s 18.283us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 21.426us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 2.000s 173.266us 5 5 100.00
pattgen_csr_rw 3.000s 13.372us 20 20 100.00
pattgen_csr_aliasing 2.000s 18.283us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 21.426us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 4.000s 70.003us 20 20 100.00
pattgen_sec_cm 3.000s 143.881us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 4.000s 70.003us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 31.867m 744.104ms 42 50 84.00
V3 TOTAL 42 50 84.00
TOTAL 512 520 98.46

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.81 100.00 100.00 100.00 99.06 96.13 -- 100.00 90.43

Failure Buckets

Past Results