748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | prim_alert_request_test | prim_async_alert | 0.410s | 12.114us | 20 | 20 | 100.00 |
| prim_async_fatal_alert | 0.460s | 28.830us | 15 | 20 | 75.00 | ||
| prim_sync_alert | 0.380s | 9.812us | 18 | 20 | 90.00 | ||
| prim_sync_fatal_alert | 0.420s | 28.122us | 20 | 20 | 100.00 | ||
| V1 | prim_alert_test | prim_async_alert | 0.410s | 12.114us | 20 | 20 | 100.00 |
| prim_async_fatal_alert | 0.460s | 28.830us | 15 | 20 | 75.00 | ||
| prim_sync_alert | 0.380s | 9.812us | 18 | 20 | 90.00 | ||
| prim_sync_fatal_alert | 0.420s | 28.122us | 20 | 20 | 100.00 | ||
| V1 | prim_alert_ping_request_test | prim_async_alert | 0.410s | 12.114us | 20 | 20 | 100.00 |
| prim_async_fatal_alert | 0.460s | 28.830us | 15 | 20 | 75.00 | ||
| prim_sync_alert | 0.380s | 9.812us | 18 | 20 | 90.00 | ||
| prim_sync_fatal_alert | 0.420s | 28.122us | 20 | 20 | 100.00 | ||
| V1 | prim_alert_integrity_errors_test | prim_async_alert | 0.410s | 12.114us | 20 | 20 | 100.00 |
| prim_async_fatal_alert | 0.460s | 28.830us | 15 | 20 | 75.00 | ||
| prim_sync_alert | 0.380s | 9.812us | 18 | 20 | 90.00 | ||
| prim_sync_fatal_alert | 0.420s | 28.122us | 20 | 20 | 100.00 | ||
| V1 | TOTAL | 73 | 80 | 91.25 | |||
| V2 | prim_alert_init_trigger_test | prim_async_alert | 0.410s | 12.114us | 20 | 20 | 100.00 |
| prim_async_fatal_alert | 0.460s | 28.830us | 15 | 20 | 75.00 | ||
| prim_sync_alert | 0.380s | 9.812us | 18 | 20 | 90.00 | ||
| prim_sync_fatal_alert | 0.420s | 28.122us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 0 | 0 | -- | |||
| V2S | TOTAL | 0 | 0 | -- | |||
| V3 | prim_alert_gate_sender_clk_rst_test | prim_alert_gate_sender_clk_rst_test | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 73 | 80 | 91.25 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 4 | 4 | 2 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
|---|---|---|---|---|---|---|
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
Exit reason: Error: User command failed Job returned non-zero exit code has 7 failures:
0.prim_async_fatal_alert.83609230455211660797583746772319917796346289896904433721763096208440829733978
Log /container/opentitan-public/scratch/os_regression/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest/run.log
[make]: simulate
cd /workspace/0.prim_async_fatal_alert/latest && /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897800282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2897800282
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.prim_async_fatal_alert.19029181141963068314920467273308349024286198361038929475047268917002821056534
Log /container/opentitan-public/scratch/os_regression/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest/run.log
[make]: simulate
cd /workspace/3.prim_async_fatal_alert/latest && /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591176726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2591176726
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
1.prim_sync_alert.21716912699031477659984005880604994984560930050736399025349765858839027418567
Log /container/opentitan-public/scratch/os_regression/prim_alert-sim-vcs/1.prim_sync_alert/latest/run.log
[make]: simulate
cd /workspace/1.prim_sync_alert/latest && /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494282695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3494282695
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:36 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
15.prim_sync_alert.28239608730590743338352188964617088222775976053157982728131404385395726546227
Log /container/opentitan-public/scratch/os_regression/prim_alert-sim-vcs/15.prim_sync_alert/latest/run.log
[make]: simulate
cd /workspace/15.prim_sync_alert/latest && /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587110195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3587110195
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:36 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255