PRIM_ESC Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: `042415198f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	prim_esc_request_test	prim_esc_test	0.390s	5.109us	19	20	95.00
V1	prim_ping_req_interrupted_by_esc_req_test	prim_esc_test	0.390s	5.109us	19	20	95.00
V1	prim_esc_tx_integrity_errors_test	prim_esc_test	0.390s	5.109us	19	20	95.00
V1	prim_esc_reverse_ping_timeout_test	prim_esc_test	0.390s	5.109us	19	20	95.00
V1	prim_esc_receiver_counter_fail_test	prim_esc_test	0.390s	5.109us	19	20	95.00
V1	prim_esc_handshake_with_rand_reset_test	prim_esc_test	0.390s	5.109us	19	20	95.00
V1		TOTAL			19	20	95.00
V2		TOTAL			0	0	--
V2S		TOTAL			0	0	--
V3		TOTAL			0	0	--
		TOTAL			19	20	95.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.31	95.24	86.36	100.00	96.43	88.37	81.48

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test prim_esc_test has 1 failures.

0.prim_esc_test.62654654217048697987214888836294177758012354987565096064677724428101226739877
Log /container/opentitan-public/scratch/os_regression/prim_esc-sim-vcs/0.prim_esc_test/latest/run.log

  [make]: simulate
  cd /workspace/0.prim_esc_test/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455910565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2455910565
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  7 12:38 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255