PRIM_ESC Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 prim_esc_request_test prim_esc_test 0.500s 4.782us 20 20 100.00
V1 prim_ping_req_interrupted_by_esc_req_test prim_esc_test 0.500s 4.782us 20 20 100.00
V1 prim_esc_tx_integrity_errors_test prim_esc_test 0.500s 4.782us 20 20 100.00
V1 prim_esc_reverse_ping_timeout_test prim_esc_test 0.500s 4.782us 20 20 100.00
V1 prim_esc_receiver_counter_fail_test prim_esc_test 0.500s 4.782us 20 20 100.00
V1 prim_esc_handshake_with_rand_reset_test prim_esc_test 0.500s 4.782us 20 20 100.00
V1 TOTAL 20 20 100.00
V2 TOTAL 0 0 --
V2S TOTAL 0 0 --
V3 TOTAL 0 0 --
TOTAL 20 20 100.00

Testplan Progress

Items Total Written Passing Progress
V1 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT
88.11 92.38 85.37 100.00 85.71 83.72 81.48

Past Results