PRIM_ESC Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 prim_esc_request_test prim_esc_test 0.410s 4.534us 20 20 100.00
V1 prim_ping_req_interrupted_by_esc_req_test prim_esc_test 0.410s 4.534us 20 20 100.00
V1 prim_esc_tx_integrity_errors_test prim_esc_test 0.410s 4.534us 20 20 100.00
V1 prim_esc_reverse_ping_timeout_test prim_esc_test 0.410s 4.534us 20 20 100.00
V1 prim_esc_receiver_counter_fail_test prim_esc_test 0.410s 4.534us 20 20 100.00
V1 prim_esc_handshake_with_rand_reset_test prim_esc_test 0.410s 4.534us 20 20 100.00
V1 TOTAL 20 20 100.00
V2 TOTAL 0 0 --
V2S TOTAL 0 0 --
V3 TOTAL 0 0 --
TOTAL 20 20 100.00

Testplan Progress

Items Total Written Passing Progress
V1 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48

Past Results