PRIM_ESC Simulation Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	prim_esc_request_test	prim_esc_test	0.500s	4.126us	20	20	100.00
V1	prim_ping_req_interrupted_by_esc_req_test	prim_esc_test	0.500s	4.126us	20	20	100.00
V1	prim_esc_tx_integrity_errors_test	prim_esc_test	0.500s	4.126us	20	20	100.00
V1	prim_esc_reverse_ping_timeout_test	prim_esc_test	0.500s	4.126us	20	20	100.00
V1	prim_esc_receiver_counter_fail_test	prim_esc_test	0.500s	4.126us	20	20	100.00
V1	prim_esc_handshake_with_rand_reset_test	prim_esc_test	0.500s	4.126us	20	20	100.00
V1		TOTAL			20	20	100.00
V2		TOTAL			0	0	--
V2S		TOTAL			0	0	--
V3		TOTAL			0	0	--
		TOTAL			20	20	100.00

Items	Total	Written	Passing	Progress
V1	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.41	94.29	85.37	100.00	89.29	86.05	81.48