| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 96.92 | 97.92 | 100.00 | 100.00 | 100.00 | 86.67 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 96.91 | 96.91 | 97.87 | 97.87 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 86.67 | 86.67 | /workspace/coverage/prim_lfsr_dw_24/15.prim_lfsr_test.623347760 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24/0.prim_lfsr_test.3021127371 |
| /workspace/coverage/prim_lfsr_dw_24/1.prim_lfsr_test.3008562019 |
| /workspace/coverage/prim_lfsr_dw_24/10.prim_lfsr_test.4195400074 |
| /workspace/coverage/prim_lfsr_dw_24/11.prim_lfsr_test.1382272384 |
| /workspace/coverage/prim_lfsr_dw_24/12.prim_lfsr_test.825026312 |
| /workspace/coverage/prim_lfsr_dw_24/13.prim_lfsr_test.827029415 |
| /workspace/coverage/prim_lfsr_dw_24/14.prim_lfsr_test.1556992058 |
| /workspace/coverage/prim_lfsr_dw_24/16.prim_lfsr_test.234542670 |
| /workspace/coverage/prim_lfsr_dw_24/17.prim_lfsr_test.3589894256 |
| /workspace/coverage/prim_lfsr_dw_24/18.prim_lfsr_test.2625199227 |
| /workspace/coverage/prim_lfsr_dw_24/19.prim_lfsr_test.1609914486 |
| /workspace/coverage/prim_lfsr_dw_24/2.prim_lfsr_test.684736042 |
| /workspace/coverage/prim_lfsr_dw_24/20.prim_lfsr_test.3128259420 |
| /workspace/coverage/prim_lfsr_dw_24/21.prim_lfsr_test.2498976821 |
| /workspace/coverage/prim_lfsr_dw_24/22.prim_lfsr_test.369214352 |
| /workspace/coverage/prim_lfsr_dw_24/23.prim_lfsr_test.741158157 |
| /workspace/coverage/prim_lfsr_dw_24/24.prim_lfsr_test.1078828969 |
| /workspace/coverage/prim_lfsr_dw_24/25.prim_lfsr_test.506472686 |
| /workspace/coverage/prim_lfsr_dw_24/26.prim_lfsr_test.877766889 |
| /workspace/coverage/prim_lfsr_dw_24/27.prim_lfsr_test.2865470485 |
| /workspace/coverage/prim_lfsr_dw_24/28.prim_lfsr_test.3748280388 |
| /workspace/coverage/prim_lfsr_dw_24/29.prim_lfsr_test.218943339 |
| /workspace/coverage/prim_lfsr_dw_24/3.prim_lfsr_test.1636228770 |
| /workspace/coverage/prim_lfsr_dw_24/30.prim_lfsr_test.1525993268 |
| /workspace/coverage/prim_lfsr_dw_24/31.prim_lfsr_test.3448572587 |
| /workspace/coverage/prim_lfsr_dw_24/32.prim_lfsr_test.3260891854 |
| /workspace/coverage/prim_lfsr_dw_24/33.prim_lfsr_test.1681759266 |
| /workspace/coverage/prim_lfsr_dw_24/34.prim_lfsr_test.2595077614 |
| /workspace/coverage/prim_lfsr_dw_24/35.prim_lfsr_test.3170347962 |
| /workspace/coverage/prim_lfsr_dw_24/36.prim_lfsr_test.364526843 |
| /workspace/coverage/prim_lfsr_dw_24/37.prim_lfsr_test.1488897272 |
| /workspace/coverage/prim_lfsr_dw_24/38.prim_lfsr_test.2880105433 |
| /workspace/coverage/prim_lfsr_dw_24/39.prim_lfsr_test.2898085258 |
| /workspace/coverage/prim_lfsr_dw_24/4.prim_lfsr_test.1632895298 |
| /workspace/coverage/prim_lfsr_dw_24/40.prim_lfsr_test.905426664 |
| /workspace/coverage/prim_lfsr_dw_24/41.prim_lfsr_test.876472761 |
| /workspace/coverage/prim_lfsr_dw_24/42.prim_lfsr_test.1394973030 |
| /workspace/coverage/prim_lfsr_dw_24/43.prim_lfsr_test.2364340783 |
| /workspace/coverage/prim_lfsr_dw_24/44.prim_lfsr_test.2691103424 |
| /workspace/coverage/prim_lfsr_dw_24/45.prim_lfsr_test.3653240123 |
| /workspace/coverage/prim_lfsr_dw_24/46.prim_lfsr_test.2340288667 |
| /workspace/coverage/prim_lfsr_dw_24/47.prim_lfsr_test.3995055219 |
| /workspace/coverage/prim_lfsr_dw_24/48.prim_lfsr_test.4140993623 |
| /workspace/coverage/prim_lfsr_dw_24/49.prim_lfsr_test.956420568 |
| /workspace/coverage/prim_lfsr_dw_24/5.prim_lfsr_test.4192576620 |
| /workspace/coverage/prim_lfsr_dw_24/6.prim_lfsr_test.4074765061 |
| /workspace/coverage/prim_lfsr_dw_24/7.prim_lfsr_test.2485161323 |
| /workspace/coverage/prim_lfsr_dw_24/8.prim_lfsr_test.2283369362 |
| /workspace/coverage/prim_lfsr_dw_24/9.prim_lfsr_test.901802795 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_24/18.prim_lfsr_test.2625199227 | Apr 28 01:44:10 AM PDT 22 | Apr 28 01:55:35 AM PDT 22 | 167773180056 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_24/16.prim_lfsr_test.234542670 | Apr 28 01:44:22 AM PDT 22 | Apr 28 01:55:15 AM PDT 22 | 167773242071 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_24/6.prim_lfsr_test.4074765061 | Apr 28 01:44:26 AM PDT 22 | Apr 28 01:54:53 AM PDT 22 | 167773316595 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_24/42.prim_lfsr_test.1394973030 | Apr 28 01:41:25 AM PDT 22 | Apr 28 01:53:30 AM PDT 22 | 167772992084 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_24/38.prim_lfsr_test.2880105433 | Apr 28 01:42:13 AM PDT 22 | Apr 28 01:52:30 AM PDT 22 | 167772872916 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_24/47.prim_lfsr_test.3995055219 | Apr 28 01:39:05 AM PDT 22 | Apr 28 01:48:49 AM PDT 22 | 167772976050 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_24/32.prim_lfsr_test.3260891854 | Apr 28 01:44:26 AM PDT 22 | Apr 28 01:56:42 AM PDT 22 | 167773343547 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_24/35.prim_lfsr_test.3170347962 | Apr 28 01:43:52 AM PDT 22 | Apr 28 01:54:30 AM PDT 22 | 167773007800 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_24/31.prim_lfsr_test.3448572587 | Apr 28 01:44:22 AM PDT 22 | Apr 28 01:54:24 AM PDT 22 | 167773035420 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_24/15.prim_lfsr_test.623347760 | Apr 28 01:40:19 AM PDT 22 | Apr 28 01:50:41 AM PDT 22 | 167773341748 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_24/48.prim_lfsr_test.4140993623 | Apr 28 01:44:03 AM PDT 22 | Apr 28 01:55:02 AM PDT 22 | 167772942328 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_24/10.prim_lfsr_test.4195400074 | Apr 28 01:44:34 AM PDT 22 | Apr 28 01:55:43 AM PDT 22 | 167773112849 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_24/36.prim_lfsr_test.364526843 | Apr 28 01:43:37 AM PDT 22 | Apr 28 01:55:03 AM PDT 22 | 167773091978 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24/13.prim_lfsr_test.827029415 | Apr 28 01:39:39 AM PDT 22 | Apr 28 01:49:29 AM PDT 22 | 167773053556 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24/0.prim_lfsr_test.3021127371 | Apr 28 01:40:34 AM PDT 22 | Apr 28 01:50:08 AM PDT 22 | 167772928351 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24/40.prim_lfsr_test.905426664 | Apr 28 01:44:22 AM PDT 22 | Apr 28 01:54:26 AM PDT 22 | 167773205299 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24/17.prim_lfsr_test.3589894256 | Apr 28 01:39:03 AM PDT 22 | Apr 28 01:48:28 AM PDT 22 | 167773163830 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24/39.prim_lfsr_test.2898085258 | Apr 28 01:43:59 AM PDT 22 | Apr 28 01:55:04 AM PDT 22 | 167773070358 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24/12.prim_lfsr_test.825026312 | Apr 28 01:42:34 AM PDT 22 | Apr 28 01:53:04 AM PDT 22 | 167773039650 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24/24.prim_lfsr_test.1078828969 | Apr 28 01:43:56 AM PDT 22 | Apr 28 01:55:28 AM PDT 22 | 167772870191 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24/3.prim_lfsr_test.1636228770 | Apr 28 01:44:21 AM PDT 22 | Apr 28 01:54:13 AM PDT 22 | 167773142626 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24/8.prim_lfsr_test.2283369362 | Apr 28 01:43:49 AM PDT 22 | Apr 28 01:54:41 AM PDT 22 | 167772998780 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24/49.prim_lfsr_test.956420568 | Apr 28 01:39:03 AM PDT 22 | Apr 28 01:49:57 AM PDT 22 | 167773114818 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_24/27.prim_lfsr_test.2865470485 | Apr 28 01:41:34 AM PDT 22 | Apr 28 01:53:02 AM PDT 22 | 167773002961 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_24/7.prim_lfsr_test.2485161323 | Apr 28 01:44:25 AM PDT 22 | Apr 28 01:54:30 AM PDT 22 | 167773221989 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_24/25.prim_lfsr_test.506472686 | Apr 28 01:43:26 AM PDT 22 | Apr 28 01:54:09 AM PDT 22 | 167773010505 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_24/26.prim_lfsr_test.877766889 | Apr 28 01:44:03 AM PDT 22 | Apr 28 01:55:27 AM PDT 22 | 167773213050 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_24/41.prim_lfsr_test.876472761 | Apr 28 01:42:54 AM PDT 22 | Apr 28 01:54:45 AM PDT 22 | 167773000681 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_24/11.prim_lfsr_test.1382272384 | Apr 28 01:43:13 AM PDT 22 | Apr 28 01:53:37 AM PDT 22 | 167773130797 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_24/21.prim_lfsr_test.2498976821 | Apr 28 01:43:54 AM PDT 22 | Apr 28 01:54:24 AM PDT 22 | 167772933452 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24/1.prim_lfsr_test.3008562019 | Apr 28 01:44:33 AM PDT 22 | Apr 28 01:55:41 AM PDT 22 | 167772884596 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24/43.prim_lfsr_test.2364340783 | Apr 28 01:43:51 AM PDT 22 | Apr 28 01:55:28 AM PDT 22 | 167773134319 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24/14.prim_lfsr_test.1556992058 | Apr 28 01:44:35 AM PDT 22 | Apr 28 01:55:53 AM PDT 22 | 167772937451 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24/9.prim_lfsr_test.901802795 | Apr 28 01:44:02 AM PDT 22 | Apr 28 01:54:53 AM PDT 22 | 167773084226 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24/46.prim_lfsr_test.2340288667 | Apr 28 01:39:39 AM PDT 22 | Apr 28 01:50:41 AM PDT 22 | 167772858719 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24/34.prim_lfsr_test.2595077614 | Apr 28 01:39:50 AM PDT 22 | Apr 28 01:51:38 AM PDT 22 | 167773048168 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24/45.prim_lfsr_test.3653240123 | Apr 28 01:41:55 AM PDT 22 | Apr 28 01:53:20 AM PDT 22 | 167773292996 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24/33.prim_lfsr_test.1681759266 | Apr 28 01:39:03 AM PDT 22 | Apr 28 01:49:59 AM PDT 22 | 167773221216 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24/37.prim_lfsr_test.1488897272 | Apr 28 01:39:49 AM PDT 22 | Apr 28 01:50:58 AM PDT 22 | 167772891753 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24/23.prim_lfsr_test.741158157 | Apr 28 01:43:50 AM PDT 22 | Apr 28 01:54:40 AM PDT 22 | 167773325324 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_24/20.prim_lfsr_test.3128259420 | Apr 28 01:41:17 AM PDT 22 | Apr 28 01:51:30 AM PDT 22 | 167772953909 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_24/5.prim_lfsr_test.4192576620 | Apr 28 01:41:17 AM PDT 22 | Apr 28 01:51:47 AM PDT 22 | 167773203660 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_24/19.prim_lfsr_test.1609914486 | Apr 28 01:44:21 AM PDT 22 | Apr 28 01:54:58 AM PDT 22 | 167773020251 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_24/28.prim_lfsr_test.3748280388 | Apr 28 01:41:11 AM PDT 22 | Apr 28 01:51:49 AM PDT 22 | 167773179501 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_24/29.prim_lfsr_test.218943339 | Apr 28 01:42:41 AM PDT 22 | Apr 28 01:53:34 AM PDT 22 | 167773315569 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_24/30.prim_lfsr_test.1525993268 | Apr 28 01:44:02 AM PDT 22 | Apr 28 01:55:05 AM PDT 22 | 167773078645 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_24/22.prim_lfsr_test.369214352 | Apr 28 01:44:23 AM PDT 22 | Apr 28 01:54:47 AM PDT 22 | 167773018230 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_24/2.prim_lfsr_test.684736042 | Apr 28 01:43:52 AM PDT 22 | Apr 28 01:56:37 AM PDT 22 | 167773214913 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_24/44.prim_lfsr_test.2691103424 | Apr 28 01:44:26 AM PDT 22 | Apr 28 01:54:05 AM PDT 22 | 167773126799 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_24/4.prim_lfsr_test.1632895298 | Apr 28 01:39:23 AM PDT 22 | Apr 28 01:49:58 AM PDT 22 | 167772970604 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_24/15.prim_lfsr_test.623347760 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 167773341748 ps |
| CPU time | 270.08 seconds |
| Started | Apr 28 01:40:19 AM PDT 22 |
| Finished | Apr 28 01:50:41 AM PDT 22 |
| Peak memory | 142740 kb |
| Host | smart-4043ca70-4216-41c8-b58f-d198b635ca84 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=623347760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_test.623347760 |
| Directory | /workspace/15.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/0.prim_lfsr_test.3021127371 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 167772928351 ps |
| CPU time | 260.28 seconds |
| Started | Apr 28 01:40:34 AM PDT 22 |
| Finished | Apr 28 01:50:08 AM PDT 22 |
| Peak memory | 142800 kb |
| Host | smart-5615f64c-858f-4838-ac2e-9c88f495d013 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3021127371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_test.3021127371 |
| Directory | /workspace/0.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/1.prim_lfsr_test.3008562019 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 167772884596 ps |
| CPU time | 307.9 seconds |
| Started | Apr 28 01:44:33 AM PDT 22 |
| Finished | Apr 28 01:55:41 AM PDT 22 |
| Peak memory | 142924 kb |
| Host | smart-47c94b66-09c8-4de7-9e92-dee6cef8be5b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3008562019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_test.3008562019 |
| Directory | /workspace/1.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/10.prim_lfsr_test.4195400074 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 167773112849 ps |
| CPU time | 307.57 seconds |
| Started | Apr 28 01:44:34 AM PDT 22 |
| Finished | Apr 28 01:55:43 AM PDT 22 |
| Peak memory | 142928 kb |
| Host | smart-ce56be37-ca4c-4135-8111-df4a4b08fa71 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4195400074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_test.4195400074 |
| Directory | /workspace/10.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/11.prim_lfsr_test.1382272384 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 167773130797 ps |
| CPU time | 275.03 seconds |
| Started | Apr 28 01:43:13 AM PDT 22 |
| Finished | Apr 28 01:53:37 AM PDT 22 |
| Peak memory | 142800 kb |
| Host | smart-fbcdd216-442d-4d29-8503-d91ffae6182d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1382272384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_test.1382272384 |
| Directory | /workspace/11.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/12.prim_lfsr_test.825026312 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 167773039650 ps |
| CPU time | 274.72 seconds |
| Started | Apr 28 01:42:34 AM PDT 22 |
| Finished | Apr 28 01:53:04 AM PDT 22 |
| Peak memory | 142788 kb |
| Host | smart-1855643b-172f-4f5a-9d59-d7d8c3d5afe9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=825026312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_test.825026312 |
| Directory | /workspace/12.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/13.prim_lfsr_test.827029415 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 167773053556 ps |
| CPU time | 267.14 seconds |
| Started | Apr 28 01:39:39 AM PDT 22 |
| Finished | Apr 28 01:49:29 AM PDT 22 |
| Peak memory | 142728 kb |
| Host | smart-9c8bb8c8-394d-4923-9e68-72b16f58ed82 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=827029415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_test.827029415 |
| Directory | /workspace/13.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/14.prim_lfsr_test.1556992058 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 167772937451 ps |
| CPU time | 305.41 seconds |
| Started | Apr 28 01:44:35 AM PDT 22 |
| Finished | Apr 28 01:55:53 AM PDT 22 |
| Peak memory | 142924 kb |
| Host | smart-d76c353c-79bb-4ad9-8ed4-b983075e7362 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1556992058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_test.1556992058 |
| Directory | /workspace/14.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/16.prim_lfsr_test.234542670 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 167773242071 ps |
| CPU time | 285.48 seconds |
| Started | Apr 28 01:44:22 AM PDT 22 |
| Finished | Apr 28 01:55:15 AM PDT 22 |
| Peak memory | 142756 kb |
| Host | smart-c742bc4d-bc90-430f-8c58-20ff6942f888 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=234542670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_test.234542670 |
| Directory | /workspace/16.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/17.prim_lfsr_test.3589894256 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 167773163830 ps |
| CPU time | 257.97 seconds |
| Started | Apr 28 01:39:03 AM PDT 22 |
| Finished | Apr 28 01:48:28 AM PDT 22 |
| Peak memory | 142804 kb |
| Host | smart-7cb1abea-bba7-47e0-9ff6-a9ee1247d35f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3589894256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_test.3589894256 |
| Directory | /workspace/17.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/18.prim_lfsr_test.2625199227 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 167773180056 ps |
| CPU time | 310.06 seconds |
| Started | Apr 28 01:44:10 AM PDT 22 |
| Finished | Apr 28 01:55:35 AM PDT 22 |
| Peak memory | 142904 kb |
| Host | smart-f70b976c-702f-469c-b2b7-78ce43e43263 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2625199227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_test.2625199227 |
| Directory | /workspace/18.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/19.prim_lfsr_test.1609914486 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 167773020251 ps |
| CPU time | 274.17 seconds |
| Started | Apr 28 01:44:21 AM PDT 22 |
| Finished | Apr 28 01:54:58 AM PDT 22 |
| Peak memory | 142924 kb |
| Host | smart-f206c6bd-8e30-4390-be49-a0b32d7d0ff0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1609914486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_test.1609914486 |
| Directory | /workspace/19.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/2.prim_lfsr_test.684736042 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 167773214913 ps |
| CPU time | 337.18 seconds |
| Started | Apr 28 01:43:52 AM PDT 22 |
| Finished | Apr 28 01:56:37 AM PDT 22 |
| Peak memory | 142912 kb |
| Host | smart-54956ee7-c7dc-4002-b603-39e782d42b8e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=684736042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_test.684736042 |
| Directory | /workspace/2.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/20.prim_lfsr_test.3128259420 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 167772953909 ps |
| CPU time | 275.03 seconds |
| Started | Apr 28 01:41:17 AM PDT 22 |
| Finished | Apr 28 01:51:30 AM PDT 22 |
| Peak memory | 142812 kb |
| Host | smart-e013fedf-63b1-417f-8b48-44dc7e679b81 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3128259420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_test.3128259420 |
| Directory | /workspace/20.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/21.prim_lfsr_test.2498976821 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 167772933452 ps |
| CPU time | 282.98 seconds |
| Started | Apr 28 01:43:54 AM PDT 22 |
| Finished | Apr 28 01:54:24 AM PDT 22 |
| Peak memory | 142928 kb |
| Host | smart-930263cc-c261-4c54-844b-f29268f053ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2498976821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_test.2498976821 |
| Directory | /workspace/21.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/22.prim_lfsr_test.369214352 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 167773018230 ps |
| CPU time | 274.23 seconds |
| Started | Apr 28 01:44:23 AM PDT 22 |
| Finished | Apr 28 01:54:47 AM PDT 22 |
| Peak memory | 142736 kb |
| Host | smart-6952e925-b8ee-472c-a7ad-7fe79cdee613 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=369214352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_test.369214352 |
| Directory | /workspace/22.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/23.prim_lfsr_test.741158157 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 167773325324 ps |
| CPU time | 291.59 seconds |
| Started | Apr 28 01:43:50 AM PDT 22 |
| Finished | Apr 28 01:54:40 AM PDT 22 |
| Peak memory | 142852 kb |
| Host | smart-5022478f-d312-4c5c-a013-9e43e99cf9dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=741158157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_test.741158157 |
| Directory | /workspace/23.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/24.prim_lfsr_test.1078828969 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 167772870191 ps |
| CPU time | 309.9 seconds |
| Started | Apr 28 01:43:56 AM PDT 22 |
| Finished | Apr 28 01:55:28 AM PDT 22 |
| Peak memory | 142928 kb |
| Host | smart-b2851ad3-631b-4132-a3e3-d70125834b44 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1078828969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_test.1078828969 |
| Directory | /workspace/24.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/25.prim_lfsr_test.506472686 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 167773010505 ps |
| CPU time | 280.27 seconds |
| Started | Apr 28 01:43:26 AM PDT 22 |
| Finished | Apr 28 01:54:09 AM PDT 22 |
| Peak memory | 142756 kb |
| Host | smart-c057e155-1e5d-4131-9498-0c969cbfaa88 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=506472686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_test.506472686 |
| Directory | /workspace/25.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/26.prim_lfsr_test.877766889 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 167773213050 ps |
| CPU time | 302.26 seconds |
| Started | Apr 28 01:44:03 AM PDT 22 |
| Finished | Apr 28 01:55:27 AM PDT 22 |
| Peak memory | 142848 kb |
| Host | smart-6041cd59-b273-4d17-896a-7b39f68f275f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=877766889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_test.877766889 |
| Directory | /workspace/26.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/27.prim_lfsr_test.2865470485 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 167773002961 ps |
| CPU time | 297.53 seconds |
| Started | Apr 28 01:41:34 AM PDT 22 |
| Finished | Apr 28 01:53:02 AM PDT 22 |
| Peak memory | 142804 kb |
| Host | smart-23f042ef-74be-4e3f-96f4-09e2a4deed3b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2865470485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_test.2865470485 |
| Directory | /workspace/27.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/28.prim_lfsr_test.3748280388 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 167773179501 ps |
| CPU time | 287.57 seconds |
| Started | Apr 28 01:41:11 AM PDT 22 |
| Finished | Apr 28 01:51:49 AM PDT 22 |
| Peak memory | 142804 kb |
| Host | smart-b20f8bc6-8923-42b2-9380-88611a60c75d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3748280388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_test.3748280388 |
| Directory | /workspace/28.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/29.prim_lfsr_test.218943339 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 167773315569 ps |
| CPU time | 292.7 seconds |
| Started | Apr 28 01:42:41 AM PDT 22 |
| Finished | Apr 28 01:53:34 AM PDT 22 |
| Peak memory | 142740 kb |
| Host | smart-e909e765-70ca-4e49-8850-b0c2f8431981 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=218943339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_test.218943339 |
| Directory | /workspace/29.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/3.prim_lfsr_test.1636228770 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 167773142626 ps |
| CPU time | 267.22 seconds |
| Started | Apr 28 01:44:21 AM PDT 22 |
| Finished | Apr 28 01:54:13 AM PDT 22 |
| Peak memory | 142912 kb |
| Host | smart-36f31a2a-81b8-4d8d-b7f4-3a7ecab41a88 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1636228770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_test.1636228770 |
| Directory | /workspace/3.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/30.prim_lfsr_test.1525993268 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 167773078645 ps |
| CPU time | 291.59 seconds |
| Started | Apr 28 01:44:02 AM PDT 22 |
| Finished | Apr 28 01:55:05 AM PDT 22 |
| Peak memory | 142928 kb |
| Host | smart-5b69df5d-8166-40f7-8e5c-5a449d141384 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1525993268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_test.1525993268 |
| Directory | /workspace/30.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/31.prim_lfsr_test.3448572587 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 167773035420 ps |
| CPU time | 263.37 seconds |
| Started | Apr 28 01:44:22 AM PDT 22 |
| Finished | Apr 28 01:54:24 AM PDT 22 |
| Peak memory | 142928 kb |
| Host | smart-9053b57d-9249-476e-8c94-369ad0f8147e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3448572587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_test.3448572587 |
| Directory | /workspace/31.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/32.prim_lfsr_test.3260891854 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 167773343547 ps |
| CPU time | 329.68 seconds |
| Started | Apr 28 01:44:26 AM PDT 22 |
| Finished | Apr 28 01:56:42 AM PDT 22 |
| Peak memory | 142912 kb |
| Host | smart-4e798129-aaba-41e9-8e06-3898135f64e8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3260891854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_test.3260891854 |
| Directory | /workspace/32.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/33.prim_lfsr_test.1681759266 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 167773221216 ps |
| CPU time | 280.5 seconds |
| Started | Apr 28 01:39:03 AM PDT 22 |
| Finished | Apr 28 01:49:59 AM PDT 22 |
| Peak memory | 142800 kb |
| Host | smart-822b9db3-80f2-4dfc-b3b2-5f0d92877200 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1681759266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_test.1681759266 |
| Directory | /workspace/33.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/34.prim_lfsr_test.2595077614 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 167773048168 ps |
| CPU time | 312.99 seconds |
| Started | Apr 28 01:39:50 AM PDT 22 |
| Finished | Apr 28 01:51:38 AM PDT 22 |
| Peak memory | 142804 kb |
| Host | smart-3bc906ec-5fdc-4910-b216-c650063eb96a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2595077614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_test.2595077614 |
| Directory | /workspace/34.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/35.prim_lfsr_test.3170347962 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 167773007800 ps |
| CPU time | 275.18 seconds |
| Started | Apr 28 01:43:52 AM PDT 22 |
| Finished | Apr 28 01:54:30 AM PDT 22 |
| Peak memory | 142876 kb |
| Host | smart-4b91fd78-01da-44da-baea-d6802d6a035e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3170347962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_test.3170347962 |
| Directory | /workspace/35.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/36.prim_lfsr_test.364526843 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 167773091978 ps |
| CPU time | 301.6 seconds |
| Started | Apr 28 01:43:37 AM PDT 22 |
| Finished | Apr 28 01:55:03 AM PDT 22 |
| Peak memory | 142752 kb |
| Host | smart-c0263cee-9ebc-4e4a-91e7-44ac15e4c141 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=364526843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_test.364526843 |
| Directory | /workspace/36.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/37.prim_lfsr_test.1488897272 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 167772891753 ps |
| CPU time | 298.01 seconds |
| Started | Apr 28 01:39:49 AM PDT 22 |
| Finished | Apr 28 01:50:58 AM PDT 22 |
| Peak memory | 142800 kb |
| Host | smart-a4c80e11-3f12-456b-91d5-86b83e42a4e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1488897272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_test.1488897272 |
| Directory | /workspace/37.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/38.prim_lfsr_test.2880105433 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 167772872916 ps |
| CPU time | 271.25 seconds |
| Started | Apr 28 01:42:13 AM PDT 22 |
| Finished | Apr 28 01:52:30 AM PDT 22 |
| Peak memory | 142816 kb |
| Host | smart-110cb542-0e25-4866-810f-69c695dc1553 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2880105433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_test.2880105433 |
| Directory | /workspace/38.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/39.prim_lfsr_test.2898085258 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 167773070358 ps |
| CPU time | 303.44 seconds |
| Started | Apr 28 01:43:59 AM PDT 22 |
| Finished | Apr 28 01:55:04 AM PDT 22 |
| Peak memory | 142928 kb |
| Host | smart-b7b4a53d-0618-4c1a-b10c-0a34c4194746 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2898085258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_test.2898085258 |
| Directory | /workspace/39.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/4.prim_lfsr_test.1632895298 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 167772970604 ps |
| CPU time | 286.19 seconds |
| Started | Apr 28 01:39:23 AM PDT 22 |
| Finished | Apr 28 01:49:58 AM PDT 22 |
| Peak memory | 142820 kb |
| Host | smart-ea70b53d-6a69-4e28-b003-21a6305345b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1632895298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_test.1632895298 |
| Directory | /workspace/4.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/40.prim_lfsr_test.905426664 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 167773205299 ps |
| CPU time | 271.53 seconds |
| Started | Apr 28 01:44:22 AM PDT 22 |
| Finished | Apr 28 01:54:26 AM PDT 22 |
| Peak memory | 142740 kb |
| Host | smart-27c66db0-2715-4b8b-abbc-0ce0bcea93a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=905426664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_test.905426664 |
| Directory | /workspace/40.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/41.prim_lfsr_test.876472761 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 167773000681 ps |
| CPU time | 316.28 seconds |
| Started | Apr 28 01:42:54 AM PDT 22 |
| Finished | Apr 28 01:54:45 AM PDT 22 |
| Peak memory | 142740 kb |
| Host | smart-6bd85ca8-e47f-43c1-87a9-c3e97354b709 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=876472761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_test.876472761 |
| Directory | /workspace/41.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/42.prim_lfsr_test.1394973030 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 167772992084 ps |
| CPU time | 319.71 seconds |
| Started | Apr 28 01:41:25 AM PDT 22 |
| Finished | Apr 28 01:53:30 AM PDT 22 |
| Peak memory | 142784 kb |
| Host | smart-6423521c-133d-4fdf-9f59-f5e3dd1303ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1394973030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_test.1394973030 |
| Directory | /workspace/42.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/43.prim_lfsr_test.2364340783 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 167773134319 ps |
| CPU time | 310.46 seconds |
| Started | Apr 28 01:43:51 AM PDT 22 |
| Finished | Apr 28 01:55:28 AM PDT 22 |
| Peak memory | 142928 kb |
| Host | smart-6135f967-c243-4e34-8a8b-dc6d5b17ae0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2364340783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_test.2364340783 |
| Directory | /workspace/43.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/44.prim_lfsr_test.2691103424 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 167773126799 ps |
| CPU time | 259.31 seconds |
| Started | Apr 28 01:44:26 AM PDT 22 |
| Finished | Apr 28 01:54:05 AM PDT 22 |
| Peak memory | 142792 kb |
| Host | smart-ce7f11dc-0347-48f2-8618-704e050f70c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2691103424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_test.2691103424 |
| Directory | /workspace/44.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/45.prim_lfsr_test.3653240123 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 167773292996 ps |
| CPU time | 304.41 seconds |
| Started | Apr 28 01:41:55 AM PDT 22 |
| Finished | Apr 28 01:53:20 AM PDT 22 |
| Peak memory | 142804 kb |
| Host | smart-733a4f98-bcc3-4fe7-8466-409feefd4d8b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3653240123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_test.3653240123 |
| Directory | /workspace/45.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/46.prim_lfsr_test.2340288667 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 167772858719 ps |
| CPU time | 294.3 seconds |
| Started | Apr 28 01:39:39 AM PDT 22 |
| Finished | Apr 28 01:50:41 AM PDT 22 |
| Peak memory | 142780 kb |
| Host | smart-07f44e90-a8f7-47f1-b3d0-a9ee6d9b219a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2340288667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_test.2340288667 |
| Directory | /workspace/46.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/47.prim_lfsr_test.3995055219 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 167772976050 ps |
| CPU time | 263.88 seconds |
| Started | Apr 28 01:39:05 AM PDT 22 |
| Finished | Apr 28 01:48:49 AM PDT 22 |
| Peak memory | 142784 kb |
| Host | smart-4253e453-17f3-4398-a41c-ae2a9c4b2883 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3995055219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_test.3995055219 |
| Directory | /workspace/47.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/48.prim_lfsr_test.4140993623 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 167772942328 ps |
| CPU time | 283.64 seconds |
| Started | Apr 28 01:44:03 AM PDT 22 |
| Finished | Apr 28 01:55:02 AM PDT 22 |
| Peak memory | 142928 kb |
| Host | smart-6afd5f1b-a9ae-4992-be16-8d9ed78ea511 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4140993623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_test.4140993623 |
| Directory | /workspace/48.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/49.prim_lfsr_test.956420568 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 167773114818 ps |
| CPU time | 283.79 seconds |
| Started | Apr 28 01:39:03 AM PDT 22 |
| Finished | Apr 28 01:49:57 AM PDT 22 |
| Peak memory | 142772 kb |
| Host | smart-eedc116e-2745-4dfc-88a0-41444ef919eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=956420568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_test.956420568 |
| Directory | /workspace/49.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/5.prim_lfsr_test.4192576620 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 167773203660 ps |
| CPU time | 280.91 seconds |
| Started | Apr 28 01:41:17 AM PDT 22 |
| Finished | Apr 28 01:51:47 AM PDT 22 |
| Peak memory | 142820 kb |
| Host | smart-7b1c72fb-00ec-4ec3-ad46-2ad6f99b4c87 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4192576620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_test.4192576620 |
| Directory | /workspace/5.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/6.prim_lfsr_test.4074765061 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 167773316595 ps |
| CPU time | 282.6 seconds |
| Started | Apr 28 01:44:26 AM PDT 22 |
| Finished | Apr 28 01:54:53 AM PDT 22 |
| Peak memory | 142788 kb |
| Host | smart-963cd48e-7aa1-451b-a09d-838179b3f510 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4074765061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_test.4074765061 |
| Directory | /workspace/6.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/7.prim_lfsr_test.2485161323 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 167773221989 ps |
| CPU time | 272.3 seconds |
| Started | Apr 28 01:44:25 AM PDT 22 |
| Finished | Apr 28 01:54:30 AM PDT 22 |
| Peak memory | 142800 kb |
| Host | smart-d915d233-fe75-4b4e-9586-52c3346ed656 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2485161323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_test.2485161323 |
| Directory | /workspace/7.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/8.prim_lfsr_test.2283369362 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 167772998780 ps |
| CPU time | 283.97 seconds |
| Started | Apr 28 01:43:49 AM PDT 22 |
| Finished | Apr 28 01:54:41 AM PDT 22 |
| Peak memory | 143200 kb |
| Host | smart-9b47f007-69bb-484b-bc5f-490bc527a965 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2283369362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_test.2283369362 |
| Directory | /workspace/8.prim_lfsr_test/out |
| Test location | /workspace/coverage/prim_lfsr_dw_24/9.prim_lfsr_test.901802795 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 167773084226 ps |
| CPU time | 284.68 seconds |
| Started | Apr 28 01:44:02 AM PDT 22 |
| Finished | Apr 28 01:54:53 AM PDT 22 |
| Peak memory | 142928 kb |
| Host | smart-7728ea81-033d-4747-9765-916964a40d6f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=901802795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_test.901802795 |
| Directory | /workspace/9.prim_lfsr_test/out |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |