PRIM_LFSR Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 TOTAL 0 0 --
V2 TOTAL 0 0 --
V2S TOTAL 0 0 --
V3 TOTAL 0 0 --
Unmapped tests prim_lfsr_gal_smoke 2.140s 1.553ms 50 50 100.00
prim_lfsr_fib_test 3.931m 336.694ms 50 50 100.00
prim_lfsr_fib_smoke 2.100s 1.504ms 50 50 100.00
prim_lfsr_gal_test 3.875m 336.626ms 50 50 100.00
TOTAL 200 200 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 4 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT
98.31 100.00 96.55 100.00 -- 100.00 95.00

Past Results