PRIM_PRESENT Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: `042415198f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1		TOTAL			0	0	--
V2		TOTAL			0	0	--
V2S		TOTAL			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	prim_present_test	51.120s	14.871ms	42	50	84.00
		TOTAL			42	50	84.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	90.41	100.00	98.73	--	100.00	100.00

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 8 failures:

Test prim_present_test has 8 failures.

16.prim_present_test.49878929527670311173278638456758623436270513868817135908483254383751307992485
Log /container/opentitan-public/scratch/os_regression/prim_present-sim-vcs/16.prim_present_test/latest/run.log

  [make]: simulate
  cd /workspace/16.prim_present_test/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300503973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1300503973
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  7 12:31 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

17.prim_present_test.69190325128559728021180071418438386067188060500149503923012956165494206269868
Log /container/opentitan-public/scratch/os_regression/prim_present-sim-vcs/17.prim_present_test/latest/run.log

  [make]: simulate
  cd /workspace/17.prim_present_test/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463191980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1463191980
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  7 12:30 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

... and 6 more failures.