042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | TOTAL | 0 | 0 | -- | |||
| V2 | TOTAL | 0 | 0 | -- | |||
| V2S | TOTAL | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | prim_prince_test | 1.039m | 3.615ms | 433 | 500 | 86.60 | |
| TOTAL | 433 | 500 | 86.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
|---|---|---|---|---|---|---|
| 100.00 | 100.00 | 100.00 | 100.00 | -- | 100.00 | 100.00 |
Exit reason: Error: User command failed Job returned non-zero exit code has 66 failures:
5.prim_prince_test.73260013234791181018467852664679241797346121257450966595176219509327276087126
Log /container/opentitan-public/scratch/os_regression/prim_prince-sim-vcs/5.prim_prince_test/latest/run.log
[make]: simulate
cd /workspace/5.prim_prince_test/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231544662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_prince_test.231544662
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:50 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
7.prim_prince_test.76511111471566754008127444634423093787910325537753670497826778727815525193639
Log /container/opentitan-public/scratch/os_regression/prim_prince-sim-vcs/7.prim_prince_test/latest/run.log
[make]: simulate
cd /workspace/7.prim_prince_test/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630192551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_prince_test.3630192551
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:50 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 64 more failures.
Job prim_prince-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
187.prim_prince_test.50730765531891361769761662804200418591209536662627944162237937176501991666779
Log /container/opentitan-public/scratch/os_regression/prim_prince-sim-vcs/187.prim_prince_test/latest/run.log
Job ID: smart:b3e0a633-eb96-454b-b5b7-a56253fbf8fc